CN116043180A

CN116043180A - Wafer production fixture

Info

Publication number: CN116043180A
Application number: CN202211726232.6A
Authority: CN
Inventors: 欧阳华; 欧阳晟; 陈伟文; 陈炀
Original assignee: Guangzhou Jingyou Electronic Technology Co ltd
Current assignee: Guangzhou Jingyou Electronic Technology Co ltd
Priority date: 2022-12-29
Filing date: 2022-12-29
Publication date: 2023-05-02

Abstract

The invention relates to the field of clamps, in particular to a wafer production clamp, which comprises an upper clamping plate, a middle plate and a lower clamping plate, wherein the middle plate is clamped between the upper clamping plate and the lower clamping plate to form a plurality of wafer clamping units, and the specific structure of each wafer clamping unit is as follows: the middle plate is provided with a wafer cavity and a middle conducting cavity, and the middle conducting cavity comprises a first type middle conducting cavity and a second type middle conducting cavity; an upper electrode cavity and an upper conducting cavity are arranged on the upper clamping plate; the lower clamping plate is provided with a lower electrode cavity and a lower conducting cavity; at least one part of the upper electrode cavity, the first-type middle conducting cavity and the lower conducting cavity form an upper channel and a lower channel; at least a part of the lower electrode cavity, the second type intermediate conducting cavity and the upper conducting cavity form a lower upper channel. The method is used for solving the problems of improving the coating accuracy and operation automation of the wafer, and achieving the effects of multi-wafer model, improving the coating accuracy, improving the operation efficiency, simplifying the working procedure and reducing the cost.

Description

Wafer production fixture

Technical Field

The invention relates to the field of clamps, in particular to a wafer production clamp.

Background

With the rapid development of chips, the manufacture of semiconductor components is also becoming an industry requiring rapid expansion. The quartz crystal resonator is called quartz crystal or crystal oscillator for short, and is used as a necessary product for providing stable time-frequency signals in a circuit and enabling semiconductor components to uniformly work, and the manufacturing process requirement is quite high. The crystal oscillator is a resonant device made by using piezoelectric effect of quartz crystal, and its basic structure is that a thin sheet (the thin sheet is called wafer for short) is cut from a quartz crystal according to a certain azimuth angle, and the thin sheet can be square, rectangular or circular, etc. on its two correspondent surfaces a silver layer is coated as electrodes, and on each electrode a lead wire is welded on the pin, and a package shell is added so as to obtain the invented crystal oscillator. Since quartz crystals are ionic crystals, which are regularly distributed in the crystal lattice, when they are mechanically deformed, for example, stretched or compressed, they can generate an electric polarization phenomenon, which becomes a piezoelectric phenomenon. The natural frequency of the piezoelectric effect of the quartz crystal depends not only on the geometric dimension and the cutting type, but also on the thickness of the wafer, when the thickness of the wafer is increased by plating a certain film layer on the wafer, the natural frequency of the wafer correspondingly attenuates, and the effect of the quartz crystal is a mass load effect.

In order to realize accurate coating of wafers in the prior art, workers are required to place the wafers by means of a manual suction pen, manual operation leads to low efficiency, but if the manual operation is changed into mechanical hand to adsorb the wafers and automatically place the wafers, the mechanical hand is difficult to accurately place the wafers in the positioning holes because the diameter of the positioning holes is very small, so that the automation of accurate coating operation of the wafers becomes a difficult problem in the prior art. In the manufacturing process of the crystal oscillator, the thickness of the wafer directly affects the fundamental frequency, so how to simplify the steps of silver coating, wire bonding, film plating and the like and ensure the thickness and the flatness of the wafer is a problem to be solved in the field.

How to achieve the effect of simplifying the crystal oscillator manufacturing process and reducing the manufacturing cost through the design of the wafer clamp is the technical problem to be solved by the scheme.

Disclosure of Invention

The present invention is directed to overcoming at least one of the above-mentioned drawbacks (shortcomings) of the prior art, and providing a wafer production fixture for solving the problems of simplifying the manufacturing process of crystal oscillator, reducing the manufacturing cost and improving the plating accuracy and operation automation of wafers.

The technical scheme adopted by the invention is that the wafer production clamp comprises an upper clamp plate, a middle plate and a lower clamp plate, wherein the middle plate is clamped between the upper clamp plate and the lower clamp plate, a plurality of wafer clamping units are formed between the upper clamp plate and the lower clamp plate, the wafer clamping units are distributed in multiple areas, each area comprises an array formed by arranging a plurality of wafer clamping units, and the specific structure of each wafer clamping unit is as follows: the middle plate is provided with a wafer cavity for accommodating a wafer and a plurality of middle conducting cavities which are distributed around the wafer cavity and are communicated with the wafer cavity, and the middle conducting cavities comprise a first type middle conducting cavity and a second type middle conducting cavity; an upper electrode cavity for forming an upper electrode plate by electroplating and an upper conducting cavity which is separated from the upper electrode cavity are formed on the upper clamping plate, and the upper conducting cavity corresponds to the second-class middle conducting cavity; the lower clamping plate is provided with a lower electrode cavity for forming a lower electrode plate through electroplating and a lower conducting cavity which is arranged separately from the lower electrode cavity, and the lower conducting cavity corresponds to the first type of intermediate conducting cavity; at least one part of the upper electrode cavity is communicated with the first-type middle conducting cavity and the lower conducting cavity to form an upper channel and a lower channel; at least one part of the lower electrode cavity is communicated with the second-type middle conducting cavity and the upper conducting cavity to form a lower upper channel.

Further, the upper electrode cavity comprises an upper main cavity and an upper extension cavity communicated with the upper main cavity, the area of the upper main cavity is smaller than that of the wafer cavity, the middle plate is clamped between the upper clamping plate and the lower clamping plate, the upper main cavity does not exceed the wafer cavity, and the upper extension cavity is communicated with the first type middle conducting cavity and the lower conducting cavity to form an upper channel and a lower channel; the lower electrode cavity comprises a lower main cavity and a lower extension cavity communicated with the lower main cavity, the area of the lower main cavity is smaller than that of the wafer cavity, the middle plate is clamped between the upper clamping plate and the lower clamping plate, the lower main cavity does not exceed the wafer cavity, and the lower extension cavity is communicated with the second-type middle conducting cavity and the upper conducting cavity to form a lower upper channel. The fixture is beneficial to directly forming the lead between the fixtures, so that the step of welding the lead in the wafer manufacturing process is reduced, the wafer manufacturing efficiency is effectively improved, and the wafer manufacturing cost is reduced.

Further, the outer contours of the upper extension cavity, the first type middle conducting cavity and the lower conducting cavity are overlapped up and down to form an upper channel and a lower channel with the same cross section; and the outer contours of the lower extension cavity, the second type middle conducting cavity and the upper conducting cavity are overlapped up and down to form a lower upper channel with the same cross section. The electron potential energy is not changed when electrons flow in the lead.

Further, the area of the upper main cavity or the lower main cavity accounts for 1/2-9/10 of the area of the wafer cavity. The service life of the lead wires in the wafer is prolonged.

Further, the upper and lower main chamber edges do not coincide with wafer chamber edges. The influence of the lead on the fundamental frequency of the chip is reduced.

Further, the shape and layout of the upper electrode cavity and the upper conducting cavity are the same as those of the lower electrode cavity and the lower conducting cavity, and the directions of the upper electrode cavity and the upper conducting cavity are opposite or symmetrical. The positive electrode lead and the negative electrode lead are identical in shape, opposite or symmetrical in direction, so that the universality of the leads is improved, the crystal oscillator with different specifications is adapted, the use frequency of the clamp is improved, and the production efficiency of the clamp is improved.

Further, the wafer cavity and the middle conducting cavity are rectangular, the middle conducting cavity comprises four corners which are symmetrically distributed in the wafer cavity and are partially overlapped with the wafer cavity, and the area of the overlapped part accounts for 1/4-1/2 of the area of the middle conducting cavity; the upper conducting cavity and the lower conducting cavity are rectangular, and the areas of the upper conducting cavity and the lower conducting cavity are the same as and correspond to those of the middle conducting cavity; the upper extension cavity is L-shaped and comprises a vertical part and a transverse part which are communicated with the upper main cavity, and the area of the transverse part is the same as and corresponds to that of the middle conduction cavity; the lower extension cavity is L-shaped and comprises a vertical part and a transverse part which are communicated with the lower main cavity, and the area of the transverse part is the same as and corresponds to that of the middle conduction cavity; the upper extension cavity and the upper conduction cavity are diagonally arranged on the upper main cavity, the lower extension cavity and the lower conduction cavity are diagonally arranged on the lower main cavity, the upper electrode cavity and the upper conduction cavity are identical to the lower electrode cavity and the lower conduction cavity in shape and layout, and are arranged in a central symmetry manner of the wafer cavity, so that the first type middle conduction cavity forming the upper and lower channels and the second type middle conduction cavity forming the lower upper channels are diagonally distributed on the wafer cavity. The wafer is suitable for different frequencies, and the production efficiency of the clamp is improved.

Further, the wafer cavity and the middle conducting cavity are rectangular, the middle conducting cavity comprises two corners which are adjacently distributed in the wafer cavity and are partially overlapped with the wafer cavity, and the area of the overlapped part accounts for 1/4-1/2 of the area of the middle conducting cavity; the upper conducting cavity and the lower conducting cavity are rectangular, and the areas of the upper conducting cavity and the lower conducting cavity are the same as and correspond to those of the middle conducting cavity; the upper extension cavity is L-shaped and comprises a vertical part and a transverse part which are communicated with the upper main cavity, and the area of the transverse part is the same as and corresponds to that of the middle conduction cavity; the lower extension cavity is L-shaped and comprises a vertical part and a transverse part which are communicated with the lower main cavity, and the area of the transverse part is the same as and corresponds to that of the middle conduction cavity; the upper extension cavity and the upper conduction cavity are arranged at adjacent angles on the upper main cavity, the lower extension cavity and the lower conduction cavity are arranged at adjacent angles on the lower main cavity, the upper electrode cavity and the upper conduction cavity are identical to the lower electrode cavity and the lower conduction cavity in shape and layout, and are symmetrically arranged with the central axis of the wafer cavity, so that the first type middle conduction cavity forming the upper and lower channels and the second type middle conduction cavity forming the lower upper channels are distributed at adjacent angles on the wafer cavity (230). The wafer is suitable for different frequencies, and the production efficiency of the clamp is improved.

Further, the other two corners of the wafer cavity are provided with guide grooves communicated with the wafer cavity. Is beneficial to being suitable for the crystal oscillator which needs a plurality of leads and improves the production efficiency of the clamp.

Further, the wafer cavity and the middle conducting cavity are rectangular, the middle conducting cavity comprises four corners which are symmetrically distributed in the wafer cavity and are partially overlapped with the wafer cavity, and the area of the overlapped part accounts for 1/4-1/2 of the area of the middle conducting cavity; comprises two upper conducting cavities arranged adjacently, two lower conducting cavities arranged adjacently, two upper extending cavities arranged adjacently and two lower extending cavities arranged adjacently; the upper conducting cavity and the lower conducting cavity are rectangular, and the areas of the upper conducting cavity and the lower conducting cavity are the same as and correspond to those of the middle conducting cavity; the upper extension cavity is L-shaped and comprises a vertical part and a transverse part which are communicated with the upper main cavity, and the area of the transverse part is the same as and corresponds to that of the middle conduction cavity; the lower extension cavity is L-shaped and comprises a vertical part and a transverse part which are communicated with the lower main cavity, and the area of the transverse part is the same as and corresponds to that of the middle conduction cavity; the upper extension cavity and the upper conduction cavity are diagonally arranged on the upper main cavity, the lower extension cavity and the lower conduction cavity are diagonally arranged on the lower main cavity, the upper electrode cavity and the upper conduction cavity are identical to the lower electrode cavity and the lower conduction cavity in shape and layout, and are symmetrically arranged on the central axis of the wafer cavity, so that the two first-type middle conduction cavities forming the upper and lower channels and the two second-type middle conduction cavities forming the lower upper channels are axisymmetrically distributed on the wafer cavity. The wafer is suitable for different frequencies, and the production efficiency of the clamp is improved.

Compared with the prior art, the invention has the beneficial effects that: the through hole clamp capable of placing the wafer is formed by utilizing the multi-layer electrode plate, so that the effects of multi-wafer pattern, automatic placement of the wafer, improvement of the film plating accuracy of the wafer, improvement of the operation automation efficiency, simplification of the manufacturing process and reduction of the manufacturing cost are realized.

Drawings

FIG. 1 is an enlarged schematic view of a wafer cavity structure according to the present invention.

Fig. 2 is a plan view of the upper electrode of the first set of clamps according to a preferred embodiment of the present invention.

Fig. 3 is a plan view of the lower electrode of the first set of clamps according to a preferred embodiment of the present invention.

Fig. 4 is a plan view of a middle electrode of a first set of clamps according to a preferred embodiment of the present invention.

Fig. 5 is a plan view of the upper electrode of the second set of clamps according to a preferred embodiment of the present invention.

Fig. 6 is a plan view of the lower electrode of the second set of clamps according to a preferred embodiment of the present invention.

Fig. 7 is a plan view of a middle electrode of a second set of clamps according to a preferred embodiment of the present invention.

Fig. 8 is a plan view of the upper electrode of the third set of clamps according to a preferred embodiment of the present invention.

Fig. 9 is a plan view of the lower electrode of the third set of clamps according to a preferred embodiment of the present invention.

Fig. 10 is a plan view of a middle electrode of a third set of clamps according to a preferred embodiment of the present invention.

Fig. 11 is a plan view of the upper electrode of the fourth set of clamps according to a preferred embodiment of the present invention.

Fig. 12 is a plan view of the lower electrode of the fourth set of clamps according to a preferred embodiment of the present invention.

Fig. 13 is a plan view of a middle electrode of a fourth set of clamps according to a preferred embodiment of the present invention.

The attached drawings are used for identifying and describing: upper clamping plate 100, upper electrode cavity 110, upper main cavity 111, upper extension cavity 112, upper conduction cavity 120, middle plate 200, first type middle conduction cavity 210, second type middle conduction cavity 220, wafer cavity 230, lower clamping plate 300, lower electrode cavity 310, lower main cavity 311, lower extension cavity 312, lower conduction cavity 320.

Detailed Description

The drawings are for illustrative purposes only and are not to be construed as limiting the invention. For better illustration of the following embodiments, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the actual product dimensions; it will be appreciated by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

Example 1

As shown in fig. 1, the wafer production jig of the present embodiment is used for clamping a wafer for a double-anchor silver-plated electrode layer, and is divided into three layers, namely an upper clamping plate 100, a middle plate 200 and a lower clamping plate 300, wherein the thickness of each of the upper clamping plate 100 and the lower clamping plate 300 is 0.15mm, and the thickness of the middle plate 200 is 0.07mm. The middle plate 300 is clamped between the upper clamping plate 100 and the lower clamping plate 300, and a plurality of wafer clamping units are formed therebetween, the plurality of wafer clamping units are distributed in a plurality of areas, each area comprises an array formed by arranging a plurality of wafer clamping units, wherein each wafer clamping unit has the following specific structure: the middle plate 200 is provided with a wafer cavity 230 for accommodating a wafer and a plurality of middle conducting cavities which are distributed around the wafer cavity 230 and are communicated with the wafer cavity 230, wherein the middle conducting cavities comprise a first type middle conducting cavity 210 and a second type middle conducting cavity 220; an upper electrode cavity 110 for forming an upper electrode plate by electroplating and an upper conducting cavity 120 which is separated from the upper electrode cavity 110 are formed on the upper clamping plate 100, and the upper conducting cavity 120 corresponds to the second-type middle conducting cavity 220; a lower electrode cavity 310 for forming a lower electrode plate by electroplating and a lower conducting cavity 320 which is separated from the lower electrode cavity 310 are formed on the lower clamping plate 300, and the lower conducting cavity 320 corresponds to the first type middle conducting cavity 210; at least a portion of the upper electrode cavity 110 communicates with the first type intermediate conducting cavity 210 and the lower conducting cavity 320 to form an upper and lower channel 410; at least a portion of the lower electrode cavity 310 communicates with the second type intermediate pass-through cavity 220 and the upper pass-through cavity 120 to form a lower upper channel 420.

The upper electrode cavity 110 includes an upper main cavity 111 and an upper extension cavity 112, the upper main cavity 111 is smaller than the wafer cavity 230 in area, the middle plate 200 is clamped between the upper clamping plate 100 and the lower clamping plate 300, the upper main cavity 111 does not exceed the wafer cavity 230, the upper extension cavity 112 is communicated with the first type middle conducting cavity 210 and the lower conducting cavity 320 to form an upper and lower channel 410, the lower electrode cavity 310 includes a lower main cavity 311 and a lower extension cavity 312 communicated with the lower main cavity 311, the lower main cavity 311 is smaller than the wafer cavity 230, the middle plate 200 is clamped between the upper clamping plate 100 and the lower clamping plate 300, the lower main cavity 311 does not exceed the wafer cavity 230, and the lower extension cavity 312 is communicated with the second type middle conducting cavity 220 and the upper conducting cavity 120 to form a lower upper channel 420. The upper and lower channels 410 in this embodiment are used to limit the flow of silver of the electrode material to form a positive lead in communication with the die cavity 230, and the lower and upper channels 420 are used to limit the flow of silver of the electrode material to form a negative lead in communication with the die 230.

The upper extension cavity 112, the first type intermediate conducting cavity 210 and the lower conducting cavity 320 are partially overlapped with each other in the outer contour to form an upper channel 410 and a lower channel 410 with the same cross section; the lower extension cavities 312, the second type intermediate conducting cavities 220 and the upper conducting cavities 120 are partially overlapped on top of each other in their outer contours, forming lower and upper channels 420 having the same cross section. In this embodiment, since the cross-section of the end portion of the upper and lower channels 410 is the same as the cross-section area of the root portion thereof, when the silver coating electrode material flows through the upper and lower channels 410, the width of the positive electrode lead formed by the silver coating electrode material from the end portion to the root portion is consistent, the cross-section area is not changed, and after the current is applied, electrons flow from the end portion to the root portion in the positive electrode lead, and the potential energy is not changed.

The area of the upper main chamber 111 or the lower main chamber 311 occupies 1/2 to 9/10 of the area of the wafer chamber 230. In this embodiment, the area of the upper main chamber 111 and the area of the lower main chamber 311 are equal, but are slightly smaller than the area of the wafer chamber 230. The size of the area of the upper main cavity 111 and the lower main cavity 311 replaces the bond point size of two wires in the prior art, but it increases the life of wire bonding.

The edges of the upper main cavity 111 and the lower main cavity 311 do not coincide with the edges of the wafer cavity 230. In this embodiment, the connecting edge of the upper main chamber 111 and the wafer chamber 230 is covered by the vertical portion and the lateral portion of the upper extension chamber 112, and the connecting edge of the lower main chamber 311 and the wafer chamber 230 is covered by the vertical portion and the lateral portion of the lower extension chamber 312, corresponding to the upper main chamber 111. When the edge of the upper main chamber 111 or the lower main chamber 311 coincides with the edge of the wafer chamber 230, the thickness of the wafer may be increased, thereby affecting the vibration of the wafer.

The upper electrode cavity 110 and the upper via cavity 120 are identical in shape and layout to the lower electrode cavity 310 and the lower via cavity 320, and are opposite or symmetrical. In this embodiment, as shown in fig. 2 to 4, the shapes and the layouts of the upper electrode cavity, the upper conducting cavity, the lower electrode cavity and the lower conducting cavity are the same, but the directions of the upper electrode cavity, the upper conducting cavity, the lower electrode cavity and the lower conducting cavity are diagonally symmetrical; as shown in fig. 5 to 7, the shapes and the layouts of the upper electrode cavity, the upper conducting cavity, the lower electrode cavity and the lower conducting cavity are the same, but the directions of the upper electrode cavity, the upper conducting cavity, the lower electrode cavity and the lower conducting cavity are up-down symmetrical; as shown in fig. 8 to 10, the shapes and the layouts of the upper electrode cavity, the upper conducting cavity, the lower electrode cavity and the lower conducting cavity are the same, but the directions of the upper electrode cavity, the upper conducting cavity, the lower electrode cavity and the lower conducting cavity are bilaterally symmetrical; as shown in fig. 11 to 13, the shapes and the layouts of the upper electrode cavity, the upper conducting cavity, the lower electrode cavity and the lower conducting cavity are the same, but the directions of the upper electrode cavity, the upper conducting cavity, the lower electrode cavity and the lower conducting cavity are up-down symmetrical.

The wafer cavity 230 and the middle conducting cavity are rectangular, the middle conducting cavity comprises four corners symmetrically distributed in the wafer cavity 230 and is partially overlapped with the wafer cavity 230, and the area of the overlapped part accounts for 1/4-1/2 of the area of the middle conducting cavity; the upper main cavity 111 and the lower main cavity 311, the upper conducting cavity 120 and the lower conducting cavity 320 are rectangular, and the areas of the upper conducting cavity 120 and the lower conducting cavity 320 are the same as and correspond to those of the middle conducting cavity; the lower extension cavity 312 is L-shaped and comprises a vertical portion and a transverse portion which are communicated with the lower main cavity 311, and the area of the transverse portion is the same as and corresponds to that of the middle conduction cavity; the upper extension cavity 112 and the upper conduction cavity 120 are diagonally arranged on the upper main cavity 111, the lower extension cavity 312 and the lower conduction cavity 320 are diagonally arranged on the lower main cavity 311, and the upper electrode cavity 110 and the upper conduction cavity 120, the lower electrode cavity 310 and the lower conduction cavity 320 are in the same shape and layout, and are symmetrically arranged with respect to the center of the wafer cavity 230, so that the first type intermediate conduction cavity 210 forming the upper and lower channels 410 and the second type intermediate conduction cavity 220 forming the lower upper channels 420 are diagonally distributed on the wafer cavity 230. In this embodiment, when the wafer is subjected to mechanical pressure, the potential difference generated by the piezoelectric effect thereof is affected by the lead distance at the diagonal position. As shown in fig. 2 to 4, the leads of the die are located at diagonal positions, and the distance between the leads of the die is about 1.64mm from the diagonal of the die having a rectangular shape with a length of 1.3mm and a width of 1mm.

The wafer cavity 230 and the middle conducting cavity are rectangular, the middle conducting cavity comprises two corners which are adjacently distributed in the wafer cavity 230 and are partially overlapped with the wafer cavity (230), and the area of the overlapped part accounts for 1/4-1/2 of the area of the middle conducting cavity; the upper main cavity 111 and the lower main cavity 311, the upper conducting cavity 120 and the lower conducting cavity 320 are rectangular, and the areas of the upper conducting cavity 120 and the lower conducting cavity 320 are the same as and correspond to those of the middle conducting cavity; the upper extension cavity 112 is L-shaped and comprises a vertical portion and a transverse portion which are communicated with the upper main cavity 111, and the area of the transverse portion is the same as and corresponds to that of the middle conduction cavity; the lower extension cavity 312 is L-shaped and comprises a vertical portion and a transverse portion which are communicated with the lower main cavity 311, and the area of the transverse portion is the same as and corresponds to that of the middle conduction cavity; the upper extension cavity 112 and the upper conduction cavity 120 are disposed at adjacent angles on the upper main cavity 111, the lower extension cavity 312 and the lower conduction cavity 320 are disposed at adjacent angles on the lower main cavity 311, and the upper electrode cavity 110 and the upper conduction cavity 120, the lower electrode cavity 310 and the lower conduction cavity 320 are formed in the same shape and layout, and are symmetrically disposed with respect to the central axis of the wafer cavity 230, so that the first type intermediate conduction cavity 210 forming the upper and lower channels 410 and the second type intermediate conduction cavity 220 forming the lower upper channels 420 are distributed at adjacent angles on the wafer cavity 230. In this embodiment, as shown in fig. 5 to 7, the leads of the wafer are positioned at the adjacent corners of the long sides, and the distance between the leads is 1.3mm for the rectangular wafer having a length of 1.3mm and a width of 1mm.

The other two corners of the wafer cavity 230 are provided with guide grooves 231 communicating with the wafer cavity 230. In this embodiment, as shown in fig. 4 and 5, the guide groove is disposed at a long-side adjacent corner or a short-side adjacent corner of the wafer cavity, and the guide groove is used for introducing silver electrode material as two other leads of the wafer. So as to be suitable for the crystal oscillator requiring four pins.

The wafer cavity 230 and the middle conducting cavity are rectangular, the middle conducting cavity comprises four corners symmetrically distributed in the wafer cavity 230 and is partially overlapped with the wafer cavity 230, and the area of the overlapped part accounts for 1/4-1/2 of the area of the middle conducting cavity; comprising two adjacently disposed upper conductive lumens 120, two adjacently disposed lower conductive lumens 320, two adjacently disposed upper extension lumens 112, and two adjacently disposed lower extension lumens 312; the upper main cavity 111 and the lower main cavity 311, the upper conducting cavity 120 and the lower conducting cavity 320 are rectangular, and the areas of the upper conducting cavity 120 and the lower conducting cavity 320 are the same as and correspond to those of the middle conducting cavity; the upper extension cavity 112 is L-shaped and comprises a vertical portion and a transverse portion which are communicated with the upper main cavity 111, and the area of the transverse portion is the same as and corresponds to that of the middle conduction cavity; the lower extension cavity 312 is L-shaped and comprises a vertical portion and a transverse portion which are communicated with the lower main cavity 311, and the area of the transverse portion is the same as and corresponds to that of the middle conduction cavity; the upper extension cavity 112 and the upper conduction cavity 120 are diagonally arranged on the upper main cavity 111, the lower extension cavity 312 and the lower conduction cavity 320 are diagonally arranged on the lower main cavity 311, and the upper electrode cavity 110 and the upper conduction cavity 120, the lower electrode cavity 310 and the lower conduction cavity 320 are in the same shape and layout, and are symmetrically arranged on the central axis of the wafer cavity 230, so that the two first type middle conduction cavities 210 forming the upper and lower channels 410 and the two second type middle conduction cavities 220 forming the lower upper channels 220 are axisymmetrically distributed on the wafer cavity 230. In this embodiment, as shown in fig. 8 to 10, the leads of the wafer are positioned at the adjacent corners of the long sides, and the distance between the leads is 1.3mm for the rectangular wafer with the length of 1.3mm and the width of 1 mm; as shown in fig. 11 to 13, the leads of the die are located at short side adjacent angular positions with a lead distance of 1mm from the length of the die of a rectangle of 1.3mm in length and 1mm in width.

Example 2

In this embodiment, the electrode material of the wafer is silver, which is the first choice of electrode material because of its very low contact resistance and good plastic deformation, and the electrode type of the wafer is a double anchor, which focuses energy at the center of the wafer and maximizes the stability and lifetime of the wafer. The silver plating wafer has high stress film, such as Ni, cr, mo, zr, ni-Cr, ti, stainless steel, etc.

In order to ensure the life of the wafer, the edge of the wafer needs to be clamped by tweezers, the center of the wafer is not contacted by fingers, oil stains are avoided, and otherwise the vibration capability of the wafer is reduced. The wafer is soaked in the analytically pure solution for 1 min before being used, then the analytically pure solution is wiped clean by using a plastic tweezer clamp and using dust-free paper or clean silk, meanwhile, the clamp is wiped clean by using dust-free paper or clean silk dipped with alcohol, before the wafer is assembled, the wafer and dust possibly remained on the clamp are blown off by using a blowing ball, any particles or ash layer between the wafer and the clamp influence electronic contact, stress points are generated, so that the crystal vibration mode is changed, and the surface of the wafer is blown off again by using the blowing ball after the wafer is assembled, so that scattered dust is removed.

Thicker films can be deposited on the surface of the crystal oscillator seat after multiple film plating, and if the crystal oscillator seat is not removed, the test precision of the crystal oscillator sheet can be affected by reverse sputtering generated by ion bombardment. The film layer can be removed by sand blasting or sand sanding, then the film layer is soaked in alcohol for about 5 minutes, if the film layer can be cleaned by ultrasonic waves, the effect is better, and finally the film layer is put into an oven at 110 ℃ to be baked for 15 minutes, so that the film layer can be used.

In the process of depositing a coating film, the new wafer is replaced after the film layer on the wafer is plated to a certain thickness, because the thicker the film layer is, the lower the fundamental frequency of the crystal oscillator is, the more the fundamental frequency is, the frequency hopping phenomenon of the crystal oscillator is generated, the stable work cannot be realized, and if the deposition is continued, the vibration stopping phenomenon can be generated. In addition to the need to replace the wafer when the deposited film is too thick, the evaporation rate is obviously abnormal or the film is obviously peeled off or peeled off from the surface of the wafer, and the need to replace the wafer is also required. The cooling water is kept enough to ensure that the effect of the temperature of the crystal oscillator head is better in the range of 20-50 degrees.

It should be understood that the foregoing examples of the present invention are merely illustrative of the present invention and are not intended to limit the present invention to the specific embodiments thereof. Any modification, equivalent replacement, improvement, etc. that comes within the spirit and principle of the claims of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. Wafer production anchor clamps, including punch holder (100), intermediate lamella (200) and lower plate (300), intermediate lamella (200) are held in between punch holder (100) and lower plate (300) and form a plurality of wafer clamping units between them, and a plurality of wafer clamping units are multizone distribution, and every region includes the array that a plurality of wafer clamping units arrange and form, its characterized in that, every wafer clamping unit specific structure is as follows:

the middle plate (200) is provided with a wafer cavity (230) for accommodating a wafer and a plurality of middle conducting cavities which are distributed around the wafer cavity (230) and are communicated with the wafer cavity (230), and the middle conducting cavities comprise a first type middle conducting cavity (210) and a second type middle conducting cavity (220);

an upper electrode cavity (110) for forming an upper electrode plate through electroplating and an upper conducting cavity (120) which is separated from the upper electrode cavity (110) are formed on the upper clamping plate (100), and the upper conducting cavity (120) corresponds to the second-type intermediate conducting cavity (220);

a lower electrode cavity (310) for forming a lower electrode plate by electroplating and a lower conducting cavity (320) which is separated from the lower electrode cavity (310) are formed on the lower clamping plate (300), and the lower conducting cavity (320) corresponds to the first type of intermediate conducting cavity (210);

at least a portion of the upper electrode cavity (110) communicates with the first type intermediate conducting cavity (210) and the lower conducting cavity (320) to form an upper and lower channel (410);

at least a portion of the lower electrode cavity (310) communicates with the second type intermediate conducting cavity (220) and the upper conducting cavity (120) to form a lower upper channel (420).

2. The wafer production jig according to claim 1, wherein,

the upper electrode cavity (110) comprises an upper main cavity (111) and an upper extension cavity (112) communicated with the upper main cavity (111), the area of the upper main cavity (111) is smaller than that of the wafer cavity (230), the middle plate (200) is clamped between the upper clamping plate (100) and the lower clamping plate (300), the upper main cavity (111) does not exceed the wafer cavity (230), and the upper extension cavity (112) is communicated with the first type middle conducting cavity (210) and the lower conducting cavity (320) to form an upper channel and a lower channel (410);

the lower electrode cavity (310) comprises a lower main cavity (311) and a lower extension cavity (312) communicated with the lower main cavity (311), the area of the lower main cavity (311) is smaller than that of the wafer cavity (230), the middle plate (200) is clamped between the upper clamping plate (100) and the lower clamping plate (300), the lower main cavity (311) does not exceed the wafer cavity (230), and the lower extension cavity (312) is communicated with the second-type middle conduction cavity (220) and the upper conduction cavity (120) to form a lower upper channel (420).

3. The wafer production jig according to claim 2, wherein,

the upper extension cavity (112), the first-class middle conduction cavity (210) and the lower conduction cavity (320) are partially overlapped up and down in the outer contour to form an upper channel (410) and a lower channel with the same cross section;

the lower extension cavity (312), the second type intermediate conducting cavity (220) and the upper conducting cavity (120) are partially overlapped in an upper-lower mode to form a lower upper channel (420) with the same cross section.

4. Wafer production jig according to claim 2, wherein the upper main chamber (111) or the lower main chamber (311) occupies 1/2-9/10 of the area of the wafer chamber (230).

5. Wafer production jig according to claim 2, wherein the upper main chamber (111) and lower main chamber (311) edges do not coincide with wafer chamber (230) edges.

6. Wafer production jig according to claim 1, wherein the upper electrode cavity (110) and the upper via cavity (120) are shaped in the same way as, opposite or symmetrical to the layout of the lower electrode cavity (310) and the lower via cavity (320).

7. A wafer production jig as claimed in any one of claims 2 to 6, wherein,

the wafer cavity (230) and the middle conducting cavity are rectangular, the middle conducting cavity comprises four corners which are symmetrically distributed in the wafer cavity (230) and are partially overlapped with the wafer cavity (230), and the area of the overlapped part accounts for 1/4-1/2 of the area of the middle conducting cavity;

the upper main cavity (111) and the lower main cavity (311), the upper conducting cavity (120) and the lower conducting cavity (320) are rectangular, and the areas of the upper conducting cavity (120) and the lower conducting cavity (320) are the same as and correspond to those of the middle conducting cavity;

the upper extension cavity (112) is L-shaped and comprises a vertical part and a transverse part which are communicated with the upper main cavity (111), and the area of the transverse part is the same as and corresponds to that of the middle conduction cavity;

the lower extension cavity (312) is L-shaped and comprises a vertical part and a transverse part which are communicated with the lower main cavity (311), and the area of the transverse part is the same as and corresponds to that of the middle conduction cavity;

the upper extension cavity (112) and the upper conduction cavity (120) are diagonally arranged on the upper main cavity (111), the lower extension cavity (312) and the lower conduction cavity (320) are diagonally arranged on the lower main cavity (311), and the upper electrode cavity (110) and the upper conduction cavity (120), the lower electrode cavity (310) and the lower conduction cavity (320) are in the same shape and the same layout, and are arranged in a central symmetry manner of the wafer cavity (230), so that the first-type middle conduction cavity (210) forming the upper and lower channels (410) and the second-type middle conduction cavity (220) forming the lower upper channels (420) are diagonally distributed on the wafer cavity (230).

8. A wafer production jig as claimed in any one of claims 2 to 6, wherein,

the wafer cavity (230) and the middle conducting cavity are rectangular, the middle conducting cavity comprises two corners which are adjacently distributed in the wafer cavity (230) and are partially overlapped with the wafer cavity (230), and the area of the overlapped part accounts for 1/4-1/2 of the area of the middle conducting cavity;

the upper extension cavity (112) and the upper conduction cavity (120) are arranged at adjacent angles on the upper main cavity (111), the lower extension cavity (312) and the lower conduction cavity (320) are arranged at adjacent angles on the lower main cavity (311), the upper electrode cavity (110) and the upper conduction cavity (120), the lower electrode cavity (310) and the lower conduction cavity (320) are identical in shape and layout, and the upper electrode cavity (112) and the lower electrode cavity (310) are symmetrically arranged with the central axis of the wafer cavity (230) so that the first-type middle conduction cavity (210) forming the upper and lower channels (410) and the second-type middle conduction cavity (220) forming the lower upper channels (420) are distributed at adjacent angles on the wafer cavity (230).

9. Wafer production jig according to claim 8, characterized in that the other two corners of the wafer cavity (230) are provided with guide grooves (231) communicating with the wafer cavity (230).

10. A wafer production jig as claimed in any one of claims 2 to 6, wherein,

comprises two adjacently arranged upper conducting cavities (120), two adjacently arranged lower conducting cavities (320), two adjacently arranged upper extending cavities (112) and two adjacently arranged lower extending cavities (312);

the upper extension cavity (112) and the upper conduction cavity (120) are diagonally arranged on the upper main cavity (111), the lower extension cavity (312) and the lower conduction cavity (320) are diagonally arranged on the lower main cavity (311), and the upper electrode cavity (110) and the upper conduction cavity (120), the lower electrode cavity (310) and the lower conduction cavity (320) are identical in shape and layout, and are symmetrically arranged on the central axis of the wafer cavity (230) so that the two first-type middle conduction cavities (210) forming the upper channel (410) and the two second-type middle conduction cavities (220) forming the lower channel (220) are axially symmetrically distributed on the wafer cavity (230).