CN116034346A

CN116034346A - Device for memory management

Info

Publication number: CN116034346A
Application number: CN202080102045.3A
Authority: CN
Inventors: 盖伊·沙塔; 本-沙哈尔·贝尔彻; 罗宁·凯悦特; 利奥·赫尔莫什; 亚历克斯·马戈林
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-06-16
Filing date: 2020-06-16
Publication date: 2023-04-28
Also published as: EP4121861A1; WO2021254598A1

Abstract

The present invention relates to a requesting entity for requesting access to a virtual address range and to a memory device for allocating physical memory to said virtual address range and making the requested virtual address available to said requesting entity. Embodiments of the present invention enable multiple pages to be requested within a single range, which minimizes the number of requests and thus may reduce the request queue size. With the number of request messages significantly reduced, embodiments of the present invention also minimize the amount of traffic between the requesting entity and the memory device. Furthermore, embodiments of the present invention support multiple responses to the same request, where each response involves a sub-range of the virtual address range of the request. This enables the requesting entity to immediately begin DMA of the portion of the translated address and enables the memory device to translate a series of memory pages.

Description

Device for memory management

Technical Field

The present invention relates generally to the field of memory management. More particularly, embodiments of the present invention relate to an apparatus for requesting access to a virtual address and a memory device for allocating physical memory to a virtual address.

Background

The address translation service (address translation service, ATS) is a peripheral component interconnect express (peripheral component interconnect express, PCIe) service that enables a computer system to use translation agents to translate addresses from virtual addresses provided by I/O devices (i.e., endpoints) to physical addresses in system memory. An example of a computer system 100 is shown in FIG. 1, the computer system 100 including a translation agent 101, an address translation and protection table (address translation and protection table, ATPT) 103, and address translation cache (address translation cache, ATC) elements 107a-107d, as disclosed in the PCI Express 5.0 specification. The translation agent 101 accesses the address translation and protection table (address translation and protection table, ATPT) 103 to check the access authority and translation address. Endpoints (EP) 105a-105d may cache address translation entries from a system level address translation and protection table (address translation and protection table, ATPT) within an address translation cache (address translation cache, ATC).

However, the known address translation concepts are complex and inefficient, which results in increased traffic between the translation agent and the endpoint in the computer system.

Accordingly, there is a need for improved apparatus for memory devices.

Disclosure of Invention

It is an object of the present invention to provide an improved device for requesting access to a virtual address, and an improved device for more efficiently allocating physical memory to a virtual address.

The above and other objects are achieved by the subject matter as claimed in the independent claims. Other implementations are apparent in the dependent claims, the description and the drawings.

In general, the present invention relates to a requesting entity for requesting access to a virtual address, and a memory device for allocating physical memory to a virtual address and making the requested virtual address available to the requesting entity.

Compared to most advanced page request interfaces, embodiments of the present invention enable multiple pages to be requested within a single range, which minimizes the number of requests and thus may reduce the request queue size. With a significant reduction in the number of request messages, embodiments of the present invention also minimize the amount of traffic between the endpoint and the translation agent as described above, thereby reducing the number of software interrupts.

Furthermore, embodiments of the present invention support multiple responses to the same request, where each response relates to a portion of the requested range. This new response also supports more efficient (software and hardware) algorithms: enabling the requesting device to immediately start direct memory access to the portion of the translated address; and allows software to translate a series of pages instead of one at a time, thereby greatly improving the page prefetch algorithm. This may speed up operation, reduce CPU load, and increase memory utilization.

Briefly, embodiments of the present invention provide two types of messages: a single request message for a series of pages rather than page by page and a response message that can be used to respond to only a partial request rather than the entire request. In addition, multiple response messages may be sent in reply to a single request that may request a virtual address range associated with multiple contiguous physical address ranges, whereas in most advanced page request interfaces, there is only one response per request.

More specifically, according to a first aspect, the present invention relates to a memory device comprising: a storage arranged to include a physical memory unit; an interface for receiving a request message from a requesting entity for requesting access to a virtual address range; a memory controller configured to allocate a plurality of physical memory units in the memory to a sub-range of the virtual address range, and map physical addresses of the plurality of physical memory units with the sub-range of the virtual address range; and a memory address translator for generating address information indicative of the sub-range of the virtual address range to which the physical address is mapped.

After generating the address information, the interface is configured to send a response message including the address information to the requesting entity in response to the request message.

In one embodiment, the requesting entity may be an input/output device, a graphics card, a network card, or other peripheral device, and the requested virtual address range is associated with at least two virtual memory units.

In view of the foregoing, an improved memory device is therefore provided that supports efficient authorization of portions of a virtual address range in response to a request for the virtual address range. This allows the requesting entity to initiate a direct memory access (direct memory access, DMA) to a partial range of virtual addresses (i.e., a portion of the requested virtual memory that has been translated).

In another possible implementation of the first aspect, the memory controller is configured to determine, prior to allocating the plurality of physical memory to the sub-range of the virtual address range, whether the plurality of physical memory units are available in the memory, and the memory address translator is configured to generate an indication that the request cannot be granted if the memory controller determines that the plurality of physical memory units are not available, and the interface is configured to send a rejection message to the requesting entity, the rejection message including the indication.

Therefore, a rejection message indicating that the request cannot be authorized can be efficiently sent to the requesting entity.

In another possible implementation manner of the first aspect, the memory controller is configured to allocate a further plurality of physical memory units in the memory to another sub-range of the virtual address range, and map physical addresses of the further plurality of physical memory units with the another sub-range of the virtual address range. Accordingly, the memory address translator is operable to generate further address information indicative of a further sub-range of the virtual address range to which the physical address is mapped, and the interface is operable to send a further response message comprising the further address information to the requesting entity.

Accordingly, an improved memory device is provided that can send multiple response messages to answer a single request for a virtual address range by a requesting entity. The plurality of response messages includes a plurality of sub-ranges of virtual address ranges, which may be associated with a plurality of contiguous ranges of physical addresses.

Embodiments of the present invention allow a memory device to translate a set of pages of virtual memory, rather than one page at a time, which greatly improves the page prefetch algorithm.

In another possible implementation of the first aspect, the memory controller is configured to determine whether the further plurality of physical memory units are available in the storage before allocating the further plurality of physical memory to the further sub-range of the virtual address range.

In accordance with the memory controller determining whether the further plurality of physical memory units are available, the memory address translator generates a further indication indicating whether the further sub-range requesting access to the virtual address range may be authorised. The interface is configured to send the further response message to the requesting entity, the further response message comprising the further address information and the further indication.

Thus, two types of responses may be sent, including a "successful" response indicating that an unconverted range has been successfully requested, or an "unsuccessful" message indicating that the requested range is not available.

An address translation service (address translation service, ATS) is also required to request translation of the successfully requested virtual address.

In another possible implementation manner of the first aspect, the request message includes an identifier identifying the request message, wherein the memory address translator is configured to include the identifier in the response message, and/or a responder identifier identifying the memory address translator and/or a requester identifier identifying the requesting entity.

Thus, a plurality of response messages responding to the same request message can be efficiently identified and transmitted. In addition, the memory address translator and the requesting entity may also be identified with a responder identifier and a request identifier, respectively.

In another possible implementation manner of the first aspect, if the memory controller determines that the plurality of physical memory units are not available, the memory address translator is configured to generate a status indication indicating one of the following states: requesting access to the virtual address range fails; requesting access to the virtual address range is invalid; requesting access to the virtual address range may be resent. The interface is configured to send the rejection message including the status indication to the requesting entity.

In another possible implementation manner of the first aspect, if the status indication indicates that the request to access the virtual address range may be retransmitted, the memory address translator is configured to generate a retry time indication indicating a time period for retransmitting the request message, where the retry time indication is configured to enable the requesting entity to retransmit the request message for requesting access to the virtual address range after the time period after the requesting entity receives the rejection message.

In another possible implementation of the first aspect, if the memory controller determines that the further plurality of physical memory units are not available in the storage, the memory address translator is configured to generate another state indication indicating one of: requesting access to the other sub-range of the virtual address range fails; requesting access to the other sub-range of the virtual address range is invalid; the further sub-range requesting access to the virtual address range may be sent.

The interface is configured to send the further response message comprising the further status indication to the requesting entity.

In another possible implementation manner of the first aspect, if the further status indication indicates that the further sub-range requesting access to the virtual address range may be transmitted, the memory address translator is configured to generate a retry time indication indicating a further time period for transmitting a further request message.

The retry time indicates the further request message for requesting access to the further sub-range of the virtual address range after the further time period for the requesting entity to be able to send after the further response message.

In another possible implementation of the first aspect, the request message includes a threshold indication indicating a maximum number of response messages allowed to be sent to the requesting entity, and the memory controller is further configured to allocate each physical memory unit of a set of physical memory units in the memory to a respective one of a set of sub-ranges of the virtual address range, and map each physical memory unit of the set of physical memory units with a respective sub-range of the virtual address range of the set of sub-ranges of the virtual address range.

In addition, the memory address translator is configured to: generating a set of address information based on the set of sub-ranges of the virtual address range, each address information in the set of address information indicating a respective sub-range of the virtual address range in the set of sub-ranges of the virtual address range; each address information in the set of address information is included into a respective response message in a set of response messages for accessing the set of sub-ranges of the virtual address range in response to a request.

The interface is configured to send the set of response messages to the requesting entity if the number of the set of response messages is equal to or less than the maximum number.

The interface is configured to send a subset of the set of response messages to the requesting entity if the number of the set of response messages is greater than the maximum number, the number of the subset of the set of response messages being equal to the maximum number.

In another possible implementation manner of the first aspect, the memory address translator is configured to generate a response indication to indicate whether a response message in the set of response messages is a last response message to be sent to the requesting entity, and the memory address translator is further configured to include the response indication in the response message in the set of response messages, the response message being a last response message to be sent to the requesting entity.

In another possible implementation of the first aspect, the request message includes an indication indicating a relaxed transmission order. In this aspect, the memory controller is further configured to: each physical memory unit of a set of a plurality of physical memory units in the memory is allocated to a respective one of a set of sub-ranges of the virtual address range, and each physical memory unit of the set of a plurality of physical memory units is mapped with a respective sub-range of the virtual address range of the set of sub-ranges of the virtual address range that is contiguous.

The memory address translator is configured to: generating a set of address information based on the set of sub-ranges of the virtual address range, each address information in the set of address information indicating a respective sub-range of the virtual address range, a respective plurality of physical memory units in the set of physical memory units mapped to a respective sub-range of the virtual address range, and including each address information of the set of address information to a respective response message of a set of response messages; generating a sequence number set based on the sub-range sets of the virtual address range, the corresponding address information of the address information set being mapped to each of the sub-range sets; each sequence number in the sequence number set is assigned to a corresponding response message in the response message set for responding to the request to access the sub-range set of the virtual address range according to the order in which the memory controller assigns the time point of a corresponding one of the plurality of sets of physical memory units.

The interface is configured to send the set of response messages according to the order of the set of sequence numbers.

Thus, the interface of the memory device may send the response message without following the order of the request scope. Upon receiving any response message by the requesting entity indicating the availability of the sub-range of the virtual address range, the requesting entity may immediately begin direct memory access (direct memory access, DMA) to the sub-range of the virtual address range without waiting for authorization of the entire virtual address range.

In another possible implementation manner of the first aspect, the memory address translator is integrated within the memory controller or is a separate device interconnected with the memory controller through another interface.

According to a second aspect, the invention relates to a requesting entity for requesting access to a virtual address range. In this regard, the requesting entity is configured to send a request message requesting access to the virtual address range, wherein the virtual address range is associated with at least two virtual memory units.

In an embodiment, the requesting entity may send a request message to the memory device of the first aspect. If the memory device allows the requesting entity to access a sub-range of the virtual address range, the requesting entity is operable to receive a response message comprising address information indicating the sub-range of the virtual address range that the requesting entity is allowed to access.

In one embodiment, the requesting entity is a peripheral device such as an I/O device, graphics card, network card, or other peripheral device, and communicates with the memory device via an interface such as a bus.

In another possible implementation manner of the second aspect, the requesting entity is configured to receive another response message including another address information, the another address information indicating another sub-range of the virtual address range that the requesting entity is allowed to access.

Thus, an improved requesting entity is provided that can request more than one virtual memory unit, i.e. more than one page of virtual memory, at a time. The requesting entity is able to request a translation of memory range rather than page by page, which reduces the number of messages between the requesting entity and the memory device and increases the bus bandwidth between the two entities.

In addition, the requesting entity may begin direct memory access (direct memory access, DMA) to a sub-range of the virtual address range without waiting for authorization of the entire virtual address range.

In another possible implementation manner of the second aspect, the requesting entity is configured to define the virtual address range as a range from a starting virtual address plus a virtual memory unit length, or a range between the starting virtual address and an ending virtual address.

Thus, the requesting entity can efficiently request the virtual address range.

In another possible implementation manner of the second aspect, the requesting entity is further configured to include a threshold indication in the request message, wherein the threshold indication indicates a maximum number of response messages allowed to be sent to the requesting entity for responding to the request message.

In another possible implementation manner of the second aspect, the requesting entity is configured to include one or more of the following in the request message: a requestor identifier identifying the requesting entity, a responder identifier identifying a responding entity that responds to the request message, an identifier identifying the request message, and a flag comprising at least one access right requested by the requesting entity, the at least one access right being associated with a range of virtual memory addresses, in particular written, read, executed, not read, not written or not executed.

In another possible implementation manner of the second aspect, the requesting entity is configured to receive a rejection message indicating that the request for access to the virtual address range cannot be authorized and a retry time indication indicating a time period for resending the request message. In this aspect, the requesting entity is configured to resend the request message after the time period after the requesting entity receives the rejection message.

Thus, the requesting entity can efficiently resend the request to access the virtual address range.

In another possible implementation manner of the second aspect, the requesting entity is configured to receive a second further response message indicating that a second further sub-range requesting access to the virtual address range cannot be authorized, and a further retry time indication indicating a further time period for sending a further request message requesting access to the second further sub-range of the virtual address range. In this regard, the requesting entity is configured to send the further request message after the further time period after the requesting entity receives the second further response message.

Thus, the requesting entity is able to efficiently send another request to access the virtual address sub-range without requesting the entire virtual address range.

In another possible implementation manner of the second aspect, the requesting entity is configured to include in the request message an indication indicating a loose sending order, and to enable the responding entity to send a response message to the requesting entity earlier than another response message, where the response message indicates a sub-range of the virtual address range that the requesting entity is allowed to access, and the another response message indicates another sub-range of the virtual address range that the requesting entity is allowed to access. In one embodiment, the sub-range of the virtual address range is accessed by the requesting entity before the other sub-range of the virtual address range.

Thus, once a sub-range of the virtual address range is available to the requesting entity, the requesting entity may access this sub-range of the virtual address range, i.e. the requesting entity may immediately begin direct memory access (direct memory access, DMA) to the sub-range of the virtual address range without waiting for authorization of the entire virtual address range.

Drawings

Other embodiments of the invention will be described in conjunction with the following drawings, in which:

FIG. 1 shows a schematic diagram of a computer system including translation agents, address translation and protection tables (address translation and protection table, ATPT) and address translation cache (address translation cache, ATC) elements;

FIG. 2 illustrates an exemplary system memory management unit (system memory management unit, SMMU) architecture;

FIG. 3 illustrates a schematic diagram of an exemplary interaction process between a translation agent and an address translation cache (address translation cache, ATC) in a PCIe device;

FIG. 4 is a schematic diagram showing the process of address translation service (address translation service, ATS) cache invalidation;

FIG. 5 illustrates an exemplary process flow for requesting a page through a most advanced page request interface;

FIG. 6 illustrates a schematic diagram of a computer system including a memory device and a requesting entity provided by an embodiment;

FIG. 7 illustrates an exemplary process provided by an embodiment in which a requesting entity requests a virtual address range from a memory device;

FIG. 8 also illustrates an exemplary process provided by an embodiment in which a requesting entity requests a virtual address range from a memory device provided by the embodiment;

FIG. 9 illustrates an implementation of a request message that a requesting entity provided by an embodiment may send;

fig. 10 illustrates an implementation of a response message that may be sent by a memory device provided by an embodiment.

The same reference numbers will be used throughout the drawings to refer to the same or at least functionally equivalent features.

Detailed Description

The following description refers to the accompanying drawings, which form a part hereof, and which illustrate by way of illustration specific aspects in which the invention may be practiced. It is to be understood that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, as the scope of the present invention is defined by the appended claims.

For example, it should be understood that the disclosure related to describing a method may be equally applicable to a corresponding device or system for performing the method, and vice versa. For example, if a specific method step is described, the corresponding apparatus may comprise the unit performing the described method step, even if such unit is not explicitly described or illustrated in the figures.

Furthermore, the following detailed description and the claims describe various functional blocks or processing units that may be interconnected or may exchange signals. It is to be understood that embodiments are also contemplated by the present invention, including other functional blocks or processing units disposed between the functional blocks or processing units in the embodiments described below.

Finally, it should be understood that features of the various exemplary aspects described herein may be combined with one another unless explicitly stated otherwise.

Fig. 2 shows an exemplary system memory management unit (system memory management unit, SMMU) architecture 200 of an ARM processor, wherein the SMMU system 201 has translation cache units (translation buffer unit, TBUs) 203a, 203b for intercepting transactions requiring translation and translating addresses of those transactions.

Caching entries in the address translation and protection table (address translation and protection table, ATPT) allows the endpoint to request direct memory access (direct memory access, DMA) transfers using pre-translated addresses, so the address translation and protection table (address translation and protection table, ATPT) does not have to be prefetched from memory in tandem with direct memory access (direct memory access, DMA) operations, thus reducing latency of the operations.

Fig. 3, taken from the PCI specification v10.1.1 address translation service overview, shows how translation agent 301 and address translation cache (address translation cache, ATC) 307 interact within PCIe device (i.e., endpoint) 305. When PCIe device 305 sends an address translation service (address translation service, ATS) request to translation agent 301, translation agent 301 performs the following basic steps:

1. Capability: translation agent 301 tests that PCIe device 305 has been configured to issue an ATS translation request.

2. Memory access rights: translation agent 301 determines whether PCIe device 305 has access to memory 321 indicated by the ATS translation request and whether PCIe device 305 has associated access rights.

3. Availability of: translation agent 301 determines whether translation may be provided to PCIe device 305. If so, translation agent 301 issues a translation.

4. Translation agent 301 transmits the success or failure of the request to Root Complex (RC) 311, which generates an ATS translation completion and sends the ATS translation completion to PCIe device 305 through a response transaction layer packet (transaction layer packet, TLP) via root port 313. The successful translation may generate one or two ATS translation completion TLPs per request. The transition completion indicates the covered transition range. The Root Complex (RC) 311 needs to send the ATS conversion completion using the same stream Type (TC) as the corresponding ATS request.

The address of the request may be invalid. The Root Complex (RC) needs to issue a completion indicating that the address of the request is not accessible.

FIG. 4 is taken from the PCI Specification v10.1.1 address translation service overview, illustrating the process of ATS cache invalidation:

Step 401: translation agent 301 sends a invalidation request to address translation cache (address translation cache, ATC) 307.

Step 403: the PCIe device 305 completes the DMA transfer and then clears the address translation cache (address translation cache, ATC) 307 or discards the conflicting read.

Step 405: the address translation cache (address translation cache, ATC) 307 on PCIe device 305 sends the translation agent 301 a invalidation completion.

Step 407: after receiving the invalidation completion from all address translation caches (address translation cache, ATC) 307 within all PCIe devices 305 on the system, translation agent 301 deletes the entry.

The page request interface (page request interface, PRI) adds the ability for PCIe devices or functions to make direct memory accesses (direct memory access, DMA) on unfixed dynamic page memory. If the address translation service (address translation service, ATS) responds with a translation failure for a range of memory pages, the PCIe device (i.e., endpoint) may issue multiple PRI page requests to ask the software (i.e., operating system) to have the requested page reside.

Software receives these PRI page requests from a page request interface (page request interface, PRI) queue through the IOMMU interface, and may also receive interrupts. After having the page resident in RAM memory, the software further issues a positive PRI response command to the system memory management unit (system memory management unit, SMMU). If the requested address is not available or the programming failure results in the device requesting an illegal address, the PCIe device receives a failure response.

The PCIe device or function may send multiple requests using the same page request group (page request group, PRG). In this case, all pages requested in the same page request group (page request group, PRG) have a single response. Upon receiving the PRI response, the device may issue another ATS request to obtain a transition of the requested page.

Since the page request interface (page request interface, PRI) requests one page at a time, multiple requests must be made to the virtual memory range. Multiple software interrupts may also be raised when the requested pages do not share the same page request group (page request group, PRG).

An exemplary process flow for requesting a page through the most advanced page request interface may be as follows:

1. the function or PCIe device determines that it needs to access a page for which address translation service (address translation service, ATS) translation is not available.

2. The function causes the associated page request interface (page request interface, PRI) to send a page request message to its root complex. The page request message includes a page address and a page request group (page request group, PRG) index. The PRG index is used to identify transactions and to match requests with responses.

3. When the root complex determines its response to the request (typically having the requested page resident in memory), it sends a response message associated with the page request group (page request group, PRG) back to the requesting function.

4. The function may then request conversion for the requested page using an address conversion service (address translation service, ATS).

In view of the above, the most advanced page request interfaces (page request interface, PRI) only support requesting a single page per request, or possibly grouping multiple pages in the same request group. Further, for multiple requests, the response message is sent only once and includes a result indicating success or failure. Since the page request interface (page request interface, PRI) requests one page at a time, multiple requests must be made to the virtual memory range. Multiple software interrupts may also be raised when the requested pages do not share the same page request group (page request group, PRG).

FIG. 5 illustrates an exemplary process flow 500 for requesting a page through a most advanced page request interface:

steps 511a-511f: the endpoint 501 (e.g., PCIe device) sends multiple request messages to the translation agent 503 for requesting access to the virtual memory range and groups the multiple pages together in a request group, where each request message requests only one page at a time.

Steps 513a-513f: translation agent 503 also sends these multiple request messages to operating system or central processing unit (central processing unit, CPU) 505.

Step 515: operating system or CPU 505 only sends response messages indicating that multiple requests are complete.

Step 517: translation agent 503 forwards a response message to endpoint 501 indicating completion.

In contrast, embodiments of the present invention also provide a first improvement to messages transmitted between endpoints and conversion agents (i.e., the content of request and completion messages), and a second improvement to the logic flow, i.e., how such messages should be handled between endpoints and conversion agents.

In this regard, embodiments of the present invention relate to a requesting entity for requesting access to a virtual address, and a memory device for allocating physical memory to the virtual address and making the requested virtual address available to the requesting entity.

More specifically, embodiments of the present invention may be implemented in a computer system 600, the computer system 600 having a general architecture as shown in FIG. 6. In the embodiment shown in fig. 6, as an example, the communication system 600 comprises a requesting entity 631 for requesting access to a virtual address, and a memory means 601 for allocating physical memory to the virtual address and making the requested virtual address available to the requesting entity 631.

In one embodiment, requesting entity 631 is an external device such as an I/O device, graphics card, network card, or other peripheral device and communicates with the memory device through an interface such as a bus.

As can be seen from the detailed view shown in fig. 6, the memory device 601 includes: a memory 603 including physical memory units; an interface 607 for communicating with an external device; a memory controller 605 for allocating physical memory units in the memory to virtual addresses; a memory address translator 609. In one embodiment, the memory address translator 609 is integrated within the memory controller 605 or is a separate device interconnected to the memory controller 605 through other interfaces such as a bus.

In one embodiment, the requesting entity 631 is configured to send a request message for requesting access to a virtual address range, e.g., the requesting entity 631 may define the virtual address range as a range of virtual memory location length plus a starting virtual address or as a range between a starting virtual address and an ending virtual address. The virtual address range is associated with at least two virtual memory units. For example, the requesting entity requests access to a virtual address range from 0x80000000 to 0x 80100000.

In another embodiment, the requesting entity 631 can include one or more of the following in the request message: a requestor identifier identifying the requesting entity 631 itself, a responder identifier identifying the responding entity responding to the request message, an identifier identifying the request message, and a flag including at least one access right requested by the requesting entity, the at least one access right being associated with a range of virtual memory addresses, in particular "write", "read", "execute", "not read", "not write" or not execute ".

In one embodiment, the responding entity 631 responding to the request message is a memory device and the interface of the memory device 601 is configured to receive the request message from the requesting entity 631. After receiving the request, the memory controller 605 is configured to allocate a plurality of physical memory units in the memory 603 to a sub-range of the virtual address range, and map the physical addresses of the plurality of physical memory units with the sub-range of the virtual address range.

In another embodiment, the memory controller 605 is configured to determine whether a plurality of physical memory units are available in the memory before allocating the plurality of physical memory to the sub-range of the virtual address range. If the memory controller 605 determines that a plurality of physical memory units are available, the memory address translator 609 is operable to generate address information indicating a sub-range of the virtual address range to which the physical address maps.

In one embodiment, the memory address translator 609 may also generate one or more of the following information: an identifier, and/or a responder identifier identifying a memory address translator and/or a requester identifier identifying requesting entity 631. This information may be included in a response message for responding to a request message from the requesting entity 631.

After generating the address information, the interface 607 of the memory device 601 is then used to send a response message comprising the address information to the requesting entity 631 in response to the request message. The requesting entity 631 is arranged to receive response messages. Thus, the requesting entity 631 receives address information indicating the sub-ranges of the virtual address range that the requesting entity is permitted to access.

On the other hand, if the memory controller 605 determines that a plurality of physical memory units are not available, the memory address translator 609 is used to generate an indication that the request cannot be granted.

In another embodiment, the memory address translator may also generate a state indication indicating one of the following states: requesting access to the virtual address range fails; requesting access to the virtual address range is invalid; the request to access the virtual address range may be resent.

In another embodiment, if the status indication indicates that the request to access the virtual address range may be resent, the memory address translator 609 is configured to generate a retry time indication indicating a time period for resending the request message, wherein the retry time indication is configured to enable the requesting entity to resend the request message for requesting access to the virtual address range after the time period after the requesting entity receives the rejection message.

The interface 607 is adapted to send a rejection message comprising an indication and/or a status indication and/or a retry time indication to the requesting entity 631.

In another embodiment, if the requesting entity 631 receives a rejection message indicating that the request to access the virtual address range cannot be authorized and a retry time indication indicating a time period for retransmitting the request message, the requesting entity 631 is configured to retransmit the request message after the time period after the requesting entity receives the rejection message.

In another embodiment, the memory controller 605 is configured to determine whether the additional plurality of physical memory units are available in the memory 603 before allocating the additional plurality of physical memory to another sub-range of the virtual address range.

If a further plurality of physical memory units is available, the memory controller 605 is operable to allocate the further plurality of physical memory units in the memory 603 to another sub-range of the virtual address range and map the physical addresses of the further plurality of physical memory units with the other sub-range of the virtual address range. In addition, the memory address translator 609 is configured to generate further address information indicating a further sub-range of the virtual address range to which the physical address is mapped.

In one embodiment, the memory address translator 609 may determine from the memory controller 605 whether another plurality of physical memory units are available, generate another indication that indicates whether another sub-range requesting access to the virtual address range may be authorized.

The interface 607 is for sending a further response message to the requesting entity 631, the further response message comprising further address information and/or a further indication. Accordingly, the requesting entity 631 is arranged to receive a further response message comprising a further indication and/or further address information indicating a further sub-range of the virtual address range to which the requesting entity is allowed to access.

If the memory controller 605 determines that another plurality of physical memory units are not available in the memory 603, the memory address translator 609 may also generate another state indication that indicates one of the following states: requesting access to another sub-range of the virtual address range fails; requesting access to another sub-range of the virtual address range is invalid; another sub-range requesting access to the virtual address range may be sent.

If another status indication indicates that another sub-range requesting access to the virtual address range may be sent, the memory address translator 609 is operable to generate a retry time indication indicating another time period for sending another request message. The retry time indicates a further request message for requesting access to a further sub-range of the virtual address range after a further time period for enabling the requesting entity to send after the further response message.

The interface 607 is arranged to send a further response message comprising a further status indication to the requesting entity 631, if the further status indication indicates that a further sub-range requesting access to the virtual address range can be sent, a retry time indication is sent.

When the requesting entity 631 receives a further response message indicating that a further sub-range requesting access to the virtual address range cannot be granted and a retry time indication indicating a further time period for sending a further request message requesting access to a further sub-range of the virtual address range. In this regard, the requesting entity 631 is operable to send another request message after another time period after the requesting entity receives another response message.

In one embodiment, the requesting entity 631 is further configured to include a threshold indication in the request message, wherein the threshold indication indicates a maximum number of response messages allowed to be sent to the requesting entity 631 for responding to the request message.

In this regard, the memory controller 605 is further configured to allocate each physical memory unit of the set of the plurality of physical memory units in the memory 603 to a respective one of the sub-ranges of the set of sub-ranges of virtual address ranges, and map each physical memory unit of the set of physical memory units with a respective sub-range of the virtual address ranges of the sub-range set of virtual address ranges. In addition, the memory address translator 609 is configured to: generating a set of address information based on the set of sub-ranges of virtual address ranges, each address information in the set of address information indicating a respective sub-range of the virtual address ranges in the set of sub-ranges of virtual address ranges; each address information in the set of address information is included into a respective response message in a set of response messages for accessing the sub-range set of virtual address ranges in response to the request.

If the number of response message sets is equal to or less than the maximum number, the interface 607 is used to send the response message sets to the requesting entity 631. If the number of response message sets is greater than the maximum number, the interface 607 is configured to send a subset of the response message sets to the requesting entity 631, the number of subsets of the response message sets being equal to the maximum number.

In another embodiment, the memory address translator may generate a response indication to indicate whether a response message in the set of response messages is the last response message to be sent to the requesting entity, and the memory address translator is further configured to include the response indication in a response message in the set of response messages, the response message being the last response message to be sent to the requesting entity 631.

In another embodiment, the requesting entity 631 is configured to include in the request message an indication indicating a relaxed sending order and to enable the responding entity to send to the requesting entity 631 a response message earlier than another response message, wherein the response message indicates a sub-range of the virtual address range that the requesting entity 631 is permitted to access and the other response message indicates another sub-range of the virtual address range that the requesting entity is permitted to access. In one embodiment, a sub-range of the virtual address range is made to be accessed by the requesting entity before another sub-range of the virtual address range.

In this regard, the memory controller 605 is further configured to allocate each physical memory unit of the set of the plurality of physical memory units in the memory 603 to a respective one of the sub-ranges of the sub-range set of virtual address ranges, and map each physical memory unit of the set of the plurality of physical memory units with a respective sub-range of virtual address ranges of the sub-range set of consecutive virtual address ranges.

In addition, the memory address translator 609 is configured to: generating a set of address information based on the set of sub-ranges of the virtual address range, each address information in the set of address information indicating a respective sub-range of the virtual address range, a respective plurality of physical memory units in the set of physical memory units mapped to a respective sub-range of the virtual address range, and including each address information of the set of address information to a respective response message of the set of response messages; generating a sequence number set based on the sub-range sets of the virtual address range, and mapping corresponding address information of the address information set to each sub-range set; each sequence number in the sequence number set is assigned to a corresponding response message in the response message set for responding to the request to access the sub-range set of the virtual address range according to the order in which the memory controller assigns the time point of a corresponding one of the plurality of sets of physical memory units.

Finally, the interface 607 is configured to send the set of response messages according to the order of the set of sequence numbers. Thus, the interface 607 of the memory device 601 may send response messages without following the order of the requested virtual address ranges.

An exemplary logic flow provided by the embodiments is as follows:

1. the requesting entity 631 requests access to the virtual memory address range that is not translated.

2. The requesting entity 631 transmits a request message for the address translation service (address translation service, ATS) to the memory address translator 609 and receives the failure result.

3. The requesting entity 631 sends a request message to the memory address translator 609.

4. When a message is received, the memory address translator 609 triggers a software interrupt.

5. The memory controller 605 attempts to create a translation between the requested address range and the physical address and updates a table associated with the memory management unit or the system memory management unit.

6. The memory controller 605 returns the result to the memory address translator 609. The memory address translator 609 sends a response message to the requesting entity 631. The result may include a plurality of messages consisting of two types: the conversion is successful or unsuccessful (partial range has been converted and partial range has not been converted).

7. The requesting entity 631 receives the response and then issues an address translation service command to the address range where the translation was successful.

8. In response to the "please retry later" indication in the response message, the requesting entity 631 waits for a defined period of time and then retries.

Fig. 7 illustrates an exemplary process 700 of a requesting entity 631 requesting a virtual address range from a memory device 601, wherein the memory device 601 comprises: a memory 603 including physical memory units; an interface 607 for communicating with a requesting entity 631; a memory controller 605 for allocating physical memory units in the memory 603 to virtual addresses; a memory address translator 609.

The process 700 shown in fig. 7 includes the steps of:

step 701: the requesting entity 631 (e.g., endpoint) sends a request message for requesting access to a virtual address range from 0x80000000 to 0x 80100000.

Step 703: the memory address translator 609 (e.g., translation agent) also sends a request message to the memory controller 605, i.e., the operating system or central processing unit (central processing unit, CPU).

Step 705: the memory controller 605 sends a response message indicating that the request range is complete.

Step 707: the memory address translator 609 forwards a response message to the requesting entity 631 indicating completion.

While the previous endpoint had to send multiple page request interface requests using the same page request group, embodiments allow the endpoint to send a single request to request access to the virtual address range.

This reduces the number of entries in the interrupt queue, as well as the number of interrupt requests that the operating system or CPU receives from the system memory management unit.

Fig. 8 further illustrates an exemplary process 800 of the requesting entity 631 requesting a virtual address range from the memory device 601, wherein the memory device 601 comprises: a memory 603 including physical memory units; an interface 607 for communicating with a requesting entity 631; a memory controller 605 for allocating physical memory units in the memory 603 to virtual addresses; a memory address translator 609.

The process 800 shown in fig. 8 includes the steps of:

step 801: the requesting entity 631 (e.g., endpoint) sends a request message for requesting access to a virtual address range from 0x80000000 to 0x80100000.

Step 803: the memory address translator 609 (e.g., translation agent) also sends a request message to the memory controller 605, i.e., the operating system or central processing unit (central processing unit, CPU).

Steps 805a-805c: the memory controller 605 sends a plurality of response messages, each indicating a sub-range of virtual address ranges available to the requesting entity 631, e.g., the first sub-range may be 0x80000000-0x80080000, the second sub-range may be 0x80080000-0x800a0000, and the third sub-range may be 0x800a0000-0x80100000.

Steps 807a-807c: the memory address translator 609 forwards a plurality of response messages to the requesting entity 631.

Whereas previously, the requesting entity 631 had to send multiple page request interface requests using the same page request group and receive a single response (which may be a failed response if at least one page was not convertible).

In contrast, embodiments of the present invention support sending a single request for a page range and receiving multiple responses. Multiple responses may be separated in transmission time and content. Some of which may indicate success and some of which indicate failure. This allows the requesting entity to initiate a direct memory access (direct memory access, DMA) to the virtual address sub-range based on the partial response.

Embodiments of the invention may use the following request messages sent from the PCIe device to the responder, where the responder is typically a translation agent. The request message may be an extension of the existing page request interface request or may be the entire new message.

The following are fields proposed for the request message, some of which are optional, depending on implementation:

1. the requested virtual address range (optional) describes the list of virtual addresses to be translated. This may be accomplished in a number of ways. Some approaches may include a base address and a length or a start address and an end address, where each of these values may be represented directly or implicitly (e.g., a range of 4k may be represented by binary number 1101, a range of 8k may be represented by 1001, i.e., the representation is implementation-specific).

2. For identifying a request set of scope requests. This field is similar to the page request group (optional) in the page request interface.

3. Flag-supported relaxed ordering (optionally, if responses are always sent in order, then no need exists)

4. Maximum number of returned responses allowed.

5. Read, write, no read, no write, execute, no execute flags (all flags are optional) that specify the expected or likely use case of the converted page range.

6. Requester identifier/address (optionally, not required when there is only a single device in the system)

7. Responder identifier/address (optionally, default may be a translation agent)

Fig. 9 illustrates an implementation of a request message 900 that may be sent by a requesting entity provided by an embodiment. This example is based on the existing dti_ats_req message.DTI_ATS_REQ is

A distributed conversion interface (distributed translation interface, DTI) is part of the protocol specification.

The field REQ_RNG bits [75:73] may be added, indicating the address range of the request. The values of the fields are in bits (binary) as follows:

embodiments of the present invention may use the following response messages sent from the responding party, which is typically the conversion agent of the requesting entity. This message may be an extension of the existing page request interface response or may be the entire new message.

The following are fields proposed for response messages, some of which are optional, depending on implementation:

1. status (optional), indication:

a. successful conversion

b. Conversion failure (selection)

c. Request invalidation

d. Please retry after timeout (see comment at bottom of page)

e. Request invalidation

2. The address range (mandatory) may be one of the following: the untranslated virtual address range, or distance from the base virtual address specified in the request + page length.

3. A range request group (range request group, RRG) for identifying requests. The role of this field is similar to the role of the page request group in the page request interface.

4. A last flag indicating that the current message in the series of response messages is the last message (optional).

5. A response sequence number (optionally, not required if the responses are sent sequentially), wherein this number orders the range of conversions when multiple response messages are sent per request. When a request sets a relaxed ordering flag, only the 'last flag' is used to indicate the end of the response.

6. The requestor identifier/address (optionally, not needed when there is only a single endpoint in the system).

7. The responder identifier/address (optionally, default value is translation agent).

8. A time period of retry in the retry state (optional).

It should be noted that field 8 (time period of retry) and response type 1.D (please retry after timeout) are optional, which can be implemented together.

Fig. 10 illustrates an implementation of a response message 1000 that may be sent by a memory device provided by an embodiment. The present example is based on the existing DTI_ATS_RESP, is

The "resp_rng" and "STATUS" fields may be added and address bits may be extended. The value of a particular field is in bits (binary) as follows:

the field "RESP_RNG", bits [10:8] indicate the effective range of response addresses:

the field "STATUS" bits [5:4] indicate the STATUS of the range request interface request:

according to one embodiment, the request message sent from the requesting entity (e.g., endpoint) may include the following:

requested virtual address range: 0x 40000000+length 0x8000

Scope request group (range request group, RRG): 11

If loose ordering is allowed: disallowing

Maximum number of returned responses allowed: 3

Read, write, not read, not write, execute, not execute flag: write, not read, not execute.

In this regard, the requesting entity requests a memory range of 0x40000000-0x40008000 for write-only, replies no more than 3, in the range request group 11.

After receiving the request message, the memory device or the like may send the following response message:

1 consecutive block+1 unconverted block+1 consecutive block

State: successful, range 0x40000000-0x40000fff, rrg:11, not the last response. It should be noted that this is an untranslated address (i.e., virtual address)

State: successful, range 0x40001000-0x40002fff, rrg:11, not the last response. It should be noted that this is an untranslated address (i.e., virtual address)

State: successful, range 0x40003000-0x40004fff, rrg:11, last response. It should be noted that this is an untranslated address (i.e., virtual address)

For the range of requests 0x40005000-0x40008000, no response is sent since there are only 3 maximum allowed responses.

According to another embodiment, the request message sent from the requesting entity (e.g., endpoint) may include the following:

requested virtual address range: 0x 40000000+length 0x8000

Scope request group (range request group, RRG): 11

Allowed relaxed ordering: disallowing

Maximum number of returned responses allowed: 3

state: successful, range 0x40000000-0x40007fff, rrg:11, last response.

requested virtual address range: 0x 40000000+length 0x8000

Scope request group (range request group, RRG): 11

Allowed relaxed ordering: disallowing

Maximum number of returned responses allowed: 3

After receiving the request message, the memory device or the like may send the following multiple response messages:

1 consecutive block+1 unconverted block+1 consecutive block

For the range of requests 0x40005000-0x40008000, no response is sent because the maximum allowed number of responses is 3.

requested virtual address range: 0x 40000000+length 0x8000

Scope request group (range request group, RRG): 11

Allowed relaxed ordering: allow for

Maximum number of returned responses allowed: 3

In this regard, the requesting entity requests a memory range of 0x40000000-0x40008000 for write-only, for range request group 11, no more than 3 replies.

After receiving the request message, the memory device or the like may send the following unordered response messages:

1 consecutive block+1 unconverted block+1 consecutive block

State: successful, range 0x40000000-0x40000fff, rrg:11, non-last response (response sequence number: 0x 2)

State: successful, range 0x40001000-0x40002fff, rrg:11, non-last response (response sequence number: 0x 1)

State: successful, range 0x40003000-0x40004fff, rrg:11, last response (response sequence number: 0x 3)

requested virtual address range: 0x 40000000+length 0x8000

Scope request group (range request group, RRG): 11

Allowed relaxed ordering: disallowing

Maximum number of returned responses allowed: 3

Read, write, not read, not write, execute, not execute flag: writing, not reading, not executing in this regard, the requesting entity requests memory ranges 0x40000000-0x40008000 for write-only, no more than 3 replies in the range request group (range request group, RRG) 11.

1 consecutive block+1 unconverted block+1 consecutive block

State: successful, range 0x40000000-0x40000fff, rrg:11, not the last response.

State: successful, range 0x40001000-0x40002fff, rrg:11, not the last response.

State: retry later, retry time later: 100 ns, range 0x40003000-0x40004fff, rrg:11, last response.

According to one embodiment, another possible way to implement the range request interface request is to reuse existing page request interface request messages and transmit additional parameters in a separate channel. Since some of the fields in the range request interface (range request interface, RRI) are already present in the page request interface (page request interface, PRI), the device will use existing fields in the RRI message of the RRI and, in addition, the remaining fields will be transmitted in additional fields or separate channels, queues or methods. A responder receiving a PRI message will read the additional field from the additional field or from a separate channel/queue/method and treat this message as an RRI request instead of a PRI request.

According to another embodiment, another possible way to implement the range request interface (range request interface, RRI) response is to reuse existing page request interface (page request interface, PRI) responses and transmit additional parameters in a separate channel. Since some of the fields in the RRI are already present in the PRI, the central processing unit will use existing fields in the RRI message of the RRI, and furthermore, the remaining fields described above will be transmitted as additional fields or in a separate channel, queue or method. Devices receiving the PRI message will read the additional fields from a separate channel, queue, or method and treat this message as an RRI response instead of a PRI response.

While a particular feature or aspect of the invention may have been disclosed with respect to only one of several implementations or embodiments, such feature or aspect may be combined with one or more other features or aspects of the other implementations or embodiments, as may be desired and advantageous for any given or particular application. Moreover, to the extent that the terms "includes," has, "" having, "or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term" comprising. Also, the terms "exemplary," "such as," and "for example," are merely meant as examples, rather than as being best or optimal. The terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms may be used to indicate that two elements co-operate or interact with each other regardless of whether they are in direct physical or electrical contact or they are not in direct contact with each other.

Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

Although elements in the above claims are recited in a particular order with corresponding labeling, unless the claim recitations otherwise imply a particular order for implementing some or all of those elements, those elements are not necessarily limited to being implemented in that particular order.

Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art will readily recognize that there are numerous other applications of the present invention in addition to those described herein. While the invention has been described in connection with one or more specific embodiments, those skilled in the art will recognize that many changes may be made thereto without departing from the scope of the present invention. It is, therefore, to be understood that within the scope of the appended claims and equivalents thereof, the invention may be practiced otherwise than as specifically described herein.

Claims

1. A memory device (601), characterized by comprising:

a memory (603) arranged to comprise a physical memory unit;

an interface (607) for receiving a request message from a requesting entity (631) for requesting access to a virtual address range, the virtual address range being associated with at least two virtual memory units;

a memory controller (605) for allocating a plurality of physical memory units in the memory to a sub-range of the virtual address range and mapping physical addresses of the plurality of physical memory units to the sub-range of the virtual address range;

a memory address translator (609) for generating address information indicating the sub-range of the virtual address range to which the physical address is mapped;

wherein the interface (607) is configured to send a response message to the requesting entity (631), the response message comprising the address information.

2. The memory device (601) according to claim 1, characterized in that,

the memory controller (605) is configured to determine whether the plurality of physical memory units are available in the memory (603) prior to allocating the plurality of physical memory to the sub-range of the virtual address range, and wherein,

The memory address translator (609) is configured to generate an indication that the request cannot be granted if the memory controller (605) determines that the plurality of physical memory units are not available, and wherein the interface (607) is configured to send a rejection message to the requesting entity (631), the rejection message comprising the indication.

3. The memory device (601) according to claim 1 or 2, characterized in that,

the memory controller (605) is configured to allocate a further plurality of physical memory units in the memory (603) to a further sub-range of the virtual address range and map physical addresses of the further plurality of physical memory units with the further sub-range of the virtual address range;

-the memory address translator (609) is configured to generate further address information indicating the further sub-range of the virtual address range to which the physical address is mapped;

the interface (607) is configured to send a further response message to the requesting entity (631), the further response message comprising the further address information.

4. The memory device (601) according to claim 3, characterized in that,

The memory controller (605) is configured to determine whether the further plurality of physical memory units are available in the memory (603) before allocating the further plurality of physical memory to the further sub-range of the virtual address range, and wherein,

the memory address translator (609) is configured to determine whether the further plurality of physical memory units are available based on the memory controller (605), generate a further indication indicating whether the further sub-range requesting access to the virtual address range may be authorized, and wherein,

the interface (607) is for sending the further response message to the requesting entity (631), the further response message comprising the further address information and the further indication.

5. The memory device (601) according to any one of the preceding claims, wherein the request message comprises an identifier identifying the request message, wherein the memory address translator (609) is arranged to include the identifier in the response message, and/or a responder identifier identifying the memory address translator (609) and/or a requester identifier identifying the requesting entity (631).

6. The memory device (601) according to any one of the preceding claims 2 to 5, wherein if the memory controller (605) determines that the plurality of physical memory units are not available,

the memory address translator (609) is configured to generate a state indication indicating one of the following states: requesting access to the virtual address range fails; requesting access to the virtual address range is invalid; requesting access to the virtual address range may be resent; and wherein the first and second heat sinks are disposed,

the interface (607) is configured to send the rejection message to the requesting entity (631), the rejection message comprising the status indication.

7. The memory device (601) according to claim 6, wherein if the status indication indicates that the request to access the virtual address range can be resent,

the memory address translator (609) is configured to generate a retry time indication indicating a time period for resending the request message, wherein the retry time indication is configured to enable the requesting entity (631) to resend a request message requesting access to the virtual address range after the time period after the requesting entity receives the rejection message.

8. The memory device (601) according to any one of claims 4 to 7, wherein if the memory controller (605) determines that the further plurality of physical memory units are not available in the memory (603),

the memory address translator (609) is configured to generate a further state indication indicative of one of the following states: requesting access to the other sub-range of the virtual address range fails; requesting access to the other sub-range of the virtual address range is invalid; the further sub-range requesting access to the virtual address range may be sent; and wherein the first and second heat sinks are disposed,

the interface (607) is for sending the further response message to the requesting entity (631), the further response message comprising the further status indication.

9. The memory device (601) according to claim 8, wherein if the further status indication indicates that the further sub-range requesting access to the virtual address range can be sent,

the memory address translator (609) is configured to generate a retry time indication indicating a further time period for sending a further request message, wherein the retry time indication is configured to enable the requesting entity (631) to send the further request message requesting access to the further sub-range of the virtual address range after the further time period after the further response message is received by the requesting entity.

10. The memory device (601) according to any one of the preceding claims, wherein the request message comprises a threshold indication indicating a maximum number of response messages allowed to be sent to the requesting entity (631), wherein,

the memory controller (605) is further configured to allocate each physical memory unit of a set of a plurality of physical memory units in the memory (603) to a respective one of a set of sub-ranges of the virtual address range, and map each physical memory unit of the set of physical memory units with a respective sub-range of the virtual address range of the set of sub-ranges of the virtual address range, wherein,

the memory address translator (609) is configured to:

-generating a set of address information based on the set of sub-ranges of the virtual address range, each address information in the set of address information indicating a respective sub-range of the virtual address range in the set of sub-ranges of the virtual address range;

-including each address information of the set of address information into a respective response message of a set of response messages for requesting access to the set of sub-ranges of the virtual address range, respectively; wherein,

-if the number of response message sets is equal to or smaller than the maximum number, the interface (607) is for sending the response message sets to the requesting entity (631);

the interface (607) is configured to send a subset of the set of response messages to the requesting entity (631) if the number of the set of response messages is greater than the maximum number, the number of the subset of the set of response messages being equal to the maximum number.

11. The memory device (601) according to claim 10, wherein the memory address translator (609) is configured to generate a response indication to indicate whether a response message of the set of response messages is a last response message to be sent to the requesting entity (631), wherein the memory address translator (609) is further configured to include the response indication in the response messages of the set of response messages, the response message being a last response message to be sent to the requesting entity (631).

12. The memory device (601) according to any one of the preceding claims, wherein the request message comprises an indication indicating a relaxed transmission order,

Wherein, the memory controller (605) is further configured to:

-assigning each physical memory unit of a set of a plurality of physical memory units in the memory (603) to a respective one of a set of sub-ranges of the virtual address range, and mapping each physical memory unit of the set of physical memory units with a respective sub-range of the virtual address range of the set of sub-ranges of the consecutive virtual address ranges;

wherein the memory address translator (609) is configured to:

-generating a set of address information based on the set of sub-ranges of the virtual address range, each address information in the set of address information indicating a respective sub-range of the virtual address range, a respective plurality of physical memory units in the set of physical memory units being mapped to a respective sub-range of the virtual address range; and including each address information of the set of address information into a corresponding response message of a set of response messages;

-generating a set of sequence numbers based on the sub-range sets of the virtual address range, respective address information of the set of address information being mapped to each of the sub-range sets;

Assigning each sequence number of the sequence number set to a corresponding response message of the set of response messages for responding to a request to access the sub-range set of the virtual address range according to an order in which the memory controller (605) assigns a point in time of a corresponding one of the plurality of sets of physical memory units,

wherein the interface (607) is configured to send the set of response messages according to the order of the set of sequence numbers.

13. The memory device (601) according to any one of the preceding claims, wherein the memory address translator (609) is integrated within the memory controller (605) or is a stand-alone device interconnected to the memory controller (605) through another interface.

14. A requesting entity (631) for requesting access to a virtual address range, wherein the requesting entity (631) is configured to:

transmitting a request message for requesting access to the virtual address range, the virtual address range being associated with at least two virtual memory units;

a response message is received comprising address information indicating a sub-range of the virtual address range that the requesting entity (631) is allowed to access.

15. The requesting entity (631) of claim 14, wherein the requesting entity (631) is configured to receive a further response message comprising further address information indicating a further sub-range of the virtual address range to which the requesting entity (631) is allowed to access.

16. The requesting entity (631) of claim 14 or 15, wherein the requesting entity (631) is configured to define the virtual address range as a range from a starting virtual address plus a virtual memory unit length or a range between a starting virtual address and an ending virtual address.

17. The requesting entity (631) according to any of claims 14 to 16, wherein the requesting entity (631) is further configured to include in the request message a threshold indication indicating a maximum number of response messages allowed to be sent to the requesting entity (631) for responding to the request message.

18. The requesting entity (631) according to any of claims 14 to 17, wherein the requesting entity (631) is configured to include in the request message one or more of: a requester identifier identifying the requesting entity (631), a responder identifier identifying a responding entity responding to the request message, an identifier identifying the request message, and a flag comprising at least one access right requested by the requesting entity (631), the at least one access right being associated with a range of virtual memory addresses, in particular written, read, executed, not read, not written or not executed.

19. The requesting entity (631) according to any of claims 14 to 18, wherein the requesting entity (631) is configured to receive a rejection message indicating that access to the virtual address range cannot be granted and a retry time indication indicating a time period for retransmitting the request message, wherein the requesting entity (631) is configured to retransmit the request message after the time period after the rejection message is received by the requesting entity (631).

20. The requesting entity (631) of any of claims 14 to 19, wherein the requesting entity (631) is configured to receive a second further response message indicating that a second further sub-range requesting access to the virtual address range cannot be authorized, and to send a further retry time indication of a further time period for a further request message requesting access to the second further sub-range of the virtual address range, wherein the requesting entity (631) is configured to send the further request message after the further time period after the second further response message is received by the requesting entity.

21. The requesting entity (631) according to any of claims 14 to 20, wherein the requesting entity (631) is configured to include in the request message an indication indicating a relaxed sending order and to enable the responding entity to send to the requesting entity a response message earlier than another response message, the response message indicating a sub-range of the virtual address range that the requesting entity (631) is allowed to access and the other response message indicating another sub-range of the virtual address range that the requesting entity is allowed to access, wherein the sub-range of the virtual address range is accessed by the requesting entity before the other sub-range of the virtual address range.