EP4121861A1

EP4121861A1 - Devices for memory management

Info

Publication number: EP4121861A1
Application number: EP20733408.7A
Authority: EP
Inventors: Ben-Shahar BELKAR; Ronen Hyatt; Lior Khermosh; Alex Margolin; Guy Shattah
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-06-16
Filing date: 2020-06-16
Publication date: 2023-01-25
Also published as: WO2021254598A1; CN116034346A

Abstract

The present disclosure relates to a requesting entity configured to request access to a range of virtual addresses and to a memory arrangement configured to allocate physical memory to the range of virtual addresses and to make the requested virtual addresses available to the requesting entity. Embodiments thereof enable to request multiple pages over a single range, which minimizes the number of requests and hence allows for reduced the request queue size. As the number of request messages significantly decreases, embodiments of the present invention also minimize communication volume between the requesting entity and the memory arrangement. Furthermore, embodiments of the invention allow for multiple responses for the same request, wherein each response refers to a subrange of the range of virtual addresses requested. This enables the requesting entity to immediately start DMA to parts of the translated addresses and the memory arrangement to translate a range of memory pages.

Description

DEVICES FOR MEMORY MANAGEMENT

TECHNICAL FIELD

In general, the present invention relates to the field of memory management. More specifically, the embodiments of the present disclosure relate to a device configured to request access to virtual addresses and a memory arrangement configured to allocate physical memory to the virtual addresses.

BACKGROUND An Address Translation Service (ATS) is a Peripheral Component Interconnect Express (PCIe) service which enables a computer system to use a translation agent to translate addresses from a virtual address provided by an I/O device (i.e. an endpoint) to a physical address in a system memory. An example illustrating a computer system 100 comprising a translation agent 101 , an Address Translation and Protection Table (ATPT) 103 and Address Translation Cache (ATC) elements 107a-d is shown in figure 1 as disclosed in PCI Express 5.0 specification. The translation agent 101 accesses the Address Translation and Protection Table (ATPT) 103 to check access rights and translation addresses. The endpoint (EP) 105a-d may cache an address translation entry from the system-level Address Translation and Protection Table (ATPT) inside an Address Translation Cache (ATC).

However, the known address translation concept is complex and inefficient, which results in an increased communication volume between a translation agent and endpoints in a computer system.

Therefore, there is a need for improved devices for memory arrangement.

SUMMARY

It is an object of the invention to provide an improved device for requesting access to virtual addresses, as well as an improved device for allocating physical memory to the virtual addresses more efficiently. The foregoing and other objects are achieved by the subject matter of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

Generally, the present disclosure relates to a requesting entity configured to request access to virtual addresses as well as a memory arrangement configured to allocate physical memory to the virtual addresses and to make the requested virtual addresses available to the requesting entity.

In contrast to the state-of-the-art page request interface, embodiments of the present invention enable to request multiple pages over a single range, which minimizes the number of requests and hence allows for reduced requests queue size. As the number of request messages significantly decreases, embodiments of the present invention also minimize communication volume between an endpoint and a translation agent as mentioned above, decreasing the number of software interrupts.

Furthermore, embodiments of the present disclosure allow for multiple responses for the same request, wherein each response refers to a part of the requested range. This new type of response also allows for more efficient (software and hardware) algorithms: allowing the requesting device to immediately start direct memory access to parts of the translated addresses; and allowing software to translate a range of pages rather than one page at a time, which could considerably improve the page prefetching algorithms. This results in faster operation, reduced CPU load and better memory utilization.

In short, embodiments of the present disclosure provide two types of messages: a single request message for a range of pages rather than a page by page and a response message which can be used to respond only for part of the request, rather than a whole request. On top of these, multiple response messages may be sent as a reply for a single request which can request a range of virtual addresses associated with multiple contiguous ranges of physical addresses, while in the state-of-the-art page request interface there is only a single response per request.

More specifically, according to a first aspect the present disclosure relates to a memory arrangement which comprises: a memory arranged to comprise physical memory units; an interface configured to receive a request message for requesting access to a range of virtual addresses from a requesting entity; a memory controller configured to allocate a plurality of physical memory units in the memory to a subrange of the range of virtual addresses and to map physical addresses of the plurality of physical memory units with the subrange of the range of virtual addresses; a memory address translator configured to generate address information indicating the subrange of the range of virtual addresses to which the physical addresses are mapped.

After the address information is generated, the interface is then configured to send a response message comprising the address information towards the requesting entity in response to the request message.

In an embodiment, the requesting entity can be an Input/Output device, graphic card, network card or other peripheral devices and the range of requested virtual addresses is associated with at least two virtual memory units.

In light of the above, an improved memory arrangement is hence provided, allowing granting a partial range of virtual addresses in response to a request for a range of virtual addresses efficiently. This allows the requesting entity to begin direct memory access (DMA) to the partial range of virtual addresses, i.e. a part of the requested virtual memory that is already translated.

In a further possible implementation form of the first aspect, the memory controller is configured to determine whether the plurality of physical memory units is available in the memory prior to allocating the plurality of physical memory to the subrange of the range of virtual addresses, and the memory address translator is configured to generate an indication indicating that the request cannot be granted if the memory controller has determined that the plurality of physical memory units is not available, and the interface is configured to send a rejection message towards the requesting entity, the rejection message comprising the indication.

Thus, a rejection message indicating that the request cannot be granted can be sent to the requesting entity efficiently.

In a further possible implementation form of the first aspect, the memory controller is configured to allocate a further plurality of physical memory units in the memory to a further subrange of the range of virtual addresses and to map physical addresses of the further plurality of physical memory units with the further subrange of the range of virtual addresses. Accordingly, the memory address translator is configured to generate further address information indicating the further subrange of the range of virtual addresses to which the physical addresses are mapped, and the interface is configured to send a further response message comprising the further address information towards the requesting entity. Thus, an improved memory arrangement is provided, allowing that multiple response messages can be sent for answering a single request for a range of virtual addresses from the requesting entity. The multiple response messages comprise multiple subranges of the range of virtual addresses which may be associated with multiple contiguous ranges of physical addresses.

Embodiments of the invention allow the memory arrangement to translate a set of pages of virtual memory rather than one page at a time, improving considerably the page prefetching algorithm.

In a further possible implementation form of the first aspect, the memory controller is configured to determine whether the further plurality of physical memory units is available in the memory prior to allocating the further plurality of physical memory to the further subrange of the range of virtual addresses.

Depending on that the memory controller has determined whether the further plurality of physical memory units is available or not, the memory address translator is configured to generate a further indication indicating whether requesting access to the further subrange of the range of virtual addresses can be granted or not. The interface is configured to send the further response message comprising the further address information and the further indication towards the requesting entity.

Thus, two types of responses can be sent, including a “success” response indicating an un-translated range has been requested successfully or a “non-success” message indicating a requested range is not available.

An address translation service (ATS) is further required to request translation for the virtual addresses that have been successfully requested.

In a further possible implementation form of the first aspect, the request message comprising an identifier identifying the request message, wherein the memory address translator is configured to include into the response message: the identifier, and/or a responder identifier identifying the memory address translator and/or a requester identifier identifying the requesting entity.

Thus, multiple response messages responding to the same request message can be identified and sent efficiently. Further, the memory address translator and the requesting entity can also be identified with the responder identifier and request identifier respectively. In a further possible implementation form of the first aspect, if the memory controller has determined that the plurality of physical memory units is not available, the memory address translator is configured to generate a status indication indicating one of the following statuses: requesting access to the range of virtual addresses is failed; requesting access to the range of virtual addresses is invalid; requesting access to the range of virtual addresses can be re-sent. The interface is configured to send the rejection message comprising the status indication towards the requesting entity.

In a further possible implementation form of the first aspect, if the status indication indicates the requesting access to the range of virtual addresses can be resent, the memory address translator is configured to generate a retry-time indication indicating a period of time for resending the request message, wherein the retry-time indication is configured to allow the requesting entity to resend the request message for requesting access to the range of virtual addresses after the period of time once the requesting entity has received the rejection message.

In a further possible implementation form of the first aspect, if the memory controller has determined that the further plurality of physical memory units is not available in the memory, the memory address translator is configured to generate a further status indication indicating one of the following statuses: requesting access to the further subrange of the range of virtual addresses is failed; requesting access to the further subrange of the range of virtual addresses is invalid; requesting access to the further subrange of the range of virtual addresses can be sent.

The interface is configured to send the further response message comprising the further status indication towards the requesting entity.

In a further possible implementation form of the first aspect, if the further status indication indicates requesting access to the further subrange of the range of virtual addresses can be sent, the memory address translator is configured to generate a retry-time indication indicating a further period of time for sending a further request message.

The retry-time indication is configured to allow the requesting entity to send the further request message for requesting access to the further subrange of the range of virtual addresses after the further period of time once the requesting entity has received the further response message.

In a further possible implementation form of the first aspect, the request message comprises a threshold indication indicating a maximum number of response messages which are allowed to be sent towards the requesting entity, and the memory controller is further configured to allocate each of a set of pluralities of physical memory units in the memory to a respective one of a set of subranges of the range of virtual addresses, and map each of the set of pluralities of physical memory units with the respective subrange of the range of virtual addresses from the set of subranges of the range of virtual addresses.

Further, the memory address translator is configured to: generate a set of address information on the basis of the set of subranges of the range of virtual addresses, each of the set of address information indicating a respective subrange of the range of virtual addresses from the set of subranges of the range of virtual addresses; include each of the set of address information into a respective response message of a set of response messages for responding to requesting access to the set of subranges of the range of virtual addresses respectively.

If the number of the set of response messages is equal to or smaller than the maximum number, the interface is configured to send the set of response messages towards the requesting entity.

If the number of the set of response messages is larger than the maximum number, the interface is configured to send a subset of the set of response messages towards the requesting entity, the number of the subset of the set of response messages being equal to the maximum number.

In a further possible implementation form of the first aspect, the memory address translator is configured to generate a response indication to indicate whether a response message of the set of response messages is the last response message to be sent to the requesting entity, and the memory address translator is further configured to include the response indication into the response messages of the set of response messages that is the last response message to be sent to the requesting entity.

In a further possible implementation form of the first aspect, the request message comprises an indication indicating a relaxed-sending order. In this respect, the memory controller is further configured to: allocate each of a set of pluralities of physical memory units in the memory to a respective one of a set of subranges of the range of virtual addresses and map each of the set of pluralities of physical memory units with the respective subrange of the range of virtual addresses from the set of subranges of the range of virtual addresses in succession. The memory address translator is configured to: generate a set of address information on the basis of the set of subranges of the range of virtual addresses, each of the set of address information indicating a respective subrange of the range of virtual addresses to which the respective plurality of physical memory units from the set of pluralities of physical memory units is mapped and include each address information of the set of address information into a respective response message of a set of response messages; generate a set of serial numbers on the basis of the set of subranges of the range of virtual addresses to each of which respective address information of the set of address information are mapped; assign each of the set of serial numbers to a respective response message of the set of response messages for responding to requesting access to the set of subranges of the range of virtual addresses, according to an order of time points at each of which the respective one of the set of pluralities of physical memory units is allocated by the memory controller.

The interface is configured to send the set of response messages according to the order of the set of serial numbers.

Therefore, the interface of the memory arrangement can send response messages without following the order of the requested range. Once the requesting entity receives any response message indicating availability of a subrange of the range of virtual addresses, the requesting entity can immediately start direct memory access DMA to the subrange of the range of virtual addresses without waiting for the grant of the whole range of virtual addresses.

In a further possible implementation form of the first aspect, the memory address translator is integrated within the memory controller or being an independent device interconnected with the memory controller via another interface.

According to a second aspect the present disclosure relates to a requesting entity for requesting access to a range of virtual addresses. In this respect, the requesting entity is configured to send a request message for requesting access to the range of virtual addresses, wherein the range of virtual addresses is associated with at least two virtual memory units.

In an embodiment, the requesting entity can send the request message to the memory arrangement according to the first aspect. If the memory arrangement allows the requesting entity to access a subrange of the range of virtual addresses, the requesting entity is configured to receive a response message comprising address information indicating the subrange of the range of virtual addresses which the requesting entity is allowed to access.

In an embodiment, the requesting entity is a peripheral device such as an I/O device, graphic card, network card or other peripheral devices and communicates with the memory arrangement via an interface such as a bus.

In a further possible implementation form of the second aspect, the requesting entity is configured to receive a further response message comprising further address information indicating a further subrange of the range of virtual addresses which the requesting entity is allowed to access.

Thus, an improved requesting entity is provided, allowing requesting more than one virtual memory unit, i.e. more than one page of virtual memory at a time. The requesting entity is able to request translation for a range of memory rather than page after page, which reduces the number of messages between the requesting entity and the memory arrangement and improves bandwidth of the bus between these two entities.

Besides, the requesting entity is allowed to begin direct memory access (DMA) to the subrange of the range of virtual addresses without waiting for the grant of the whole range of virtual addresses.

In a further possible implementation form of the second aspect, the requesting entity is configured to define the range of virtual addresses as a range from a starting virtual address plus a length of virtual memory units or as a range between a starting virtual address and an ending virtual address.

Thus, the requesting entity is allowed to request a range of virtual addresses efficiently.

In a further possible implementation form of the second aspect, the requesting entity is further configured to include a threshold indication into the request message, wherein the threshold indication indicates a maximum number of response messages for responding to the request message which are allowed to be sent towards the requesting entity.

In a further possible implementation form of the second aspect, the requesting entity is configured to include one or more of the following into the request message: a requester identifier identifying the requesting entity, a responder identifier identifying a responding entity responding to the request message, a identifier identifying the request message, and a flag comprising at least one access permission requested by the requesting entity associated with the range of virtual memory addresses, in particular, write, read, execute, no-read, no-write, or no execute.

In a further possible implementation form of the second aspect, the requesting entity is configured to receive a rejection message indicating that requesting access to the range of virtual addresses cannot be granted and a retry-time indication indicating a period of time for resending the request message. In this respect, the requesting entity is configured to resend the request message after the period of time, after the requesting entity has received the rejection message.

Thus, the requesting entity is able to re-send a request for access to the range of virtual addresses efficiently.

In a further possible implementation form of the second aspect, the requesting entity is configured to receive a second further response message indicating that requesting access to a second further subrange of the range of virtual addresses cannot be granted and a further retry-time indication indicating a further period of time for sending a further request message for requesting access to the second further subrange of the range of virtual addresses. In this respect, the requesting entity is configured to send the further request message after the further period of time, after the requesting entity has received the second further response message.

Thus, the requesting entity is able to send another request for access to a subrange of virtual addresses efficiently without requesting for the whole range of virtual addresses.

In a further possible implementation form of the second aspect, the requesting entity is configured to include an indication indicating a relaxed-sending order into the request message and to allow the responding entity to send a response message earlier than a further response message towards the requesting entity, wherein the response message indicates a subrange of the range of virtual addresses the requesting entity is allowed to access and the further response message indicates a further subrange of the range of virtual addresses the requesting is allowed to access. In an embodiment, the subrange of the range of virtual addresses is made to accessible to the requesting entity earlier than the further subrange of the range of virtual addresses.

Thus, the requesting entity can access a subrange of the range of virtual addresses once this subrange of the range of virtual addresses is available to the requesting entity, i.e. the requesting entity can immediately start direct memory access DMA to the subrange of the range of virtual addresses without waiting for the grant of the whole range of virtual addresses.

BRIEF DESCRIPTION OF THE DRAWINGS

Further embodiments of the present disclosure will be described with respect to the following figures, wherein:

Figure 1 shows a schematic diagram of a computer system comprising a translation agent, an Address Translation and Protection Table (ATPT) and address translation cache (ATC) elements;

Figure 2 shows an exemplary System Memory Management Unit (SMMU) architecture; Figure 3 shows a schematic diagram illustrating an exemplary interaction procedure between a translation agent and an Address Translation Cache (ATC) within a PCIe device;

Figure 4 shows a schematic diagram illustrating a process of an Address Translation Service (ATS) cache invalidation; Figure 5 shows an exemplary process flow of requesting page via a state-of-the-art Page Request Interface;

Figure 6 shows a schematic diagram illustrating a computer system comprising a memory arrangement and a requesting entity according to an embodiment;

Figure 7 shows an exemplary procedure according to an embodiment of requesting for a range of virtual addresses by a requesting entity from a memory arrangement;

Figure 8 further shows an exemplary procedure of requesting for a range of virtual addresses by a requesting entity according to an embodiment from a memory arrangement according to an embodiment;

Figure 9 shows an implementation of a request message which can be sent by a requesting entity according to an embodiment; and

Figure 10 shows an implementation of a response message which can be sent by a memory arrangement according to an embodiment.

In the various figures, identical reference signs will be used for identical or at least functionally equivalent features. DETAILED DESCRIPTION OF EMBODIMENTS

In the following description, reference is made to the accompanying drawings, which form part of the disclosure, and in which are shown, by way of illustration, specific aspects in which the present invention may be placed. It will be appreciated that other aspects may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, as the scope of the present invention is defined by the appended claims.

For instance, it will be appreciated that a disclosure in connection with a described method may also hold true for a corresponding device or system configured to perform the method and vice versa. For example, if a specific method step is described, a corresponding device may include a unit to perform the described method step, even if such unit is not explicitly described or illustrated in the figures.

Moreover, in the following detailed description as well as in the claims embodiments with different functional blocks or processing units are described, which are connected with each other or exchange signals. It will be appreciated that the present invention covers embodiments as well, which include additional functional blocks or processing units that are arranged between the functional blocks or processing units of the embodiments described below. Finally, it is understood that the features of the various exemplary aspects described herein may be combined with each other, unless specifically noted otherwise.

Figure 2 shows an exemplary System Memory Management Unit (SMMU) architecture 200 for ARM processors, wherein the SMMU system 201 has a translation buffer unit (TBU) 203a, b which intercepts transactions in need of translation and translates the addresses of those transactions.

Caching of entries in the Address Translation and Protection Table (ATPT) allows the endpoint to request a Direct Memory Access (DMA) transfer using an address that has been pre-translated, so the Address Translation and Protection Table (ATPT) does not have to be fetched from the memory in series with the operation of Direct Memory Access (DMA), which hence reduces the latency of the operation.

Figure 3, taken from PCI specification, v10.1.1 Address Translation Services Overview, shows how a translation agent 301 and an Address Translation Cache (ATC) 307 within a PCIe device (i.e. an endpoint) 305 interact. As the PCIe device 305 sends a request of address translation service (ATS) to the translation agent 301 , the translation agent 301 performs the following basic steps:

1. Capabilities: the translation agent 301 tests that the PCIe device 305 has been configured to issue ATS translation requests. 2. Memory access rights: the translation agent 301 determines whether the PCIe device 305 may access the memory 321 indicated by the ATS translation request and if the PCIe device 305 has the associated access rights.

3. Availability: the translation agent 301 determines whether a translation can be provided to the PCIe device 305. If yes, the translation agent 301 issues a translation.

4. The translation agent 301 communicates the success or failure of the request to a Root Complex (RC) 311 which generates an ATS Translation Completion and transmits via a Response Transaction Layer Packet (TLP) through a Root Port 313 to the PCIe device 305. A successful translation can result in one or two ATS translation completion TLPs per request. The translation completion indicates the range of translation covered. The Root Complex (RC) 311 is required to transmit the ATS Translation Completion using the same Traffic Class (TC) as the corresponding ATS request.

The requested address may not be valid. The Root Complex (RC) is required to issue a completion indicating that the requested address is not accessible.

Figure 4, taken from PCI specification, v10.1.1 Address Translation Services Overview, shows a process of an ATS cache invalidation:

Step 401 : the translation agent 301 sends an invalidate-request to the Address Translation Cache (ATC) 307. Step 403: the PCIe device 305 completes DMA transfers and then flush the Address Translation Cache (ATC) 307 or discard conflicting reads.

Step 405: the Address Translation Cache (ATC) 307 on the PCIe device 305 sends invalidate-completion to the translation agent 301.

Step 407: After invalidate-completions were received from all the ATC Address Translation Caches 307 inside all PCIe devices 305 on the system, the translation agent 301 removes the entry. A Page Request Interface (PRI) adds the ability for a PCIe devices or a function to target direct memory access (DMA) at unpinned dynamically-paged memory. If an address translation service (ATS) responds with a translation failure for a range of memory pages, then the PCIe device (i.e. endpoint) possibly issues multiple PRI page requests to ask software (i.e. an operation system) to make the requested pages resident.

The software receives these PRI Page Requests from the Page Request Interface (PRI) queue via an IOMMU interface and can also receive an interrupt. The software further issues a positive PRI response command to the System Memory Management Unit (SMMU) after making pages resident in the RAM memory. If a requested address is unavailable or a programming failure has caused the device to request an illegal address, then the PCIe device received a failure response.

PCIe devices or functions may send multiple requests using the same Page Request Group (PRG). In this case there is a single response for all pages requested in the same Page Request Group (PRG). Once a PRI response is received the devices can issue another ATS request to get the translation of the requested pages.

As the Page Request Interface (PRI) requests one page at a time, multiple requests must be made for a range of virtual memory. When the requested pages do not share the same Page Request Group (PRG) then also multiple software interrupts are raised.

An exemplary process flow of requesting page via a state-of-the-art Page Request Interface can be the following:

1. A function or a PCIe device determines that it requires access to a page for which an address translation service (ATS) translation is not available.

2. The function causes the associated Page Request Interface (PCI) to send a page request message to its Root Complex. A page request message contains a page address and a Page Request Group (PRG) index. The PRG index is used to identify the transaction and is used to match requests with responses.

3. When the Root Complex determines its response to the request (which will typically be to make the requested page resident in the memory), it sends a response message associated with the Page Request Group (PRG) back to the requesting function.

4. The function can then employ an address translation service (ATS) to request a translation for the requested page. In view of the above, the state-of-the-art Page Request Interface (PRI) allows only requesting a single page per request or possibly grouping multiple pages together within the same request group. Furthermore, merely a response message is sent once for multiple requests and contains a result indicating either success or failure. As the Page Request Interface (PRI) requests one page at a time, multiple requests must be made for a range of virtual memory. When the requested pages do not share the same Page Request Group (PRG) then also multiple software interrupts are raised.

Figure 5 shows an exemplary process flow 500 of requesting page via a state-of-the-art Page Request Interface:

Step 511 a-f: an endpoint 501 e.g. a PCIe device sends multiple request messages to a translation agent 503 for requesting access to a range of virtual memory and group multiple pages together within a request group, wherein each request message only requests one page at a time.

Step 513a-f: the translation agent 503 further transmits these multiple request messages to an operation system or a central processing unit (CPU) 505.

Step 515: the operation system or CPU 505 merely sends a response message indicating completion for multiple requests.

Step 517: the translation agent 503 forwards the response message indicating completion to the endpoint 501.

In contrast, embodiments of the invention further provide a first improvement on messages transmitted between the endpoint and the translation agent, i.e. contents of a request and a completion message and a second improvement on a logical flow, i.e. how such messages should be handled between the endpoint and the translation agent.

In this respect, embodiments of the invention involve a requesting entity configured to request access to virtual addresses and a memory arrangement configured to allocate physical memory to the virtual addresses and to make the requested virtual addresses available to the requesting entity.

More specifically, embodiments of the invention can be implemented in a computer system 600, which has a general architecture as shown in figure 6. In the embodiment shown in figure 6 the communication system 600, by way of example, comprises a requesting entity 631 configured to request access to virtual addresses and a memory arrangement 601 configured to allocate physical memory to the virtual addresses and to make the requested virtual addresses available to the requesting entity 631.

In an embodiment, the requesting entity 631 is an external device such as an I/O device, graphic card, network card or other peripheral devices and communicates with the memory arrangement via an interface such as a bus.

As can be taken from the detailed view shown in figure 6, the memory arrangement 601 comprises: a memory 603 comprising physical memory units; an interface 607 configured to communicate with the external device; a memory controller 605 configured to allocate physical memory units in the memory to virtual addresses; and a memory address translator 609. In an embodiment, the memory address translator 609 is integrated within the memory controller 605 or being an independent device interconnected with the memory controller 605 via another interface such as a bus.

In an embodiment, the requesting entity 631 is configured to send a request message for requesting access to a range of virtual addresses, for instance, the requesting entity 631 can define the range of virtual addresses as a range from a starting virtual address plus a length of virtual memory units or as a range between a starting virtual address and an ending virtual address. The range of virtual addresses is associated with at least two virtual memory units. As an example, the requesting entity requests access to a range of virtual addresses from 0x80000000 to 0x80100000.

In another embodiment, the requesting entity 631 may include one or more of the following into the request message: a requester identifier identifying the requesting entity 631 itself, a responder identifier identifying a responding entity responding to the request message, a identifier identifying the request message, and a flag comprising at least one access permission requested by the requesting entity associated with the range of virtual memory addresses, such as, “write”, “read”, “execute”, “no-read”, “no-write”, or “no execute”.

In an embodiment, the responding entity 631 for responding to the request message is the memory arrangement and the interface of the memory arrangement 601 is configured to receive the request message from the requesting entity 631. After the reception of the request, the memory controller 605 is configured to allocate a plurality of physical memory units in the memory 603 to a subrange of the range of virtual addresses and to map physical addresses of the plurality of physical memory units with the subrange of the range of virtual addresses. In a further embodiment, the memory controller 605 is configured to determine whether the plurality of physical memory units is available in the memory prior to allocating the plurality of physical memory to the subrange of the range of virtual addresses. If the memory controller 605 has determined that the plurality of physical memory units is available, the memory address translator 609 is configured to generate address information indicating the subrange of the range of virtual addresses to which the physical addresses are mapped.

In an embodiment, the memory address translator 609 may also generate one or more of the following information: the identifier, and/or a responder identifier identifying the memory address translator and/or a requester identifier identifying the requesting entity 631. The information may be included into a response message for responding the request message from the requesting entity 631.

After the address information is generated, the interface 607 of the memory arrangement 601 is then configured to send a response message comprising the address information towards the requesting entity 631 , in response to the request message. The requesting entity 631 is configured to receive the response message. Thus, the requesting entity 631 receives the address information that indicates the subrange of the range of virtual addresses which the requesting entity is allowed to access.

On the other hand, if the memory controller 605 has determined that the plurality of physical memory units is not available, the memory address translator 609 is configured to generate an indication indicating that the request cannot be granted.

In a further embodiment, the memory address translator may also generate a status indication indicating one of the following statuses: requesting access to the range of virtual addresses is failed; requesting access to the range of virtual addresses is invalid; requesting access to the range of virtual addresses can be re-sent.

In a further embodiment, if the status indication indicates the requesting access to the range of virtual addresses can be resent, the memory address translator 609 is configured to generate a retry-time indication indicating a period of time for resending the request message, wherein the retry-time indication is configured to allow the requesting entity to resend the request message for requesting access to the range of virtual addresses after the period of time once the requesting entity has received the rejection message. The interface 607 is configured to send a rejection message comprising the indication and/or the status indication and/or the retry-time indication towards the requesting entity 631.

In an embodiment, if the requesting entity 631 receives a rejection message indicating that requesting access to the range of virtual addresses cannot be granted and a retrytime indication indicating a period of time for resending the request message, the requesting entity 631 is configured to resend the request message after the period of time, after the requesting entity has received the rejection message.

In a further embodiment, the memory controller 605 is configured to determine whether a further plurality of physical memory units is available in the memory 603 prior to allocating the further plurality of physical memory to a further subrange of the range of virtual addresses.

If the further plurality of physical memory units is available, the memory controller 605 is configured to allocate the further plurality of physical memory units in the memory 603 to the further subrange of the range of virtual addresses and to map physical addresses of the further plurality of physical memory units with the further subrange of the range of virtual addresses. Also, the memory address translator 609 is configured to generate further address information indicating the further subrange of the range of virtual addresses to which the physical addresses are mapped.

In an embodiment, the memory address translator 609 may generate a further indication indicating whether requesting access to the further subrange of the range of virtual addresses can be granted or not, depending on that the memory controller 605 has determined whether the further plurality of physical memory units is available or not.

The interface 607 is configured to send a further response message comprising the further address information and/or the further indication towards the requesting entity 631. Correspondingly, the requesting entity 631 is configured to receive the further response message comprising the further indication and/or the further address information indicating the further subrange of the range of virtual addresses which the requesting entity is allowed to access.

If the memory controller 605 has determined that the further plurality of physical memory units is not available in the memory 603, the memory address translator 609 may also generate a further status indication indicating one of the following statuses: requesting access to the further subrange of the range of virtual addresses is failed; requesting access to the further subrange of the range of virtual addresses is invalid; requesting access to the further subrange of the range of virtual addresses can be sent.

If the further status indication indicates requesting access to the further subrange of the range of virtual addresses can be sent, the memory address translator 609 is configured to generate a retry-time indication indicating a further period of time for sending a further request message. The retry-time indication is configured to allow the requesting entity to send the further request message for requesting access to the further subrange of the range of virtual addresses after the further period of time once the requesting entity has received the further response message.

The interface 607 is configured to send towards the requesting entity 631 the further response message comprising the further status indication, and the retry-time indication if the further status indication indicates requesting access to the further subrange of the range of virtual addresses can be sent.

When the requesting entity 631 receives the further response message indicating that requesting access to the further subrange of the range of virtual addresses cannot be granted and the retry-time indication indicating the further period of time for sending a further request message for requesting access to the further subrange of the range of virtual addresses. In this respect, the requesting entity 631 is configured to send the further request message after the further period of time, after the requesting entity has received the further response message.

In an embodiment, the requesting entity 631 is further configured to include a threshold indication into the request message, wherein the threshold indication indicates a maximum number of response messages for responding to the request message which are allowed to be sent towards the requesting entity 631.

In this respect, the memory controller 605 is further configured to allocate each of a set of pluralities of physical memory units in the memory 603 to a respective one of a set of subranges of the range of virtual addresses, and map each of the set of pluralities of physical memory units with the respective subrange of the range of virtual addresses from the set of subranges of the range of virtual addresses. Further, the memory address translator 609 is configured to: generate a set of address information on the basis of the set of subranges of the range of virtual addresses, each of the set of address information indicating a respective subrange of the range of virtual addresses from the set of subranges of the range of virtual addresses; include each of the set of address information into a respective response message of a set of response messages for responding to requesting access to the set of subranges of the range of virtual addresses respectively.

If the number of the set of response messages is equal to or smaller than the maximum number, the interface 607 is configured to send the set of response messages towards the requesting entity 631. If the number of the set of response messages is larger than the maximum number, the interface 607 is configured to send a subset of the set of response messages towards the requesting entity 631 , the number of the subset of the set of response messages being equal to the maximum number.

In a further embodiment, the memory address translator may generate a response indication to indicate whether a response message of the set of response messages is the last response message to be sent to the requesting entity, and the memory address translator is further configured to include the response indication into the response messages of the set of response messages that is the last response message to be sent to the requesting entity 631.

In another embodiment, the requesting entity 631 is configured to include an indication indicating a relaxed-sending order into the request message and to allow the responding entity to send a response message earlier than a further response message towards the requesting entity 631 , wherein the response message indicates a subrange of the range of virtual addresses the requesting entity 631 is allowed to access and the further response message indicates a further subrange of the range of virtual addresses the requesting is allowed to access. In an embodiment, the subrange of the range of virtual addresses is made to accessible to the requesting entity earlier than the further subrange of the range of virtual addresses.

In this respect, the memory controller 605 is further configured to: allocate each of a set of pluralities of physical memory units in the memory 603 to a respective one of a set of subranges of the range of virtual addresses and map each of the set of pluralities of physical memory units with the respective subrange of the range of virtual addresses from the set of subranges of the range of virtual addresses in succession.

Also, the memory address translator 609 is configured to: generate a set of address information on the basis of the set of subranges of the range of virtual addresses, each of the set of address information indicating a respective subrange of the range of virtual addresses to which the respective plurality of physical memory units from the set of pluralities of physical memory units is mapped and include each address information of the set of address information into a respective response message of a set of response messages; generate a set of serial numbers on the basis of the set of subranges of the range of virtual addresses to each of which respective address information of the set of address information are mapped; assign each of the set of serial numbers to a respective response message of the set of response messages for responding to requesting access to the set of subranges of the range of virtual addresses, according to an order of time points at each of which the respective one of the set of pluralities of physical memory units is allocated by the memory controller.

Finally, the interface 607 is configured to send the set of response messages according to the order of the set of serial numbers. Therefore, the interface 607 of the memory arrangement 601 can send response messages without following the order of the requested range of virtual addresses.

An exemplary logical flow according to an embodiment is shown below:

1. The requesting entity 631 requests to access a range of virtual memory addresses which has no translation. 2. The requesting entity 631 sends a request message for an address translation service (ATS) to the memory address translator 609 and receives a failure result.

3. The requesting entity 631 sends a request message to the memory address translator 609.

4. On receiving the message, the memory address translator 609 triggers software interrupt.

5. The memory controller 605 tries to create translation between the requested range of addresses to physical addresses and updates tables associated with a memory management unit or a system memory management unit.

6. The memory controller 605 returns the result to the memory address translator 609. The memory address translator 609 sends response messages to the requesting entity 631. The result may comprise multiple messages made of two types: Translation success or non-success (some of the range is translated and some of it is not).

7. The requesting entity 631 accepts responses and then issues an Address Translation Service command to address ranges for which the translation succeeded. 8. In response to an indication “Please retry later” within a response message, the requesting entity 631 waits for the defined period of time and then retries.

Figure 7 shows an exemplary procedure 700 of requesting for a range of virtual addresses by a requesting entity 631 from a memory arrangement 601 , wherein the memory arrangement 601 comprises: a memory 603 comprising physical memory units; an interface 607 configured to communicate with the requesting entity 631 ; a memory controller 605 configured to allocate physical memory units in the memory 603 to virtual addresses; and a memory address translator 609.

The procedure 700 shown in figure 7 comprises the following steps:

Step 701 : The requesting entity 631 e.g. an endpoint sends a request message for requesting access to a range of virtual addresses from 0x80000000 to 0x80100000.

Step 703: the memory address translator 609, e.g. a translation agent further transmits the request message to the memory controller 605 i.e. an operation system or a central processing unit (CPU).

Step 705: the memory controller 605 sends a response message indicating completion for requested range.

Step 707: the memory address translator 609 forwards the response message indicating completion to the requesting entity 631.

While previously an endpoint had to send multiple Page Request Interface requests with the same Page Request Group, embodiments enable the endpoint to send a single request for requesting access to a range of virtual addresses.

This reduces the number of entries in the interrupt queue and the number of interrupt requests the operation system or the CPU receives from the system memory management unit.

Figure 8 further shows an exemplary procedure 800 of requesting for a range of virtual addresses by a requesting entity 631 from a memory arrangement 601 , wherein the memory arrangement 601 comprises: a memory 603 comprising physical memory units; an interface 607 configured to communicate with the requesting entity 631 ; a memory controller 605 configured to allocate physical memory units in the memory 603 to virtual addresses; and a memory address translator 609. The procedure 800 shown in figure 8 comprises the following steps:

Step 801 : The requesting entity 631 e.g. an endpoint sends a request message for requesting access to a range of virtual addresses from 0x80000000 to 0x80100000.

Step 803: the memory address translator 609, e.g. a translation agent further transmits the request message to the memory controller 605 i.e. an operation system or a central processing unit (CPU).

Step 805a-c: the memory controller 605 sends multiple response messages, each response message indicating a subrange of the range of virtual addresses that is available to the requesting entity 631 , for example, a first subrange can be 0x80000000- 0x80080000, a send subrange can 0x80080000-0x800A0000, a third subrange can 0x800A0000-0x80100000.

Step 807a-c: the memory address translator 609 forwards the multiple response messages to the requesting entity 631.

While previously a requesting entity 631 had to send multiple Page Request Interface requests with the same Page Request Group and receive a single response (which might be a failure response if at least one page cannot be translated).

In comparison, embodiments of the invention allow for sending a single request for a range of pages and receiving multiple responses. The multiple responses may be separated both in the time they are sent and in their contents. Some of them may indicate success and some failure. This enables the requesting entity to start direct memory access (DMA) on a subrange of virtual addresses on the basis of the partial response.

Embodiments of the invention may use the following request message sent from a PCIe device to a responder, wherein a responder is typically a translation agent. This request message may be either extension to the existing Page Request Interface request or a whole new message.

These are the fields suggested for the request message and some of them are optional and are implementation dependent:

1. A requested range of virtual addresses (mandatory), which describes a list of virtual address to be translated. This can be done in many ways. Some of the ways may include base-address and length or start address and end address, where each of these values may be represented directly or implicitly (for example, a range of 4k can be represented by the binary number 1101 and a range of 8k by 1001 , i.e. the representation is implementation specific.

2. A Range request group used to identify the request. This field is similar to Page Request Group in the Page Request Interface (mandatory) 3. A relaxed ordering allowed by a flag (optional, not needed if responses are always sent in order)

4. A maximum number of returned responses allowed.

5. Read, write, no-read, no-write, execute, no-execute flags (all flags are optional) that specify what is the expected or possible use-case for a translated range of pages.

6. A requester identifier/addresses (Optional, not needed when there is only a single device in the system)

7. A responder identifier/address (Optional, default can be the translation agent)

Figure 9 shows an implementation of a request message 900 which can be sent by a requesting entity according to an embodiment. The example is based on the existing

DTI_ATS _REQ message. DTI_ATS_REQ is part of Arm® AMBA® Distributed Translation Interface (DTI) Protocol Specification.

A field “REQ_RNG” bits [75:73] can be added, which indicates the range of addresses be requested. Values of the field are given in bits (binary) and are as following:

000 4 KB;

001 8 KB;

010 64 KB;

011 2 MB;

100 32 MB;

101 512 MB;

110 1 GB;

111 4 GB.

Embodiments of the invention may use the following response message sent from a responder, wherein a responder is typically a translation agent to a requesting entity. This message may be either extension to the existing Page Request Interface response or a whole new message. These are the fields suggested for the response message and some of them are optional and are implementation dependent:

1. A status (mandatory) indicating: a. successful translation b. failed translation (mandatory) c. invalid request d. Please retry after timeout (see comment at bottom of page) e. invalid request

2. A range of addresses (mandatory) that can be one of the following: range of untranslated virtual address, or distance from the base virtual address specified in the request + length of pages.

3. A range request group (RRG) which is used to identify the request. The role of this field is similar to the role of Page Request Group in Page Request Interface.

4. A last Flag, indicating that the current message in a series of response messages is the last one (mandatory).

5. A response serial number (optional, not needed if responses are sent in order) wherien this number orders the translated ranges when multiple response messages are sent per request. When the request sets a relaxed ordering flag then only the ‘last flag’ is used to denote end of responses. 6. A requester identifier/addresses (optional, not needed when only a single endpoint in the system).

7. A responder identifier /address (optional, default is the translation agent).

8. Time period to retry in case of re-try status (optional).

It is to be noted that the field 8 (time period to retry) and the response type 1.d (Please retry after timeout) are optional and they can be implemented together.

Figure 10 shows an implementation of a response message 1000 which can be sent by a memory arrangement according to an embodiment. The example is based on the existing DTI_ATS_RESP is part of Arm® AMBA® Distributed Translation Interface (DTI) Protocol Specification. The “RESP_RNG” and “STATUS” fields can be added and address bits can be extended. Values of the specific field are given in bits (binary) and are as following:

The field “RESP_RNG”, bits [10:8] indicates the valid range of addresses for response:

000 4 KB;

001 8 KB;

010 64 KB;

011 2 MB;

100 32 MB;

101 512 MB;

110 1 GB;

111 4 GB.

The field “STATUS”, bits [5:4] indicates the status of the Range Request Interface request:

00 request success;

01 request failed;

10 please retry after timeout;

11 invalid request.

According to an embodiment, a request message sent from a requesting entity such as an endpoint may comprise the following:

• A requested range of virtual addresses: 0x40000000 + length 0x8000

• A Range Request Group (RRG): 11

• If a relaxed ordering is allowed: not allowed

• A maximum number of returned responses allowed: 3

• Read, write, no-read, no-write, execute, no-execute flags: write, no-read, no execute.

In this respect, the requesting entity requests a memory range 0x40000000-0x40008000 for write-only with no more than 3 replies, the replies being in the Range Request Group, 11.

After receiving the above request message, a responder such as a memory arrangement can send the following response messages: 1 contiguous blocks + 1 untranslated + 1 contiguous blocks

• Status: success, range 0x40000000-0x40000FFF, RRG:11 , non-last response. Note that this is an untranslated address (i.e. virtual address)

• Status: success, range 0x40001000-0x40002FFF, RRG:11 , non-last response. Note that this is an untranslated address (i.e. virtual address)

• Status: success, range 0x40003000-0x40004FFF, RRG:11 , last response.

Note that this is an untranslated address (i.e. virtual address)

For the requested range 0x40005000-0x40008000, responses are not sent as the maximum number of responses allowed is only 3.

According to a further embodiment, a request message sent from a requesting entity such as an endpoint may comprise the following:

• A requested range of virtual addresses: 0x40000000 + length 0x8000

• A Range Request Group (RRG): 11

• A relaxed ordering allowed: not allowed

• A maximum number of returned responses allowed: 3

After receiving the above request message, a responder such as a memory arrangement can send the following response message:

• Status: success, range 0x40000000-0x40007FFF, RRG:11 , last response.

• A requested range of virtual addresses: 0x40000000 + length 0x8000

• A range Request Group (RRG): 11

• A relaxed ordering allowed: not allowed

• A maximum number of returned responses allowed: 3

• Read, write, no-read, no-write, execute, no-execute flags: write, no-read, no execute. In this respect, the requesting entity requests a memory range 0x40000000-0x40008000 for write-only with no more than 3 replies, the replies are within the range request group, 11.

After receiving the above request message, a responder such as a memory arrangement can send the following multiple response messages:

1 contiguous blocks + 1 untranslated + 1 contiguous blocks

• Status: success, range 0x40001000-0x40002FFF, RRG:11 , non-last response. Note that this is a untranslated address (i.e. virtual address)

• Status: success, range 0x40003000-0x40004FFF, RRG:11 , last response. Note that this is a untranslated address (i.e. virtual address)

For the requested range 0x40005000-0x40008000, responses are not sent as the maximum number of allowed responses is 3. According to a further embodiment, a request message sent from a requesting entity such as an endpoint may comprise the following:

• A requested range of virtual addresses: 0x40000000 + length 0x8000

• A Range Request Group (RRG): 11

• A relaxed ordering allowed: allowed

• A maximum number of returned responses allowed: 3

In this respect, the requesting entity requests a memory range 0x40000000-0x40008000 for write-only with no more than 3 replies for the Range Request Group, 11. After receiving the above request message, a responder such as a memory arrangement can send the following multiple response messages which are unordered:

1 contiguous blocks + 1 untranslated + 1 contiguous blocks

• Status: success, range 0x40000000-0x40000FFF, RRG:11 , non-last response (response serial number: 0x2)

• Status: success, range 0x40001000-0x40002FFF, RRG:11 , non-last response (response serial number: 0x1) • Status: success, range 0x40003000-0x40004FFF, RRG:11 , last response (response serial number: 0x3)

For the requested range 0x40005000-0x40008000, responses are not sent as the maximum number of responses allowed is 3. According to a further embodiment, a request message sent from a requesting entity such as an endpoint may comprise the following:

• A requested range of virtual addresses: 0x40000000 + length 0x8000

• A Range Request Group (RRG): 11

• A relaxed ordering allowed: not allowed

• A maximum number of returned responses allowed: 3

• Read, write, no-read, no-write, execute, no-execute flags: write, no-read, no execute

In this respect, the requesting entity requests a memory range 0x40000000-0x40008000 for write-only with no more than 3 replies in a Range Request Group (RRG), 11. After receiving the above request message, a responder such as a memory arrangement can send the following multiple response messages:

1 contiguous blocks + 1 untranslated + 1 contiguous blocks

• Status: success, range 0x40000000-0x40000FFF, RRG:11 , non-last response.

• Status: success, range 0x40001000-0x40002FFF, RRG:11 , non-last response. · Status: retry-later, time-to-retry later: 100 nano-sec, range 0x40003000-

0x40004FFF, RRG:11 , last response.

According to an embodiment, another possible way to implement a Range Request Interface request is re-using the existing Page Request Interface request message and delivering additional parameters in a separate channel. As some of the fields in Range Request Interface (RRI) already exist in Page Request Interface (PRI), the device will be using existing fields in PRI message for RRI, and in addition the rest of the fields as mentioned above will be either passed in additional fields or a separate channel or queue or method. The responder receiving the PRI message will read the additional fields from the additional fields or the separate channel/queue/method, and will treat this message as an RRI request rather than a PRI request. According to a further embodiment, another possible way to implement a Range Request Interface (RRI) response is re-using the existing Page Request Interface (PRI) response and delivering additional parameters in a separate channel. As some of the fields in RRI already exists in PRI, the central processing unit will be using existing fields in a PRI message for RRI, and in addition the rest of the fields as mentioned above will be passed either as additional fields or in a separate channel or queue or method. The device receiving the PRI message will read the additional fields from a separate channel or queue or method and will treat this message as RRI response rather than PRI response.

While a particular feature or aspect of the disclosure may have been disclosed with respect to only one of several implementations or embodiments, such feature or aspect may be combined with one or more other features or aspects of the other implementations or embodiments as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include", "have", "with", or other variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprise". Also, the terms "exemplary", "for example" and "e.g." are merely meant as an example, rather than the best or optimal. The terms “coupled” and “connected”, along with derivatives may have been used. It should be understood that these terms may have been used to indicate that two elements cooperate or interact with each other regardless whether they are in direct physical or electrical contact, or they are not in direct contact with each other.

Although specific aspects have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific aspects shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific aspects discussed herein.

Although the elements in the following claims are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.

Many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the above teachings. Of course, those skilled in the art readily recognize that there are numerous applications of the invention beyond those described herein. While the present invention has been described with reference to one or more particular embodiments, those skilled in the art recognize that many changes may be made thereto without departing from the scope of the present invention. It is therefore to be understood that within the scope of the appended claims and their equivalents, the invention may be practiced otherwise than as specifically described herein.

Claims

1. A memory arrangement (601), comprising: a memory (603) being arranged to comprise physical memory units; an interface (607) being configured to receive a request message for requesting access to a range of virtual addresses from a requesting entity (631), the range of virtual addresses being associated with at least two virtual memory units; a memory controller (605) being configured to allocate a plurality of physical memory units in the memory to a subrange of the range of virtual addresses and to map physical addresses of the plurality of physical memory units with the subrange of the range of virtual addresses, a memory address translator (609) being configured to generate address information indicating the subrange of the range of virtual addresses to which the physical addresses are mapped, wherein the interface (607) is configured to send a response message towards the requesting entity (631), the response message comprising the address information.

2. The memory arrangement (601) of claim 1 , wherein the memory controller (605) is configured to determine whether the plurality of physical memory units is available in the memory (603) prior to allocating the plurality of physical memory to the subrange of the range of virtual addresses, and wherein the memory address translator (609) is configured to generate an indication indicating that the request cannot be granted if the memory controller (605) has determined that the plurality of physical memory units is not available, and wherein the interface (607) is configured to send a rejection message towards the requesting entity (631), the rejection message comprising the indication.

3. The memory arrangement (601) of claim 1 or 2, wherein: the memory controller (605) is configured to allocate a further plurality of physical memory units in the memory (603) to a further subrange of the range of virtual addresses and to map physical addresses of the further plurality of physical memory units with the further subrange of the range of virtual addresses, the memory address translator (609) is configured to generate further address information indicating the further subrange of the range of virtual addresses to which the physical addresses are mapped, and the interface (607) is configured to send a further response message towards the requesting entity (631), the further response message comprising the further address information.

4. The memory arrangement (601) of claim 3, wherein the memory controller (605) is configured to determine whether the further plurality of physical memory units is available in the memory (603) prior to allocating the further plurality of physical memory to the further subrange of the range of virtual addresses, and wherein the memory address translator (609) is configured to generate a further indication indicating whether requesting access to the further subrange of the range of virtual addresses can be granted or not, depending on that the memory controller (605) has determined whether the further plurality of physical memory units is available or not, and wherein the interface (607) is configured to send the further response message towards the requesting entity (631), the further response message comprising the further address information and the further indication.

5. The memory arrangement (601) of any one of the preceding claims, the request message comprising an identifier identifying the request message, wherein the memory address translator (609) is configured to include into the response message: the identifier, and/or a responder identifier identifying the memory address translator (609) and/or a requester identifier identifying the requesting entity (631).

6. The memory arrangement (601) of any one of the preceding claims 2 to 5, wherein, if the memory controller (605) has determined that the plurality of physical memory units is not available, the memory address translator (609) is configured to generate a status indication indicating one of the following statuses: requesting access to the range of virtual addresses is failed; requesting access to the range of virtual addresses is invalid; requesting access to the range of virtual addresses can be re-sent, and wherein the interface (607) is configured to send the rejection message towards the requesting entity (631), the rejection message comprising the status indication.

7. The memory arrangement (601) of claim 6, wherein, if the status indication indicates the requesting access to the range of virtual addresses can be resent, the memory address translator (609) is configured to generate a retry-time indication indicating a period of time for resending the request message, wherein the retry-time indication is configured to allow the requesting entity (631) to resend the request message for requesting access to the range of virtual addresses after the period of time once the requesting entity has received the rejection message.

8. The memory arrangement (601) of any one of the preceding claims 4 to 7, wherein, if the memory controller (605) has determined that the further plurality of physical memory units is not available in the memory (603), the memory address translator (609) is configured to generate a further status indication indicating one of the following statuses: requesting access to the further subrange of the range of virtual addresses is failed; requesting access to the further subrange of the range of virtual addresses is invalid; requesting access to the further subrange of the range of virtual addresses can be sent, and wherein the interface (607) is configured to send the further response message towards the requesting entity (631), the further response message comprising the further status indication.

9. The memory arrangement (601) of claim 8, wherein, if the further status indication indicates requesting access to the further subrange of the range of virtual addresses can be sent, the memory address translator (609) is configured to generate a retry-time indication indicating a further period of time for sending a further request message, wherein the retry-time indication is configured to allow the requesting entity (631) to send the further request message for requesting access to the further subrange of the range of virtual addresses after the further period of time once the requesting entity has received the further response message.

10. The memory arrangement (601) of any one of the preceding claims, the request message comprising a threshold indication indicating a maximum number of response messages which are allowed to be sent towards the requesting entity (631), wherein the memory controller (605) is further configured to allocate each of a set of pluralities of physical memory units in the memory (603) to a respective one of a set of subranges of the range of virtual addresses, and map each of the set of pluralities of physical memory units with the respective subrange of the range of virtual addresses from the set of subranges of the range of virtual addresses, wherein the memory address translator (609) is configured to: generate a set of address information on the basis of the set of subranges of the range of virtual addresses, each of the set of address information indicating a respective subrange of the range of virtual addresses from the set of subranges of the range of virtual addresses; include each of the set of address information into a respective response message of a set of response messages for responding to requesting access to the set of subranges of the range of virtual addresses respectively; wherein, if the number of the set of response messages is equal to or smaller than the maximum number, the interface (607) is configured to send the set of response messages towards the requesting entity (631), and if the number of the set of response messages is larger than the maximum number, the interface (607) is configured to send a subset of the set of response messages towards the requesting entity (631), the number of the subset of the set of response messages being equal to the maximum number.

11. The memory arrangement (601) of claim 10, wherein the memory address translator (609) is configured to generate a response indication to indicate whether a response message of the set of response messages is the last response message to be sent to the requesting entity (631), wherein the memory address translator (609) is further configured to include the response indication into the response messages of the set of response messages that is the last response message to be sent to the requesting entity (631).

12. The memory arrangement (601) of any one of the preceding claims, the request message comprising an indication indicating a relaxed-sending order, wherein the memory controller (605) is further configured to: - allocate each of a set of pluralities of physical memory units in the memory (603) to a respective one of a set of subranges of the range of virtual addresses and map each of the set of pluralities of physical memory units with the respective subrange of the range of virtual addresses from the set of subranges of the range of virtual addresses in succession; wherein the memory address translator (609) is configured to: generate a set of address information on the basis of the set of subranges of the range of virtual addresses, each of the set of address information indicating a respective subrange of the range of virtual addresses to which the respective plurality of physical memory units from the set of pluralities of physical memory units is mapped and include each address information of the set of address information into a respective response message of a set of response messages; generate a set of serial numbers on the basis of the set of subranges of the range of virtual addresses to each of which respective address information of the set of address information are mapped; - assign each of the set of serial numbers to a respective response message of the set of response messages for responding to requesting access to the set of subranges of the range of virtual addresses, according to an order of time points at each of which the respective one of the set of pluralities of physical memory units is allocated by the memory controller (605), wherein the interface (607) is configured to send the set of response messages according to the order of the set of serial numbers.

13. The memory arrangement (601) of any one of the preceding claims, wherein the memory address translator (609) is integrated within the memory controller (605) or being an independent device interconnected with the memory controller (605) via another interface.

14. A requesting entity (631) for requesting access to a range of virtual addresses, wherein the requesting entity (631) is configured to: send a request message for requesting access to the range of virtual addresses, the range of virtual addresses being associated with at least two virtual memory units; receive a response message comprising address information indicating a subrange of the range of virtual addresses which the requesting entity (631) is allowed to access.

15. The requesting entity (631) of claim 14, wherein the requesting entity (631) is configured to receive a further response message comprising further address information indicating a further subrange of the range of virtual addresses which the requesting entity (631) is allowed to access.

16. The requesting entity (631) of claim 14 or 15, wherein the requesting entity (631) is configured to define the range of virtual addresses as a range from a starting virtual address plus a length of virtual memory units or as a range between a starting virtual address and an ending virtual address.

17. The requesting entity (631) of any one of claims 14 to 16, the requesting entity (631) is further configured to include a threshold indication into the request message, the threshold indication indicating a maximum number of response messages for responding to the request message which are allowed to be sent towards the requesting entity (631).

18. The requesting entity (631) of any one of claims 14 to 17, wherein the requesting entity (631) is configured to include one or more of the following into the request message: a requester identifier identifying the requesting entity (631), a responder identifier identifying a responding entity responding to the request message, a identifier identifying the request message, and a flag comprising at least one access permission requested by the requesting entity (631) associated with the range of virtual memory addresses, in particular, write, read, execute, no-read, no-write, or no execute.

19. The requesting entity (631) of any one of claims 14 to 18, wherein the requesting entity (631) is configured to receive a rejection message indicating that requesting access to the range of virtual addresses cannot be granted and a retry-time indication indicating a period of time for resending the request message, wherein the requesting entity (631) is configured to resend the request message after the period of time, after the requesting entity (631) has received the rejection message.

20. The requesting entity (631) of any one of claims 14 to 19, wherein the requesting entity (631) is configured to receive a second further response message indicating that requesting access to a second further subrange of the range of virtual addresses cannot be granted and a further retry-time indication indicating a further period of time for sending a further request message for requesting access to the second further subrange of the range of virtual addresses, wherein the requesting entity (631) is configured to send the further request message after the further period of time, after the requesting entity has received the second further response message.

21. The requesting entity (631) of any one of claims 14 to 20, wherein the requesting entity (631) is configured to include an indication indicating a relaxed-sending order into the request message and to allow the responding entity to send a response message earlier than a further response message towards the requesting entity, the response message indicating a subrange of the range of virtual addresses the requesting entity (631) is allowed to access and the further response message indicating a further subrange of the range of virtual addresses the requesting is allowed to access, wherein the subrange of the range of virtual addresses is made to accessible to the requesting entity earlier than the further subrange of the range of virtual addresses.