CN116032256B - Triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signal - Google Patents
Triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signal Download PDFInfo
- Publication number
- CN116032256B CN116032256B CN202310031725.6A CN202310031725A CN116032256B CN 116032256 B CN116032256 B CN 116032256B CN 202310031725 A CN202310031725 A CN 202310031725A CN 116032256 B CN116032256 B CN 116032256B
- Authority
- CN
- China
- Prior art keywords
- clk
- triangular wave
- wave generating
- generating circuit
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses a triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signals, which relates to the technical field of triangular wave generating circuits, wherein one end of a current source I1 is connected with VDD, the other end of the current source I1 is connected with a grid and a drain of NM1 and a grid of NM6, and a source of NM1 is grounded; one end of R1 is connected with VDD, the other end of R1 is connected with one ends of R2, R5 and R6, the other end of R2 is connected with R3, the other end of R3 is connected with R4, the other end of R4 is grounded, the other end of R5 is connected with one end of output Vout-and CAP3, and the other end of CAP3 is connected with one end of PM1, one end of NM2, one end of R9, one end of R7 and one end of CAP 5. The patent provides a triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signals, and ensures that the direct current offset of the positive and negative ends of an output signal of a triangular wave is smaller.
Description
Technical Field
The invention relates to the technical field of triangular wave generating circuits, in particular to a triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signals.
Background
In the high-speed interface design, in order to realize high-speed data rate transmission, a data clock recovery circuit is required to work under a high-frequency condition, and the difficulty is that the phase interpolator needs to keep good linearity under the high-frequency condition. The triangular wave generating circuit realizes low-pass filtering through the output high-resistance and the capacitor, filters high-frequency components, filters signals into triangular waves, and can ensure that the phase interpolator has better linearity under high frequency, but direct current deviation exists between the positive terminal and the negative terminal of the differential signal due to incomplete matching of devices and incomplete consistency of layout wiring in the signal transmission process.
The triangular wave generating circuit has great amplification capability on the input DC deviation due to great DC gain, so that the DC deviation of the output signal is larger. Such signals are fed to a phase interpolator that fails to meet the linearity requirements of the data clock recovery circuit at high frequencies.
Disclosure of Invention
Aiming at the defects existing in the prior art, the invention aims to provide a triangular wave generating circuit for eliminating direct current offset of positive and negative ends of a differential signal.
In order to achieve the above purpose, the present invention provides the following technical solutions: a triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signals comprises a PMOS tube, an NMOS tube, a capacitor, a resistor, a current source I1, an operational amplifier AMP, VIN+ and VIN-;
the PMOS tube comprises PM1 and PM2;
the NMOS tube comprises NM1, NM2, NM3, NM4, NM5 and NM6;
the capacitor comprises CAP1, CAP2, CAP3, CAP4, CAP5 and CAP6;
the resistor comprises R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12 and R13;
one end of the current source I1 is connected with VDD, the other end of the current source I1 is connected with a grid and a drain of NM1 and a grid of NM6, and the source of NM1 is grounded;
one end of R1 is connected with VDD, the other end of R1 is connected with one ends of R2, R5 and R6, the other end of R2 is connected with R3, the other end of R3 is connected with R4, the other end of R4 is grounded, the other end of R5 is connected with one ends of output Vout-and CAP3, and the other end of CAP3 is connected with one end of PM1 drain, NM2 drain, one end of R9, one end of R7 and one end of CAP 5;
the other end of the CAP5 is connected with the drain end of the NM4, the grid of the NM4 is connected with the control signal CFG_CAP, and the drain of the NM4 is grounded;
the other end of R6 is connected with one end of output Vout+ and CAP4, the other end of CAP4 is connected with the drain of PM2, the drain of NM3, one end of R10, one end of R8 and one end of CAP6;
the other end of the CAP6 is connected with the drain end of the NM5, the grid of the NM5 is connected with the control signal CFG_CAP, and the drain of the NM5 is grounded;
the other end of the R9 is connected with the other end of the R10 and is connected with the input positive end of the operational amplifier AMP;
the VIN+ is the positive input end of the signal, and the output end of the VIN+ is electrically connected with the input end of the CAP 1; the output end of the CAP1 is connected with a grid of NM2 and a resistor R7;
the VIN-is the input negative terminal of the signal, the output terminal of the VIN-is electrically connected with the input terminal of the CAP2, and the output terminal of the CAP2 is connected with the grid of the NM3 and the input terminal of the resistor R8;
the sources of NM2 and NM3 and the drain of NM6 are connected together, and the source of NM6 is grounded;
the sources of PM1 and PM2 are connected with VDD, the gates of PM1 and PM2 are connected with the output of an operational amplifier AMP, one end of a resistor R11 is connected with a power supply, and the other end of the resistor R11 is connected with one end of a resistor R12 and the input negative end of the operational amplifier AMP;
the other end of the R12 is connected with R13, and the other end of the R13 is grounded.
Further, the method for accessing the triangular wave generating circuit comprises the following steps:
step one: preparing a 0 ° phase triangular wave generating circuit, a 180 ° phase triangular wave generating circuit, a 90 ° phase triangular wave generating circuit, and a 270 ° phase triangular wave generating circuit;
step two: clk_00 and clk_180 are input to the 0 °/180 ° phase triangular wave generating circuit in the form of differential signals, and then clk_twg_00 and clk_twg_180 are output;
wherein clk_00 is a signal of 0 ° phase, clk_180 is a signal of 180 ° phase, clk_twg_00 is an output signal of the signal of 0 ° phase after passing through the triangular wave generating circuit, clk_twg_180 is an output signal of the signal of 180 ° phase after passing through the triangular wave generating circuit;
step three: clk_90 and clk_270 are input to the 90 °/270 ° phase triangular wave generating circuit in the form of differential signals, and then clk_twg_90 and clk_twg_270 are output;
wherein clk_90 is a 90 ° phase signal, clk_270 is a 270 ° phase signal, clk_twg_90 is an output signal of the 90 ° phase signal after passing through the triangular wave generating circuit, and clk_twg_270 is an output signal of the 270 ° phase signal after passing through the triangular wave generating circuit;
step four: clk_twg_00, clk_twg_180, clk_twg_90, clk_twg_270 are input to the subject phase interpolation circuit, and finally clk_out_p and clk_out_n are output.
Compared with the prior art, the invention has the following beneficial effects:
the patent provides a triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signals, and ensures that the direct current offset of the positive and negative ends of an output signal of a triangular wave is smaller. The linearity of the phase interpolator is good, and the data clock recovery circuit works normally at high frequency;
and the triangular wave production circuit in the patent can be connected to the front stage of the phase interpolator, and low-pass filtering is realized by outputting high resistance and capacitance to filter high-frequency components and filter signals into triangular waves. Meanwhile, the direct current offset between the positive terminal and the negative terminal of the differential signal can be eliminated, and the phase interpolator is guaranteed to have good linearity under high frequency;
on the other hand, the circuit in this patent is simple in construction, reduce complexity of the system and chip area as much as possible.
Drawings
FIG. 1 is a circuit diagram of a triangular wave generating circuit for eliminating DC offset at positive and negative ends of differential signals;
FIG. 2 is a system block diagram of an access method of a triangular wave generating circuit in the present invention;
FIG. 3 is a schematic diagram of simulation results (-0.36 LSB to 0.46 LSB) after differentiating the linear error by the 20GHz phase interpolator in the invention.
Detailed Description
Referring to fig. 1, a triangle wave generating circuit for eliminating direct current offset of positive and negative ends of differential signals comprises a PMOS tube, an NMOS tube, a capacitor, a resistor, a current source I1, an operational amplifier AMP, vin+ and VIN-;
the PMOS tube comprises PM1 and PM2;
the NMOS tube comprises NM1, NM2, NM3, NM4, NM5 and NM6;
the capacitor comprises CAP1, CAP2, CAP3, CAP4, CAP5 and CAP6;
the resistor comprises R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12 and R13;
one end of the current source I1 is connected with VDD, the other end of the current source I1 is connected with a grid and a drain of NM1 and a grid of NM6, and the source of NM1 is grounded;
one end of R1 is connected with VDD, the other end of R1 is connected with one ends of R2, R5 and R6, the other end of R2 is connected with R3, the other end of R3 is connected with R4, the other end of R4 is grounded, the other end of R5 is connected with one ends of output Vout-and CAP3, and the other end of CAP3 is connected with one end of PM1 drain, NM2 drain, one end of R9, one end of R7 and one end of CAP 5;
the other end of the CAP5 is connected with the drain end of the NM4, the grid of the NM4 is connected with the control signal CFG_CAP, and the drain of the NM4 is grounded;
the other end of R6 is connected with one end of output Vout+ and CAP4, the other end of CAP4 is connected with the drain of PM2, the drain of NM3, one end of R10, one end of R8 and one end of CAP6;
the other end of the CAP6 is connected with the drain end of the NM5, the grid of the NM5 is connected with the control signal CFG_CAP, and the drain of the NM5 is grounded;
the other end of the R9 is connected with the other end of the R10 and is connected with the input positive end of the operational amplifier AMP;
the VIN+ is the positive input end of the signal, and the output end of the VIN+ is electrically connected with the input end of the CAP 1; the output end of the CAP1 is connected with a grid of NM2 and a resistor R7;
the VIN-is the input negative terminal of the signal, the output terminal of the VIN-is electrically connected with the input terminal of the CAP2, and the output terminal of the CAP2 is connected with the grid of the NM3 and the input terminal of the resistor R8;
the sources of NM2 and NM3 and the drain of NM6 are connected together, and the source of NM6 is grounded;
the sources of PM1 and PM2 are connected with VDD, the gates of PM1 and PM2 are connected with the output of an operational amplifier AMP, one end of a resistor R11 is connected with a power supply, and the other end of the resistor R11 is connected with one end of a resistor R12 and the input negative end of the operational amplifier AMP;
the other end of the R12 is connected with R13, and the other end of the R13 is grounded.
Referring to fig. 2, the method for switching in the triangular wave generating circuit includes the steps of:
step one: preparing a 0 ° phase triangular wave generating circuit, a 180 ° phase triangular wave generating circuit, a 90 ° phase triangular wave generating circuit, and a 270 ° phase triangular wave generating circuit;
step two: clk_00 and clk_180 are input to the 0 °/180 ° phase triangular wave generating circuit in the form of differential signals, and then clk_twg_00 and clk_twg_180 are output;
wherein clk_00 is a signal of 0 ° phase, clk_180 is a signal of 180 ° phase, clk_twg_00 is an output signal of the signal of 0 ° phase after passing through the triangular wave generating circuit, clk_twg_180 is an output signal of the signal of 180 ° phase after passing through the triangular wave generating circuit;
step three: clk_90 and clk_270 are input to the 90 °/270 ° phase triangular wave generating circuit in the form of differential signals, and then clk_twg_90 and clk_twg_270 are output;
wherein clk_90 is a 90 ° phase signal, clk_270 is a 270 ° phase signal, clk_twg_90 is an output signal of the 90 ° phase signal after passing through the triangular wave generating circuit, and clk_twg_270 is an output signal of the 270 ° phase signal after passing through the triangular wave generating circuit;
step four: clk_twg_00, clk_twg_180, clk_twg_90, clk_twg_270 are input to the subject phase interpolation circuit, and finally clk_out_p and clk_out_n are output.
The triangular wave generating circuit is connected to the front stage of the phase interpolator, and low-pass filtering is realized by outputting high resistance and capacitance to filter out high frequency components and filter the signals into triangular waves. Meanwhile, the direct current offset between the positive terminal and the negative terminal of the differential signal can be eliminated, and the phase interpolator is guaranteed to have good linearity under high frequency;
VIN+ and VIN-are triangular wave input signals, and through alternating current coupling, the direct current component of the input signals is eliminated, so that the direct current deviation of the input signals is eliminated;
the positive end of the operational amplifier output signal is connected with the input negative end through a resistor R8, and the negative end of the operational amplifier output signal is connected with the input positive end through a resistor R7, so that negative feedback is formed, direct current deviation of the positive end and the negative end of the output signal caused by mismatching of the input NMOS tubes NM2 and NM3 and the output PMOS tubes PM1 and PM2 of the operational amplifier can be effectively restrained, and the same direct current components of the positive end and the negative end of the output signal are ensured;
the main body operational amplifier circuit is provided with common mode feedback, so that the output common mode voltage of the circuit is ensured to be 2/3 of VDD, the working state of the circuit is correct, and the operational amplifier has higher gain;
the NMOS transistors NM4 and NM5 are controlled by a control signal CFG_CAP, and the capacitors CAP5 and CAP6 can be connected with or disconnected from the output, so that the rising and falling time of the output signal can be regulated, and the triangular wave generating circuit is adapted to different working frequencies;
the output signal is in AC coupling to ensure that the DC component of the output signal is eliminated, meanwhile, the DC component of the signal is obtained by resistor voltage division, and the DC components of the positive terminal and the negative terminal of the signal are connected together through resistors, so that the same DC components of the positive terminal and the negative terminal of the signal are ensured, and the DC deviation of the output signal is eliminated;
the direct current component of the output signal is obtained by resistor voltage division, so that the output common-mode voltage can be freely regulated according to the requirement of the phase interpolator on the input common-mode voltage;
the phase interpolator for simulation uniformly divides the phase variation of 0 to 360 into 64 areas, the simulation frequency is 20GHz, one period is 50ps, and one LSB is about 781.25fs.
Referring to FIG. 3, simulation results (-0.36 LSB to 0.46 LSB) after differentiating the linear error by the 20GHz phase interpolator;
where M1 is the maximum value of the delay time of PI adjacent two control words and M2 is the minimum value of the delay time of PI adjacent two control words. The delay time is desirably about 781.25fs at 20 GHz. Simulation results are-0.36 LSB to 0.46LSB after differential linear errors of the 20GHz phase interpolator are calculated.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to those skilled in the art without departing from the principles of the present invention are intended to be considered as protecting the scope of the present template.
Claims (2)
1. The triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signals is characterized by comprising a PMOS tube, an NMOS tube, a capacitor, a resistor, a current source I1, an operational amplifier AMP, VIN+ and VIN-;
the PMOS tube comprises PM1 and PM2;
the NMOS tube comprises NM1, NM2, NM3, NM4, NM5 and NM6;
the capacitor comprises CAP1, CAP2, CAP3, CAP4, CAP5 and CAP6;
the resistor comprises R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12 and R13;
one end of the current source I1 is connected with VDD, the other end of the current source I1 is connected with a grid electrode and a drain electrode of NM1 and a grid electrode of NM6, and the source electrode of NM1 is grounded;
one end of R1 is connected with VDD, the other end of R1 is connected with one ends of R2, R5 and R6, the other end of R2 is connected with R3, the other end of R3 is connected with R4, the other end of R4 is grounded, the other end of R5 is connected with one ends of output Vout-and CAP3, and the other end of CAP3 is connected with one end of PM1 drain, NM2 drain, one end of R9, one end of R7 and one end of CAP 5;
the other end of the CAP5 is connected with the drain end of the NM4, the grid electrode of the NM4 is connected with the control signal CFG_CAP, and the source electrode of the NM4 is grounded;
the other end of R6 is connected with one end of the output Vout+ and the CAP4, and the other end of the CAP4 is connected with the drain electrode of PM2, the drain electrode of NM3, one end of R10, one end of R8 and one end of CAP6;
the other end of the CAP6 is connected with the drain electrode of the NM5, the grid electrode of the NM5 is connected with the control signal CFG_CAP, and the source electrode of the NM5 is grounded;
the other end of the R9 is connected with the other end of the R10 and is connected with the input positive end of the operational amplifier AMP;
the VIN+ is the positive input end of the signal, and the output end of the VIN+ is electrically connected with the input end of the CAP 1; the output end of the CAP1 is connected with a grid electrode of NM2 and a resistor R7;
the VIN-is the input negative terminal of the signal, the output terminal of the VIN-is electrically connected with the input terminal of the CAP2, and the output terminal of the CAP2 is connected with the grid electrode of the NM3 and the input terminal of the resistor R8;
the sources of the NM2 and the NM3 are connected with the drain electrode of the NM6, and the source electrode of the NM6 is grounded;
the sources of PM1 and PM2 are connected with VDD, the gates of PM1 and PM2 are connected with the output of an operational amplifier AMP, one end of a resistor R11 is connected with a power supply, and the other end of the resistor R11 is connected with one end of a resistor R12 and the input negative end of the operational amplifier AMP;
the other end of the R12 is connected with R13, and the other end of the R13 is grounded.
2. The triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signals according to claim 1, wherein the method for connecting the triangular wave generating circuit comprises the following steps:
step one: preparing a 0 ° phase triangular wave generating circuit, a 180 ° phase triangular wave generating circuit, a 90 ° phase triangular wave generating circuit, and a 270 ° phase triangular wave generating circuit;
step two: clk_00 and clk_180 are input to the 0 °/180 ° phase triangular wave generating circuit in the form of differential signals, and then clk_twg_00 and clk_twg_180 are output;
step three: clk_90 and clk_270 are input to the 90 °/270 ° phase triangular wave generating circuit in the form of differential signals, and then clk_twg_90 and clk_twg_270 are output;
step four: clk_twg_00, clk_twg_180, clk_twg_90, clk_twg_270 are input to the subject phase interpolation circuit, and finally clk_out_p and clk_out_n are output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310031725.6A CN116032256B (en) | 2023-01-10 | 2023-01-10 | Triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310031725.6A CN116032256B (en) | 2023-01-10 | 2023-01-10 | Triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signal |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116032256A CN116032256A (en) | 2023-04-28 |
| CN116032256B true CN116032256B (en) | 2023-09-26 |
Family
ID=86070335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310031725.6A Active CN116032256B (en) | 2023-01-10 | 2023-01-10 | Triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signal |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116032256B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956306A (en) * | 2005-10-25 | 2007-05-02 | 富士通株式会社 | DC-DC converter and dc-dc converter control method |
| CN101364796A (en) * | 2007-08-07 | 2009-02-11 | 曹志明 | DC drift eliminator applied to variable gain amplifier |
| CN102130867A (en) * | 2010-12-29 | 2011-07-20 | 电子科技大学 | DC offset cancellation circuit |
| CN102361446A (en) * | 2011-10-27 | 2012-02-22 | 上海贝岭股份有限公司 | Triangular wave oscillating circuit |
| CN107276548A (en) * | 2016-04-07 | 2017-10-20 | 江西云晖生物芯片技术有限公司 | A kind of NEXT series of products CMOS automatic gain control circuits |
| CN115208194A (en) * | 2022-06-07 | 2022-10-18 | 中国电子科技集团公司第二十四研究所 | Sectional type slope compensation circuit for voltage reduction type DCDC |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4684112B2 (en) * | 2006-01-31 | 2011-05-18 | 富士通テン株式会社 | Triangular wave generation circuit |
-
2023
- 2023-01-10 CN CN202310031725.6A patent/CN116032256B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1956306A (en) * | 2005-10-25 | 2007-05-02 | 富士通株式会社 | DC-DC converter and dc-dc converter control method |
| CN101364796A (en) * | 2007-08-07 | 2009-02-11 | 曹志明 | DC drift eliminator applied to variable gain amplifier |
| CN102130867A (en) * | 2010-12-29 | 2011-07-20 | 电子科技大学 | DC offset cancellation circuit |
| CN102361446A (en) * | 2011-10-27 | 2012-02-22 | 上海贝岭股份有限公司 | Triangular wave oscillating circuit |
| CN107276548A (en) * | 2016-04-07 | 2017-10-20 | 江西云晖生物芯片技术有限公司 | A kind of NEXT series of products CMOS automatic gain control circuits |
| CN115208194A (en) * | 2022-06-07 | 2022-10-18 | 中国电子科技集团公司第二十四研究所 | Sectional type slope compensation circuit for voltage reduction type DCDC |
Non-Patent Citations (1)
| Title |
|---|
| 基于DSP的电力谐波装置研究;薛太林等;《现代电子技术》;第38卷(第23期);第41-46页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116032256A (en) | 2023-04-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104601127A (en) | Operational amplifier circuit and reference voltage generating circuit module | |
| CN116032256B (en) | Triangular wave generating circuit for eliminating direct current offset of positive and negative ends of differential signal | |
| Kilinc et al. | Realization of fully controllable negative inductance with single operational transresistance amplifier | |
| CN108259007B (en) | Enhancement circuit applied to operational amplifier conversion rate | |
| Yüce et al. | Grounded capacitor-based new floating inductor simulators and a stability test | |
| CN215452775U (en) | Wide-swing self-adaptive slope generation circuit | |
| Chen et al. | Tunable current-mode and voltage-mode quadrature oscillator using a DVCCTA | |
| Arslan et al. | On the realization of high performance current conveyors and their applications | |
| CN107710621A (en) | Signal circuit | |
| Ahn et al. | Current-mode continuous-time filters using complementary current mirror pairs | |
| Nandi et al. | Single-CFA first-order allpass filter | |
| CN202652188U (en) | Frequency hopping frequency synthesizer | |
| Salama et al. | Parasitic-capacitance-insensitive voltage-mode MOSFET-C filters using differential current voltage conveyor | |
| Khan et al. | DVCC-based electronically tunable firstorder current-mode filters | |
| Chen | Electronically tunable quadrature oscillator using grounded components with current and voltage outputs | |
| JP5078393B2 (en) | Calibration loop, filter circuit and related method capable of automatically calibrating center frequency of filter | |
| EP3048738A1 (en) | Wireless receiver with high linearity | |
| CN112865495A (en) | Slope generation circuit and control method | |
| CN110166384B (en) | Differential signal transmission circuit and communication device | |
| CN107612542B (en) | Regenerative frequency dividing circuit and high-frequency signal frequency dividing method | |
| US7285998B2 (en) | Duty ratio adjusting circuit | |
| Minayi et al. | CIM a current inverting metamutator and its application to universal filters among others | |
| JPS6378612A (en) | Level shifting circuit | |
| CN216956131U (en) | Oscilloscope analog front-end circuit suitable for high-low bandwidth | |
| DE102014118284A1 (en) | quantizer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |