CN116031265B

CN116031265B - Photodetector integrated with solar cell and CMOS circuit and manufacturing method

Info

Publication number: CN116031265B
Application number: CN202211661699.7A
Authority: CN
Inventors: 杨荣; 余明斌
Original assignee: Shanghai Mingkun Semiconductor Co ltd
Current assignee: Shanghai Mingkun Semiconductor Co ltd
Priority date: 2022-12-23
Filing date: 2022-12-23
Publication date: 2023-09-15
Anticipated expiration: 2042-12-23
Also published as: CN116031265A

Abstract

The invention discloses a photoelectric detector integrating a solar cell and a CMOS circuit and a manufacturing method thereof, wherein the photoelectric detector comprises a silicon substrate and an oxide layer from bottom to top; wherein the silicon substrate and the oxide layer comprise a CMOS integrated circuit region, a detector region, and a silicon solar cell region. The invention embeds selective silicon and germanium epitaxy to manufacture silicon and germanium detector by modifying mature CMOS process flow of shallow trench isolation on silicon substrate, and utilizes CMOS source-drain region doping to serve as electrode contact region doping of crystalline silicon solar cell, and connects electrode through metal connection wire. The silicon solar cell provides power for the detector and the CMOS circuit, the detector converts the absorbed optical signals into electrical signals, amplifies and processes the signals through the CMOS circuit, achieves a complete light receiver function, and works independently of an external power supply. The invention solves the problems of high manufacturing difficulty and high cost of the current photoelectric detector integrated with the solar cell and/or the CMOS circuit.

Description

Photodetector integrated with solar cell and CMOS circuit and manufacturing method

Technical Field

The invention relates to the technical field of semiconductors, in particular to a photoelectric detector integrating a solar cell and a CMOS circuit and a manufacturing method thereof.

Background

The semiconductor photoelectric detector is used for absorbing optical signals and converting the optical signals into electric signals for output and has very wide application. The detector typically requires a power supply to provide a negative bias operating state while converting the photocurrent through a transimpedance amplifier to an amplified voltage signal for further processing by a signal readout circuit. The photoelectric detector used in the space, the field and other scenes often lacks a long-term stable power supply or requires high cost for the power supply, which is one of the problems puzzling the use of the detector; on the other hand, if the transimpedance amplifier and the CMOS readout circuit can be integrated on the same substrate as the detector, this would be a significant benefit in improving performance, reducing chip area, and reducing cost.

The invention CN104319316A proposes that a high-efficiency Bao Mojing silicon solar cell is manufactured on a silicon-on-insulator (SOI) substrate, and the structure and the process of the high-efficiency Bao Mojing silicon solar cell are compatible with a silicon CMOS integrated circuit, but the high-efficiency Bao Mojing silicon solar cell is difficult to be compatible in a CMOS process such as a screen printing device, a TCO transparent conductive film and a silver electrode on which the solar cell depends, and a hydrogenated amorphous silicon film is also difficult to bear the temperature of 400 ℃ typical to the CMOS metallization process; moreover, if the detector is made of silicon material, only near infrared (NIR, 0.75-1.1 microns) and visible light wavelengths (0.4-0.76 microns) can be absorbed, and short wave infrared (SWIR, 1.1-2.5 microns) cannot be responded. The inability of SWIR to be applied to important fields such as optical communication, quantum key distribution, TOF ranging, gas monitoring, non-destructive testing, medical diagnostics, biological identification, etc., is a significant limitation of silicon detectors.

The invention CN202110920144 proposes a structure and a manufacturing method for integrating a germanium detector and a silicon solar cell on the same SOI substrate, which solves the problem of SWIR infrared application, but does not realize integration with CMOS circuits, and the top silicon layer thickness of the SOI substrate limits the thickness of the absorption layer of the solar cell, and the substrate cost is also higher than that of a common silicon substrate.

Disclosure of Invention

The invention mainly aims to provide a photoelectric detector integrating a solar cell and a CMOS circuit and a manufacturing method thereof, and aims to solve the problems of high manufacturing difficulty and high cost of the photoelectric detector integrating the solar cell at present.

To achieve the above object, the present invention provides a photodetector integrating a solar cell and a CMOS circuit, comprising:

a silicon substrate and an oxide layer from bottom to top; wherein the silicon substrate and the oxide layer comprise a CMOS integrated circuit region, a detector region, and a silicon solar cell region;

a detector disposed in the detector region for converting the absorbed optical signal into an electrical signal;

the CMOS integrated circuit is configured in the CMOS integrated circuit area and is used for processing the electric signals output by the detector;

and the silicon solar cell is configured in the silicon solar cell area and is used for supplying power to the detector and the CMOS integrated circuit.

Optionally, in the detector region, the silicon substrate is provided with an N-well region and a P-well region sequentially from bottom to top ⁺ A conductive layer and an epitaxial layer; wherein the silicon substrate is provided with a shallow trench isolationThe epitaxial layer is arranged in the shallow trench isolation region and is obtained by removing the oxide layer of the shallow trench isolation region to expose the silicon substrate and then epitaxially growing, and the P is formed by the epitaxial layer ⁺ The conductive layer is arranged on the bottom surface and the side surface of the shallow trench isolation region and surrounds the shallow trench isolation region, and the N well region is arranged on the P well region ⁺ Bottom and side surfaces of the conductive layer surrounding P ⁺ And a conductive layer.

Optionally, the detector comprises a silicon detector and/or a germanium detector, the detector region comprises a silicon detector region and/or a germanium detector region, and the epitaxial layer comprises an epitaxial silicon layer and/or an epitaxial germanium layer.

Optionally, the epitaxial silicon layer comprises an undoped epitaxial silicon layer and N ⁺⁺ A doped epitaxial silicon layer comprising an undoped epitaxial germanium layer and N ⁺ An epitaxial germanium layer is doped.

Optionally, in the detector region, a layer of oxide layer is disposed between the silicon substrate and the oxide layer, and is disposed on two sides of the shallow trench isolation region, and is in contact with the N-well region and the P-well region ⁺ P in contact with conductive layers ⁺⁺ And a contact layer.

Optionally, in the CMOS integrated circuit region, the silicon substrate is provided with a P-well region, an N-well region, and a shallow trench isolation region disposed between the P-well region and the N-well region and contacting the oxide layer, and an N-well region is disposed between the P-well region and the oxide layer ⁺⁺ A contact layer arranged between the N well region and the oxide layer ⁺⁺ And a contact layer.

Optionally, the silicon substrate is further provided with shallow trench isolation regions between the CMOS integrated circuit region, the silicon detector region, the germanium detector region, the silicon solar cell region, and between different devices within these regions.

Optionally, in the silicon solar cell region, N is disposed between the silicon substrate and the oxide layer ⁺⁺ Contact layer and said P ⁺⁺ And a contact layer.

Optionally, the oxide layer is further provided with a layer corresponding to the N ⁺⁺ Doped epitaxial silicon layer and said N ⁺ The doped epitaxial germanium layer contacts the connected metal electrode.

Optionally, the oxide layer is provided with a layer corresponding to the N ⁺⁺ Contact layer and said P ⁺⁺ A metal electrode contacted by the contact layer.

Optionally, the metal electrode and the N ⁺⁺ Doped epitaxial silicon layer, the N ⁺ Doping epitaxial germanium layer, said N ⁺⁺ Contact layer, P ⁺⁺ The interface between the contact layers is provided with nickel silicide or nickel germanide to improve ohmic contact.

Optionally, the detector, the CMOS integrated circuit and the silicon solar cell are connected to each other by metal wiring between the metal electrodes.

In addition, in order to achieve the above object, the present invention also provides a method for manufacturing a photodetector integrating a solar cell and a CMOS circuit, comprising the steps of:

s1: selecting a silicon substrate, and dividing the silicon substrate into a CMOS integrated circuit area, a detector area and a silicon solar cell area;

s2: performing N-type ion implantation in the detector region to form an N well region, and performing annealing activation;

s3: forming a shallow trench on a silicon substrate by dry etching with a hard mask;

s4: p-type ion implantation is carried out on the shallow trench of the detector area, and annealing activation is carried out to form P ⁺ A conductive layer;

s5: filling silicon oxide and chemically mechanical polishing the shallow trench, and removing the hard mask to form a shallow trench isolation region;

s6: depositing an oxide layer, and dry etching the silicon oxide of the shallow trench isolation region of the detector region to expose the silicon surface;

s7: a selective epitaxial undoped layer;

s8: ion implantation doping is carried out on the top of the epitaxial layer;

s9: masking the epitaxial layer region of the detector by photoresist, and removing the oxide layer deposited in the step S6 by dry etching;

s10: depositing an oxide layer, photoetching a contact hole pattern, and opening electrode contact holes of the CMOS integrated circuit, the detector and the silicon solar cell by dry etching;

s11: preparing a metal electrode, photoetching a metal wiring pattern, and forming contact hole filling, the metal electrode and an interconnection line by dry etching;

s12: and (5) annealing the alloy.

Optionally, the detector region includes a silicon detector region and/or a germanium detector region.

Optionally, when the detector region is a silicon detector region, selectively epitaxially growing an undoped monocrystalline silicon layer, N being performed on top of the epitaxial silicon layer ⁺⁺ Ion implantation doping; selectively epitaxially growing a non-doped monocrystalline germanium layer on top of the epitaxial germanium layer when the detector region is a germanium detector region ⁺ And (5) ion implantation doping. N in germanium ⁺ Ion implantation is performed than N in silicon ⁺⁺ The ion implantation dose is lower because the solid solubility of impurities in germanium is lower than in silicon and implantation into germanium materials is more prone to defects, thus using lower implantation doses.

Optionally, after step S9 of the silicon detector region, or before step S6 of the germanium detector region, the method further comprises: p well region and N well region of CMOS integrated circuit region are manufactured according to conventional process, grid electrode and side wall are defined until source and drain region injection is completed, and N of CMOS integrated circuit, detector and silicon solar cell is formed ⁺⁺ Contact layer and said P ⁺⁺ A contact layer and annealing activation; wherein the N is ⁺⁺ Contact layer and said P ⁺⁺ The contact layer is used for contacting with the metal electrode.

Optionally, the method further comprises: and depositing an oxide layer, masking an absorption region of the solar cell and an absorption region of the detector by using photoresist, removing the thickness of the oxide layer just deposited by dry etching, and then forming self-aligned nickel silicide and nickel germanide on the exposed silicon and germanium surfaces respectively.

The invention provides a photoelectric detector integrating a solar cell and a CMOS circuit and a manufacturing method thereof, wherein the photoelectric detector comprises a silicon substrate and an oxide layer from bottom to top; wherein the silicon substrate and the oxide layer comprise a CMOS integrated circuit region, a detector region, and a silicon solar cell region. The invention embeds selective silicon and germanium epitaxy to manufacture silicon and germanium detector by modifying mature CMOS process flow of shallow trench isolation on silicon substrate, and uses CMOS source/drain doped layer as electrode contact layer of crystalline silicon solar cell, and connects via metal connection. The silicon solar battery provides power for the detector and the CMOS circuit, the detector converts the absorbed optical signals into electrical signals, the signals are amplified and processed through the CMOS circuit, the complete optical receiver function is realized, the silicon solar battery works independently of an external power supply, and the technical problems of high manufacturing difficulty and high cost of the photoelectric detector of the existing integrated solar battery are solved.

Drawings

Fig. 1 is a schematic structural diagram of a photodetector integrated with a solar cell and a CMOS circuit according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of a detector after N-well implantation in accordance with an embodiment of the present invention.

FIG. 3 is a schematic diagram of shallow trench isolation formation in an embodiment of the invention.

Fig. 4 is a schematic diagram of a silicon detector after epitaxy and doping in an embodiment of the invention.

Fig. 5 is a schematic diagram of a MOS transistor after gate source and drain formation in an embodiment of the invention.

Fig. 6 is a schematic diagram of a germanium detector after epitaxy and doping in accordance with an embodiment of the present invention.

Reference numerals illustrate:

1-a silicon substrate; 2-doping the well; 21-P well region; a 22-N well region; 3-P ⁺ A doped layer; 4-shallow trench isolation; a 5-epitaxial silicon single crystal layer; 51-undoped epitaxial silicon layer; 52-N ⁺⁺ Doping the epitaxial silicon layer; a 6-polysilicon/silicon oxide gate structure; 7-source-drain doping areas; 71-silicon N ⁺⁺ A layer; 72-silicon P ⁺⁺ A layer; 8-epitaxial germanium monocrystalline layer; 81-undoped epitaxial germanium layer; 82-N ⁺ Doping the epitaxial germanium layer; a 9-silicide, germanide contact layer; 91-nickel silicide NiSi; 92-nickel germanide NiGe;10 metal electrode.

The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, based on the embodiments of the invention, which would be apparent to one of ordinary skill in the art without inventive effort are within the scope of the invention.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicators are changed accordingly.

In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed by the invention.

Currently, in the related technical field, the existing integrated solar cell photodetector is difficult to manufacture and high in cost.

To solve this problem, various embodiments of the integrated solar cell and CMOS circuit photodetector and method of fabrication of the present invention are presented. The invention provides a photoelectric detector integrating a solar cell and a CMOS circuit and a manufacturing method thereof, wherein the structure and the manufacturing method integrate the detector, the solar cell and the CMOS circuit on the same silicon substrate: the detector comprises a silicon detector of a visible light wave band and a germanium detector of an infrared wave band, the CMOS circuit is used for amplifying and processing an electric signal output by the detector, and the solar battery is used for supplying power to the detector and the CMOS circuit, so that a monolithically integrated optical receiver covering the visible light to short wave infrared range is constructed.

The embodiment provides a photoelectric detector integrating a solar cell and a CMOS circuit, which comprises a silicon substrate and an oxide layer from bottom to top; wherein the silicon substrate and the oxide layer comprise a CMOS integrated circuit region, a detector region, and a silicon solar cell region; the detector is configured in the detector area and is used for converting the absorbed optical signals into electric signals; the CMOS integrated circuit is configured in the CMOS integrated circuit area and is used for processing the electric signals output by the detector; the silicon solar cell is configured in the silicon solar cell area and is used for supplying power to the detector and the CMOS integrated circuit.

As shown in fig. 1, a schematic cross-sectional structure of a photodetector of the integrated solar cell and CMOS circuit of the present invention is shown, wherein an I silicon CMOS circuit, an II silicon detector, a III germanium detector, and an IV silicon solar cell are integrated on a silicon substrate.

The silicon substrate 1 may be a 4-12 inch silicon substrate, and has a thickness of 500-800 μm and a resistivity of 0.001-10 k ohm cm for P-type, and care should be taken: 1) A silicon-on-insulator SOI (Silicon on Insulator) substrate comprising a buried oxide layer may also be selected; 2) The substrate doping type is also N.

The doped well 2 comprises a P-well region 21 and an N-well region 22 for defining the type of MOS transistor, and has a doping concentration ranging from 5E16 cm to 5E18cm ^-3 Formed by ion implantation and annealing activation; the N-well of the detector region is used to isolate the silicon and germanium detector absorption region from the P-type silicon substrate to reduce stray signals and parasitic effects from the substrate from interfering with the high-speed, high-sensitivity detector.

Bottom and side P of silicon-germanium detector ⁺ The doped layer 3 is formed by ion implantation after the silicon etching of the shallow trench region and before the silicon oxide filling, and the doping concentration range is 5E 17-5E 19cm ^-3 The function is to connect the absorber layer of the vertical PIN detector to the P of the surface ⁺⁺ The heavily doped electrode contact layer has a concentration higher than that of N well doping to reduce the series resistance of the detector and improve the radio frequency bandwidth.

The shallow trench isolation 4 is obtained by etching silicon and then filling silicon oxide, and serves as isolation between CMOS transistors and between a detector and a solar cell, and the depth of the trench is in the range of 0.2-0.6 microns.

Epitaxial silicon single crystal layer 5 (containing undoped epitaxial silicon layers 51, N ⁺⁺ Doped epitaxial silicon layer 52), which is obtained by selective silicon epitaxial growth after the silicon oxide in the shallow trench is etched and removed in the silicon detector area, the thickness of the silicon oxide is consistent with the depth of the shallow trench by 0.2-0.6 microns, namely the upper surface of the epitaxial silicon is flush with the surface of the unetched silicon substrate, so that the effect of flattening the surfaces of all devices is achieved, and integration and metal multilayer interconnection are facilitated; undoped silicon, upper N thereof, during epitaxial growth ⁺⁺ The epitaxial silicon layer is used for forming ohmic contact with metal, can be formed by ion implantation after epitaxy, can also be formed by adopting an in-situ doping mode during epitaxy, has the thickness of 50-300 nanometers and the surface doping concentration of 5E 19-2E 21cm ^-3 . The epitaxy of the silicon detector is completed before the well region of the CMOS circuit and the grid, source and drain regions of the MOS transistor are formed, so that the situation that the fine doping distribution of the MOS transistor is seriously influenced by the high thermal budget of the silicon epitaxy is avoided.

The polysilicon/silicon oxide gate structure 6 is the gate of NMOS and PMOS transistors, the thickness of the silicon oxide and the polysilicon is respectively 2-20 nanometers and 100-300 nanometers, and the doping concentration of the polysilicon is 5E 19-2E 21cm ^-3 。

Source-drain doped regions 7 formed by high-dose ion implantation and comprising silicon N ⁺⁺ Layer 71, silicon P ⁺⁺ Layer 72, junction depth of 50-300 nm, surface doping concentration of 5E 19-2E 21cm ^-3 。

Epitaxial germanium monocrystalline layer 8 (containing undoped epitaxial germanium layers 81, N ⁺ Doped epitaxial germanium layer 82), which is a single crystal layer of germanium grown by selective epitaxy after silicon oxide in shallow trenches is etched away in the germanium detector region, may be pure germanium or a germanium alloy comprising silicon, tin, lead, carbon, etc., and has a thickness consistent with the shallow trench depth of 0.2-0.6 microns, i.e., the upper surface of the epitaxial germanium is flush with the surface of the unetched silicon substrate. The epitaxial structure can be single-layer germanium epitaxy, multi-layer germanium epitaxy superposition grown under different process conditions, and a thin silicon cap layer can be further grown on the surface of the epitaxial germanium, wherein the thickness of the silicon cap layer is generally within 50 nanometersThe method comprises the steps of carrying out a first treatment on the surface of the Germanium N on the upper part thereof ⁺ The layer can be obtained by in-situ doping during epitaxy, or by ion implantation after undoped germanium epitaxy, and has a thickness of 0.05-0.2 μm and a surface doping concentration of 1E 19-5E 20cm ^-3 。

The metal electrode 10 may be obtained by evaporation, sputtering, electroplating, or the like, and may be a metal such as aluminum, tungsten, copper, titanium, tantalum, or the like, or an alloy material thereof, and has a thickness of 0.1 to 3 μm. As an alternative, between the metal electrode 10 and silicon N ⁺⁺ Layer 71, silicon P ⁺⁺ Layer 72, N ⁺⁺ Doped epitaxial silicon layer 52, N ⁺ Doping the interface between epitaxial germanium layers 82 may increase the formation of silicide 91 or germanide 92 to reduce contact resistance and sheet resistance to a thickness of 0.01-0.2 microns.

In fig. 1, the connection among the solar cell, the detector and the CMOS circuit is completed in the chip by connecting the metal electrode and the metal wiring, and the photo-generated electromotive force (voltage) of the solar cell makes the detector in a negative bias operation state and the CMOS circuit in a set driving voltage operation state. Fig. 1 is a schematic cross-sectional view of an integrated structure, and a real system has a more complex design, and is formed by connecting a plurality of different MOS transistors, silicon detectors, germanium detectors and solar cells, and may also include passive devices such as resistors, capacitors, inductors, etc. formed by standard CMOS processes. Because of the difference of the battery structure and the external light intensity, the voltage of the silicon solar battery can be in the range of 0.5-0.7V, and a plurality of solar batteries can be integrated in series in a chip according to the bias point selection of the detector and the power supply voltage requirement of the CMOS circuit, so as to obtain the actually required working voltage.

The embodiment provides a photoelectric detector integrating a solar cell and a CMOS circuit, which integrates a silicon and germanium detector with the silicon solar cell and the CMOS circuit on the same silicon substrate, so that the complete functions of power supply, detection and signal processing are realized; meanwhile, the silicon and germanium detector is enough to completely cover the wave band of visible short wave infrared SWIR, so that the wide application scene is satisfied; the process flow is compatible with CMOS, the surface of the integrated structure is smooth, and the defect that the integration is difficult due to overlarge step fluctuation in the prior art is overcome; not only suitable for bulk silicon substrates, but also suitable for silicon-on-insulator (SOI) substrates, has a high degree of flexibility and better economy.

The embodiment of the invention also provides a method for manufacturing the integrated solar cell and CMOS circuit photoelectric detector, which is used for manufacturing the integrated solar cell and CMOS circuit photoelectric detector, and comprises the following steps:

step one: an 8 inch P (100) silicon substrate is selected, the thickness of the substrate is 725 microns, and the resistivity is 10 ohm cm.

Step two: masking other regions with photoresist, and implanting ions into silicon detector and germanium detector regions under the conditions of phosphorus ion/450 keV/1.3E13cm ^-2 7 degrees; after photoresist removal and cleaning, impurities are activated by rapid thermal annealing at 1030 degrees/5 seconds in a nitrogen atmosphere, so that an N well of a detector region is formed, and isolation between the N well and a P type substrate is realized, as shown in fig. 2.

Step three: thermal oxidation to form 10 nm silicon dioxide and LPCVD to deposit 160 nm silicon nitride, photoetching and etching to form hard mask, and dry etching to form shallow trenches of 400 nm depth on the silicon substrate.

Step four: masking other regions with photoresist, and implanting ions in shallow trench regions of silicon detector and germanium detector under the condition of boron ion/10 keV/2E14cm ^-2 0 degrees; after photoresist removal and cleaning, the impurities are activated by rapid thermal annealing at 1000 ℃ per 5 seconds in nitrogen atmosphere, and P is formed on the bottom surface and the side surface of the shallow trench ⁺ And (5) doping.

Step five: chemical vapor deposition (HDP PECVD) of silicon dioxide 700 nm is used to fill the shallow trenches, chemical Mechanical Polishing (CMP) is used to remove the residual silicon nitride layer by a thickness of about 35 nm lost by the silicon nitride hard mask, and the silicon oxide filling of the shallow trenches is completed to form isolation by boiling with concentrated phosphoric acid at 155 ℃ for 60 minutes, as shown in fig. 3.

Step six: and (3) PECVD (plasma enhanced chemical vapor deposition) is carried out to deposit the silicon dioxide layer I with the thickness of 0.1 micrometer, and the silicon dioxide layer I of the silicon detector area and the HDP silicon dioxide layer filled in the previous step are etched by a dry method under the masking of photoresist, and photoresist is removed for cleaning, so that the silicon surface is exposed.

Step seven: the thickness of the selectively epitaxial undoped monocrystalline silicon layer was 0.4 microns.

Step eight: with lower energy N on top of epitaxial silicon layer with photoresist masking other regions ⁺⁺ Ion implantation under the conditions of phosphorus ion/10 keV/4E15cm ^-2 7 degrees; after photoresist removal and cleaning, the impurity is activated by rapid thermal annealing at 1030 ℃ for 5 seconds in nitrogen atmosphere, and N is formed on the top of the epitaxial silicon ⁺⁺ Doping.

Step nine: the maskless dry etch removes the oxide layer I as shown in fig. 4.

Step ten: the P/N well region of the CMOS is manufactured according to the conventional process, the grid electrode and the side wall of the MOS transistor are defined until the injection and the annealing activation of the source region and the drain region are completed, and the anode and the cathode of the solar cell and the P of the silicon and germanium detector are formed while the source region and the drain region of the MOS transistor are manufactured ⁺⁺ The contact area is shown in fig. 5.

Step eleven: and (3) PECVD (plasma enhanced chemical vapor deposition) is carried out to deposit an oxide layer II with the thickness of 0.1 micrometer, and the oxide layer II of the germanium detector area is removed by dry etching in other areas masked by photoresist, so that the silicon surface is exposed.

Step twelve: the thickness of the selective epitaxial undoped single crystal germanium was 0.4 microns.

Step thirteen: with the photoresist masking other regions, a lower energy N is provided on top of the epitaxial germanium layer ⁺ Ion implantation under the conditions of phosphorus ion/10 keV/4E14cm ^-2 7 degrees; after photoresist removal and cleaning, the impurities are activated by rapid thermal annealing at 800 ℃ per 5 seconds in nitrogen atmosphere, and N is formed on the top of the epitaxial silicon ⁺ Doping.

Step fourteen: the oxide layer II is removed by dry etching as shown in fig. 6.

Fifteen steps: PECVD is used for depositing an oxide layer III with the thickness of 0.1 micrometer, the photoresist is used for masking the absorption areas of the solar cell and the detector, and the exposed oxide layer III is removed by dry etching.

Step sixteen: self-aligned nickel silicide and nickel germanide are formed on the exposed silicon and germanium surfaces, respectively, to improve subsequent ohmic contact quality and reduce series resistance. The conventional two-step annealing method is adopted to form low-resistance silicide NiSi and NiGe phases: 1) Sputtering 10 nm metallic nickel; 2) Annealing at 280 ℃ for 5min in nitrogen atmosphere, and reacting the exposed silicon and germanium surfaces with nickel to generate high-resistance nickel-rich silicide and germanide phases respectively; 3) Corroding in heated concentrated sulfuric acid for 3min, and removing metallic nickel which has not reacted to generate silicide; 4) Annealing at 400 ℃ for 30sec in nitrogen atmosphere converts nickel-rich silicide phase, germanide phase into low-resistance NiSi silicide phase, niGe germanide phase.

Seventeenth step: PECVD deposited 0.4 micron silicon dioxide was used as the dielectric layer prior to metallization.

Eighteenth step: and photoetching a contact hole pattern, and etching the 0.4-micrometer oxide layer by a dry method, and simultaneously opening electrode contact holes of the MOS tube, the silicon detector, the germanium detector and the solar cell.

Nineteenth step: sputtering 0.6 micron aluminum, photolithography metal wiring pattern, and dry etching aluminum to form contact hole filling and interconnection lines.

Twenty steps: the alloy was annealed at 350 c/30 min under a synthesis gas (90% nitrogen+10% hydrogen mix) environment.

So far, the fabrication of all active devices (MOS transistors, detectors and solar cells) on the chip has been completed, as shown in fig. 1. According to specific requirements, the multi-layer wiring of the CMOS circuit, the manufacturing of passive devices (various inductances, capacitances and resistances) and the passivation protection layer of the chip surface can be finished in the follow-up process; if the single-layer or multi-layer composite anti-reflection film is used in a wavelength range with larger light reflection in the detector and the solar cell, single-layer or multi-layer composite anti-reflection film applied to specific wavelengths can be manufactured through the process steps of deposition, photoetching, etching and the like, and reflected light is reduced so as to obtain better application effects.

Other embodiments or specific implementations of the method for manufacturing a photodetector integrated with a solar cell and a CMOS circuit of the present invention may refer to the above-mentioned embodiments of the photodetector integrated with a solar cell and a CMOS circuit, and are not described herein again.

The foregoing description is only of the preferred embodiments of the invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalent structure or equivalent flow scheme disclosed in the specification and drawings, or any other related art, directly or indirectly, as desired.

Claims

1. A photodetector integrated with a solar cell and CMOS circuitry, comprising:

a silicon solar cell disposed in the silicon solar cell region for powering the detector and the CMOS integrated circuit;

in the detector region, the silicon substrate is sequentially provided with an N well region and a P well region from bottom to top ⁺ A conductive layer and an epitaxial layer; wherein the silicon substrate is provided with a shallow trench isolation region, the epitaxial layer is arranged in the shallow trench isolation region and is obtained by removing an oxide layer of the shallow trench isolation region to expose the silicon substrate and then epitaxially growing, and the P is the same as the oxide layer of the shallow trench isolation region ⁺ The conductive layer is arranged on the bottom surface and the side surface of the shallow trench isolation region and surrounds the shallow trench isolation region, and the N well region is arranged on the P well region ⁺ Bottom and side surfaces of the conductive layer surrounding P ⁺ And a conductive layer.

2. The integrated solar cell and CMOS circuit photodetector of claim 1 wherein the detector comprises a silicon detector and/or a germanium detector, the detector region comprises a silicon detector region and/or a germanium detector region, and the epitaxial layer comprises an epitaxial silicon layer and/or an epitaxial germanium layer.

3. The integrated solar cell and CMOS circuit photodetector of claim 2 wherein said epitaxial silicon layer comprises an undoped epitaxial silicon layerAnd N ⁺⁺ A doped epitaxial silicon layer comprising an undoped epitaxial germanium layer and N ⁺ An epitaxial germanium layer is doped.

4. The integrated solar cell and CMOS circuit photodetector of claim 3 wherein said silicon substrate and said oxide layer are disposed on opposite sides of said shallow trench isolation region and are in contact with said N-well region and P-well region, respectively, in said detector region ⁺ P in contact with conductive layers ⁺⁺ And a contact layer.

5. The integrated solar cell and CMOS circuit photodetector of claim 1 wherein said CMOS integrated circuit region has a P-well region and an N-well region and a shallow trench isolation region disposed between said P-well region and N-well region and in contact with said oxide layer, said N-well region being disposed between said P-well region and said oxide layer ⁺⁺ A contact layer arranged between the N well region and the oxide layer ⁺⁺ And a contact layer.

6. The integrated solar cell and CMOS circuit photodetector of claim 2 wherein said silicon substrate is further provided with shallow trench isolation regions between said CMOS integrated circuit region, said silicon detector region, said germanium detector region, said silicon solar cell region and between different devices within said regions.

7. The integrated solar cell and CMOS circuit photodetector of claim 1 wherein N is disposed between said silicon substrate and said oxide layer in said silicon solar cell region ⁺⁺ Contact layer and P ⁺⁺ And a contact layer.

8. The integrated solar cell and CMOS circuit photodetector of claim 3 wherein said oxide layer is further provided with a plurality of layers respectively associated with said N ⁺⁺ Doped epitaxial silicon layer and said N ⁺ And doping the metal electrode contacted with the epitaxial germanium layer.

9. The integrated solar cell and CMOS circuit photodetector of claim 4, 5 or 7 wherein said oxide layer is provided with a layer of silicon oxide which is respectively associated with said N ⁺⁺ Contact layer and said P ⁺⁺ The contact layer contacts the connected metal electrode.

10. The integrated solar cell and CMOS circuit photodetector of claim 9 wherein said detector, said CMOS integrated circuit and said silicon solar cell are interconnected by metal wiring between said metal electrodes.

11. A method of fabricating a photodetector integrated with a solar cell and CMOS circuitry, comprising the steps of:

s7: a selective epitaxial undoped layer;

s8: ion implantation doping is carried out on the top of the epitaxial layer;

s11: preparing a metal electrode, photoetching a metal wiring pattern, and forming contact hole filling, a metal electrode and an interconnection line by dry etching;

s12: and (5) annealing the alloy.

12. The method of fabricating a photodetector for integrated solar cells and CMOS circuitry according to claim 11 wherein said detector region comprises a silicon detector region and/or a germanium detector region.

13. The method of fabricating a photodetector for integrated solar cells and CMOS circuitry according to claim 12, wherein in step S7, when said detector region is a silicon detector region, selectively epitaxially non-doped monocrystalline silicon layer is performed on top of the epitaxial silicon layer with N ⁺⁺ Ion implantation doping; selectively epitaxially growing a non-doped monocrystalline germanium layer on top of the epitaxial germanium layer when the detector region is a germanium detector region ⁺ And (5) ion implantation doping.

14. The method of fabricating a photodetector for an integrated solar cell and CMOS circuit according to claim 12, further comprising: when the detector area is a silicon detector area, between the step S9 and the step S10, or between the step S5 and the step S6 when the detector area is a germanium detector area, a P well area and an N well area of a CMOS integrated circuit area are manufactured according to a conventional process, a grid electrode and a side wall are defined until source and drain area injection is completed, and an N of the CMOS integrated circuit, the detector and a silicon solar cell is formed ⁺⁺ Contact layer and said P ⁺⁺ A contact layer and annealing activation; wherein the N is ⁺⁺ Contact layer and said P ⁺⁺ The contact layer is used for contacting with the metal electrode.

15. The method of fabricating a photodetector for integrated solar cells and CMOS circuitry according to claim 14, wherein in step S6, said method further comprises: and depositing an oxide layer, masking the absorption areas of the solar cell and the detector by using photoresist, removing the thickness of the oxide layer just deposited by dry etching, and then forming self-aligned nickel silicide and nickel germanide on the exposed silicon and germanium surfaces respectively.