CN116030763B - Display panel and display device - Google Patents
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- CN116030763B CN116030763B CN202310328572.1A CN202310328572A CN116030763B CN 116030763 B CN116030763 B CN 116030763B CN 202310328572 A CN202310328572 A CN 202310328572A CN 116030763 B CN116030763 B CN 116030763B
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Abstract
The present disclosure relates to a display panel and a display device. The display area of the display panel comprises M pixel rows arranged in the column direction, each pixel row comprises a plurality of minimum repeating units, each minimum repeating unit comprises a detection line and a plurality of sub-pixels, each sub-pixel comprises a light emitting device and a detection module, each detection module is provided with a control end, a first end and a second end, the first end of each detection module is connected with an anode of the light emitting device, and in the minimum repeating units: the detection line is connected with the second end of the detection module of each sub-pixel, wherein a plurality of sub-pixels in the minimum repeating unit are divided into Q groups; the pixel line may further include Q detection scan lines, which can be sequentially scanned when the light emitting devices of the pixel line display; the Q-th detection scanning line is connected with the control end of the detection module of all sub-pixels of the Q-th group in the minimum repeating unit, Q is more than or equal to 1 and less than or equal to Q, and 1 is more than or equal to M. The scheme can improve the accuracy of the data returned by the detection line.
Description
Technical Field
The disclosure belongs to the technical field of display, and particularly relates to a display panel and a display device.
Background
Currently, in a conventional large-sized organic light emitting display screen (abbreviated as OLED screen), its pixels are composed of four sub-pixels of R (red), G (green), B (blue) and W (white), each sub-pixel has its own data signal line, and the detection line is shared by the 4 sub-pixels in the pixel, so that the data detected by the detection line is a mixed state of the 4 sub-pixels, resulting in a large error between the data transmitted back to the timing controller (abbreviated as TCON) and the actual state of the sub-pixels, thereby affecting the display screen.
Disclosure of Invention
The disclosure provides a display panel and a display device, which can improve accuracy of data transmitted back by a detection line, thereby improving display effect.
A first aspect of the present disclosure provides a display panel, a display area of the display panel including M rows of pixel rows arranged in a column direction, the pixel rows including a plurality of minimum repeating units, each of the minimum repeating units including a detection line and a plurality of sub-pixels, the sub-pixels including a light emitting device and a detection module having a control end, a first end, and a second end, the first end of the detection module being connected to an anode of the light emitting device, among the minimum repeating units: the detection line is connected with the second end of the detection module of each sub-pixel, wherein,
the plurality of sub-pixels in the minimal repeating unit are divided into Q groups;
the pixel row further comprises Q detection scanning lines, and the Q detection scanning lines can sequentially scan when the light emitting devices of the pixel row display;
the Q-th detection scanning line is connected with the control end of the detection module of all sub-pixels of the Q-th group in the minimum repeating unit, Q is more than or equal to 1 and less than or equal to Q, and 1 is more than or equal to M.
In an exemplary embodiment of the disclosure, the non-display area of the display panel is provided with M detection scanning signal output groups arranged in a column direction, and each detection scanning signal output group includes Q detection scanning signal output terminals that are independent of each other, and the Q detection scanning signal output terminals sequentially output detection scanning signals; wherein, the liquid crystal display device comprises a liquid crystal display device,
the output end of the q-th line detection scanning signal in the M-th line detection scanning signal output group is connected with the q-th line detection scanning line in the M-th line pixel row, wherein M is more than or equal to 1 and less than or equal to M.
In an exemplary embodiment of the disclosure, Q is equal to 2, and the non-display area of the display panel is provided with a detection scanning signal trigger end, M detection scanning signal output ends, M first logic gate circuits and second logic gate circuits connected to adjacent first logic gate circuits, and the M detection scanning signal output ends sequentially output detection scanning signals according to the order from 1 st to M, each first logic gate circuit includes a first and gate, a second and gate and a first not gate connected to the first and gate and the second and gate, and each second logic gate circuit includes a second not gate; wherein, the liquid crystal display device comprises a liquid crystal display device,
the output end of the first AND gate in the mth first logic gate circuit is connected with the 1 st row detection scanning line in the mth row pixel row, and in the mth first logic gate circuit: the output end of the first AND gate is connected with the first input end of the second AND gate through the first NOT gate;
the output end of the second AND gate in the mth first logic gate circuit is connected with the first input end of the first AND gate in the (m+1) th first logic gate circuit through the second NOT gate, and is also connected with the 2 nd row detection scanning line in the mth row pixel row, and m+1 is less than or equal to M;
the output end of the mth detection scanning signal is connected with the second input ends of the first AND gate and the second AND gate of the mth first logic gate circuit;
the first input end of the first AND gate in the 1 st first logic gate circuit is connected with the detection scanning signal trigger end, and the trigger signal output by the detection scanning signal trigger end is positioned in the range of the detection scanning signal output by the 1 st detection scanning signal output end.
In an exemplary embodiment of the disclosure, a rising edge of the trigger signal output by the trigger end of the detection scan signal coincides with a rising edge of the detection scan signal output by the 1 st detection scan signal output end;
the ratio of the duration of the trigger signal output by the trigger end of the detection scanning signal to the duration of the detection scanning signal output by the 1 st detection scanning signal output end is 1/2;
the duration of the detection scanning signals output by the M detection scanning signal output ends is equal.
In one exemplary embodiment of the present disclosure, Q is equal to 2, and each group of the minimal repeating units includes at least two sub-pixels; wherein, the liquid crystal display device comprises a liquid crystal display device,
the plurality of sub-pixels in the minimum repeating unit are sequentially arranged in the row direction, in the pixel row, the control end of the detection module of the sub-pixel in the minimum repeating unit in the odd number is connected with one detection scanning line, and the control end of the detection module of the sub-pixel in the even number in the minimum repeating unit is connected with the other detection scanning line.
In an exemplary embodiment of the present disclosure, each group of the minimal repeating units includes two sub-pixels arranged in a row direction and adjacent to each other.
In an exemplary embodiment of the present disclosure, any two sub-pixels adjacent in the row direction in the minimum repeating unit are arranged in a mirror image.
In an exemplary embodiment of the present disclosure, the pixel row further includes a row driving scan line, the minimum repeating unit further includes a plurality of data lines and a power line in one-to-one correspondence with the sub-pixels, and the sub-pixels further include a data writing transistor, a driving transistor, and a storage capacitor, and the detecting module is a detecting transistor, in the minimum repeating unit: the control end of the data writing transistor of each sub-pixel is connected with the row driving scanning line of the pixel row where the data writing transistor is located, the first end of the data writing transistor of each sub-pixel is connected with a corresponding data line, the second end of the data writing transistor of each sub-pixel is connected with the control end of the driving transistor and the first pole of the storage capacitor, the first end of the driving transistor of each sub-pixel is connected with the same power line, and the second end of the driving transistor of each sub-pixel and the second pole of the storage capacitor are connected with the anode of the light emitting device.
In an exemplary embodiment of the present disclosure, the data writing transistor, the driving transistor, and the detecting transistor are all N-type transistors; and/or
The minimum repeated units positioned in the same column share the same detection line and the same power line, and the sub-pixels positioned in the same column share the same data line; and/or
The minimum repeating unit comprises four sub-pixels which are different in color and sequentially arranged in the row direction, wherein the four sub-pixels with different colors are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel.
A second aspect of the present disclosure provides a display device, including a timing controller and a display panel according to any one of the above, wherein the timing controller is connected to at least the detection line and the detection scan line.
The scheme of the disclosure has the following beneficial effects:
according to the method and the device, the plurality of detection scanning lines which are sequentially scanned are arranged in the pixel row, sub-pixels in the minimum repeating unit can be detected in a grouping mode by the aid of the same detection line, that is, the number of the sub-pixels detected by the detection line at the same time is reduced, and therefore compared with the scheme that all sub-pixel data in the minimum repeating unit are detected by the aid of the same detection line at the same time, the number of the data detected by the detection line is increased under the condition that the detection line is not increased, and therefore accuracy of data transmitted back by the detection line can be improved, and display effect can be improved.
Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.
Fig. 1 is a schematic structural diagram of a display panel according to an embodiment of the disclosure.
Fig. 2 is a schematic structural diagram of a display area in a display panel according to an embodiment of the disclosure.
Fig. 3 is a schematic diagram illustrating connection between a minimum repeating unit and a column driving scan line and a detection scan line in a display panel according to an embodiment of the disclosure.
Fig. 4 is a schematic diagram illustrating connection between sub-pixels and row driving scan lines, detection lines, power lines and data lines in a display panel according to an embodiment of the disclosure.
Fig. 5 is a schematic diagram illustrating connection between a minimum repeating unit and a column driving scan line and a detection scan line in a display panel according to a second embodiment of the disclosure.
Fig. 6 is a schematic structural diagram of a display area and a non-display area in a display panel according to a third embodiment of the present disclosure.
Fig. 7 is a schematic view of a portion of a non-display area in a display panel according to a fourth embodiment of the disclosure.
Fig. 8 is a timing chart corresponding to a front-end system of a non-display area in a display panel according to a fourth embodiment of the disclosure.
Fig. 9 is a schematic structural diagram of a display device according to a fifth embodiment of the disclosure.
Reference numerals illustrate:
1. a display area; 11. a pixel row; 110. a row driving scanning line; 111. detecting a scanning line; 112. a detection line; 113. a power line; 114. a sub-pixel; 115. a data line;
2. a non-display area; 21. detecting a scanning signal output set; 210. detecting a scanning signal trigger end; 211. detecting a scanning signal output end; 212. a first logic gate circuit; 2121. a first AND gate; 2122. a second AND gate; 2123. a first NOT gate; 213. a second logic gate circuit; 2131. a second NOT gate;
3. a timing controller;
x, row direction; y, column direction; t1, a driving transistor; C. a storage capacitor; l, a light-emitting device; t2, a data writing module; and T3, a detection module.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the disclosed aspects may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the disclosure.
The disclosure is further described in detail below with reference to the drawings and detailed description. It should be noted that the technical features of the embodiments of the present disclosure described below may be combined with each other as long as they do not collide with each other. The embodiments described below by referring to the drawings are exemplary and intended for the purpose of explaining the present disclosure and are not to be construed as limiting the present disclosure.
As shown in fig. 1, the disclosed embodiments provide a display panel that may include a display area 1 and a non-display area 2 disposed around the display area 1. As shown in fig. 2 and 3, the display area 1 may include M rows of pixel rows 11 arranged in the column direction Y, each pixel row 11 may include one row driving scan line 110, at least one detection scan line 111, and a plurality of minimum repeating units, and each minimum repeating unit may include one detection line 112, one power line 113, a plurality of sub-pixels 114, and a plurality of data lines 115.
It should be understood that, as shown in fig. 2, the whole of the row driving scan line 110 and the detection scan line 111 may extend in the row direction X, the whole of the detection line 112, the power line 113 and the data line 115 may extend in the column direction Y, and the structures may not be linear, but may be modified according to the arrangement of other surrounding structures, that is, the row driving scan line 110, the detection scan line 111, the detection line 112, the power line 113 and the data line 115 are not limited to be linear.
As shown in fig. 3 and 4, the sub-pixel 114 may include a driving transistor T1, a storage capacitor C, a light emitting device L, a data writing module T2 and a detecting module T3, where the driving transistor T1, the data writing module T2 and the detecting module T3 all have a control end, a first end and a second end, the storage capacitor C has a first pole and a second pole, the control end of the data writing module T2 may be connected to the row driving scan line 110, the first end of the data writing module T2 is connected to the data line 115, the second end of the data writing module T2 is connected to the control end of the driving transistor T1 and the first pole of the storage capacitor C, the first end of the driving transistor T1 is connected to the power line 113, the second end of the driving transistor T1, the first end of the detecting module T3 and the second pole of the storage capacitor C are connected to the anode of the light emitting device L, and the cathode of the light emitting device L is grounded VSS.
For example, the data writing module T2 may be a data writing transistor, and the detecting module T3 may be a detecting transistor, that is, the sub-pixel 114 of the present embodiment may be a 3T1C circuit, that is, 3 TFTs (simply referred to as transistors) and a capacitor, but it should be understood that the sub-pixel 114 of the present embodiment is not limited to the 3T1C circuit, but may be other circuit structures as appropriate.
For the aforementioned 3T1C circuit architecture, the pixel 114 of this embodiment operates as follows:
in the data writing stage, the data writing transistor is in an on state in response to the signal provided by the row driving scanning line 110, and makes the data provided by the data line 115 stored in the storage capacitor C, at this time, the storage capacitor C is in a charging process, and the detecting transistor is in an off state in response to the signal provided by the detecting scanning line 111;
in the display lighting phase, the data writing transistor responds to the signal provided by the row driving scanning line 110 to be in a closed state, at this time, the storage capacitor C is in a discharging process, the driving transistor T1 is turned on, the working voltage provided by the power line 113 is input to the anode of the light emitting device L, the light emitting device L is lightened to realize display lighting, in addition, the detecting transistor responds to the signal provided by the detecting scanning line 111 to be in an open state, so that the detecting line 112 can detect the current state of the light emitting device L and transmit the current state back to the TCON, and the TCON controls the source driving chip to provide data matched with the data line 115 according to the returned signal.
In this embodiment, the data writing transistor, the driving transistor T1 and the detecting transistor may be the same type transistors, for example, all N-type transistors or all P-type transistors, so that the process is simplified and the cost is reduced. The data writing transistor, the driving transistor T1 and the detecting transistor are all N-type transistors, and the data writing transistor, the driving transistor T1 and the detecting transistor are in an on state when the control ends of the data writing transistor, the driving transistor T1 and the detecting transistor respond to a high level signal and are in an off state when the control ends of the data writing transistor, the driving transistor T1 and the detecting transistor respond to a low level signal.
In addition, the light emitting device L of the present embodiment may be an OLED (organic light emitting diode), that is, the display panel of the present embodiment may be an OLED display.
In this embodiment, in the minimal repeating unit: the number of the sub-pixels 114 may be the same as the number of the data lines 115, and the sub-pixels 114 and the data lines 115 are in a one-to-one connection relationship, that is, the first end of the data writing transistor of each sub-pixel 114 is connected to a corresponding one of the data lines 115, and the control end of the data writing transistor of each sub-pixel 114 is connected to the row driving scanning line 110 of the pixel row 11 where the control end of the data writing transistor of each sub-pixel 114 is located, the first end of the driving transistor T1 of each sub-pixel 114 is connected to the same power line 113, and the detection transistor of each sub-pixel 114 is connected to the same detection line 112.
Further, as shown in fig. 2, the minimum repeating units in the same column may share the same detecting line 112 and the same power line 113, the sub-pixels 114 in the same column may share the same data line 115, and in addition, the minimum repeating units in the same row share the same row driving scanning line 110, so as to simplify the structure and reduce the cost.
The following describes a detection mode of the display panel of the present application in detail with reference to the accompanying drawings.
As shown in fig. 2 and 3, each pixel row 11 may include Q detection scan lines 111, where the Q detection scan lines 111 can sequentially scan when the light emitting devices L of the pixel row 11 display, and it should be understood that the scanning time of the Q detection scan lines 111 is between the row driving scanning phases of two adjacent pixel rows 11, that is, after the row driving scan line 110 of the current pixel row 11 has supplied with the active level signal (the signal for controlling the data writing transistor to be turned on), the phase before the row driving scan line 110 of the next pixel row 11 has supplied with the active level signal (the signal for controlling the data writing transistor to be turned on) is the period during which the Q detection scan lines 111 of the current pixel row 11 sequentially scan.
Wherein, when each pixel row 11 includes Q detection scan lines 111, the plurality of sub-pixels 114 in the minimum repeating unit may be divided into Q groups; the Q-th detection scan line 111 is connected to the control end of the detection module T3 of all sub-pixels 114 in the Q-th group in the minimum repeating unit, wherein Q is greater than or equal to 1 and less than or equal to Q, and 1 is less than M, that is, each pixel row 11 includes at least 2 detection scan lines 111, and the plurality of sub-pixels 114 in each minimum repeating unit is divided into at least 2 groups.
In this embodiment, by arranging a plurality of detection scan lines 111 that sequentially scan in the pixel row 11, the sub-pixels 114 in the minimum repeating unit can be detected in groups by using the same detection line 112, that is, the sub-pixels 114 detected by the detection line 112 simultaneously are reduced, so that compared with the scheme of detecting all the sub-pixel 114 data in the minimum repeating unit simultaneously by using the same detection line 112, the data detected by the detection line 112 is increased without increasing the detection line 112, and therefore, the accuracy of the data transmitted by the detection line 112 can be improved, so that the display effect can be improved.
For example, as shown in fig. 3, each group of the minimal repeating units may include two sub-pixels 114 arranged and adjacent in the row direction X, that is: in the pixel row 11: each of the detection scanning lines 111 is connected to two adjacent sub-pixels 114 in the minimum repeating unit, that is, when each of the detection scanning lines 111 scans, the detection lines 112 simultaneously detect the display of the two sub-pixels 114 in each of the minimum repeating units, so that compared with the scheme that each of the sub-pixels 114 in the minimum repeating unit is respectively matched with one of the detection scanning lines 111, the number of the detection scanning lines 111 can be reduced, thereby achieving the purposes of high PPI (pixel density) and low process cost, and simultaneously, compared with the scheme that the same detection line 112 is used for simultaneously detecting the data of all the sub-pixels 114 in the minimum repeating unit, the data detected by the detection lines 112 is increased without increasing the detection lines 112, and therefore, the accuracy of the data transmitted by the detection lines 112 can be improved, and the display effect can be improved.
Further, as shown in fig. 3, the arrangement manner of the adjacent sub-pixels 114 in the row direction X of any two of the minimum repeating units is mirror image, so that the distance between the detection modules T3 of the adjacent sub-pixels 114 is increased, when the detection modules T3 are connected with the same detection scanning line 111, the response time of the detection modules T3 of the two sub-pixels 114 is properly staggered due to a certain delay in the transmission process of the signal, so that a staggered time difference exists in the process of transmitting the data back to the detection line 112 by the detection modules T3 of the two sub-pixels 114, so as to reduce the mixing degree when the data back to the detection line 112 by the detection modules T3 of the two sub-pixels 114, and thus, for example, the accuracy of the data transmitted back by the detection line 112 can be properly improved: the detection line 112 may detect the time period of the two sub-pixels 114, the data acquired in the first half may be the return data of the sub-pixel 114 closer to the first half, the data acquired in the middle may be the return mixed data of the two sub-pixels 114, and the data acquired in the second half may be the return data of the sub-pixel 114 farther from the second half, so that the first half and the second half correspond to the data more accurate to the two sub-pixels 114, so that the more accurate the data returned to TCON is, the better the display compensation is.
In this embodiment, Q may be equal to 2, that is, as shown in fig. 2 and 3, the pixel row 11 includes 2 rows of detection scan lines 111, the plurality of sub-pixels 114 in the minimum repeating unit are divided into 2 groups, wherein the 1 st row of detection scan lines 111 in the pixel row 11 is connected to the control end of the detection module T3 of all sub-pixels 114 in the 1 st group in the minimum repeating unit, and the 2 nd row of detection scan lines 111 in the pixel row 11 is connected to the control end of the detection module T3 of all sub-pixels 114 in the 2 nd group in the minimum repeating unit, so that the design is superior to the scheme of simultaneously detecting the data of all sub-pixels 114 in the minimum repeating unit by using the same detection line 112, each pixel row 11 is increased by only one detection scan line 111, so that the display device is in a better balance state in both high PPI and detection accuracy.
For example, the minimum repeating unit may include four sub-pixels 114 with different colors and sequentially arranged in the row direction X, the four sub-pixels 114 with different colors are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, and if the four sub-pixels 114 with different colors are sequentially arranged in the row direction X, the control ends of the detection modules T3 of the red sub-pixel and the white sub-pixel may be connected with the 1 st row detection scanning line 111 in the pixel row 11, and the control ends of the detection modules T3 of the green sub-pixel and the blue sub-pixel may be connected with the 2 nd row detection scanning line 111 in the pixel row 11.
Example two
The main difference between this embodiment and the first embodiment is that: the division manner of each group of sub-pixels 114 in the minimum repeating unit is different, and the description of the first embodiment is referred to for other matters, and the description is not repeated here.
The specific division manner of this embodiment is as follows:
as shown in fig. 5, Q may be equal to 2, with each group in the minimal repeating unit comprising at least two subpixels 114; the plurality of sub-pixels 114 in the minimum repeating unit are sequentially arranged in the row direction X, in the pixel row 11, the control end of the detection module T3 of the sub-pixel 114 in the minimum repeating unit located at the odd number is connected with one row of the detection scanning line 111, the control end of the detection module T3 of the sub-pixel 114 in the even number in the minimum repeating unit is connected with the other row of the detection scanning line 111, that is, the plurality of sub-pixels 114 in the minimum repeating unit are divided into 2 groups, the first group can be an odd-numbered group, and the second group can be an even-numbered group, so that the distance between the detection modules T3 of the two adjacent sub-pixels 114 connected with the same row of the detection scanning line 111 is increased, and as the signal has a certain delay in the transmission process, the response time of the detection modules T3 of the two adjacent sub-pixels 114 can be properly staggered, so that there is a staggered time difference in the process of transmitting back data to the detection module T3 of the two adjacent sub-pixels 114 to the detection module 112, so that the accuracy of data transmission of the two adjacent sub-pixels 114 is improved, and the data transmission of the detection module T3 is properly, and the data transmission of the data transmission 112 is improved.
For example, the minimum repeating unit may include four sub-pixels 114 with different colors and sequentially arranged in the row direction X, the four sub-pixels 114 with different colors are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel, and if the four sub-pixels 114 with different colors are sequentially arranged in the row direction X, the control ends of the detection modules T3 of the red sub-pixel and the green sub-pixel may be connected with the 1 st row detection scanning line 111 in the pixel row 11, and the control ends of the detection modules T3 of the white sub-pixel and the blue sub-pixel may be connected with the 2 nd row detection scanning line 111 in the pixel row 11.
In the present embodiment, any two sub-pixels 114 adjacent to each other in the row direction X in the minimum repeating unit may be arranged in a mirror image, but not limited thereto, and may be arranged in the same manner, as the case may be.
Example III
The front-end system is specifically limited based on the first embodiment or the second embodiment, and the description of the other structures of the front-end system may be repeated here without being limited.
As shown in fig. 6, the front-end system of the present embodiment may include M rows of detection scan signal output groups 21 arranged in the column direction Y, specifically, the M rows of detection scan signal output groups 21 arranged in the column direction Y may be disposed in the non-display area 2 of the display panel, where each row of detection scan signal output groups 21 may include Q mutually independent detection scan signal output terminals 211, and the Q detection scan signal output terminals 211 sequentially output detection scan signals; the q-th row detection scanning signal output end 211 in the M-th row detection scanning signal output set 21 is connected with the q-th row detection scanning line 111 in the M-th row pixel row 11, wherein M is more than or equal to 1 and less than or equal to M.
In this embodiment, the detection scan signal input is directly increased by Q times through the outside, so that the detected data is increased by Q times without increasing the detection line 112, and the detection scan signal output 211 directly increased by a corresponding multiple through the outside has strong versatility, and is not limited to the architecture with Q equal to 2, but also applicable to the architecture with Q equal to 3, 4, 5, etc.
If the total detection time in each pixel row 11 is T, the scanning time of each detection scanning line 111 (i.e. the on time of the detection transistor) in each pixel row 11 is T, where t=t≡q.
In addition, it should be noted that the detection frequency of the detection line 112 in the present embodiment can be controlled by TCON.
Example IV
The main difference between this embodiment and the third embodiment is that: the configuration of the front-end system is different, and the description of the other configurations may be the first embodiment or the second embodiment, and is not repeated here.
In this embodiment, the front-end system is applicable to a configuration with Q equal to 2, specifically, as shown in fig. 7, the front-end system may include a detection scan signal trigger end 210 disposed in the non-display area 2 of the display panel, M detection scan signal output ends 211, M first logic gate circuits 212, and second logic gate circuits 213 connected to the adjacent first logic gate circuits 212, where the M detection scan signal output ends 211 sequentially output detection scan signals in the order from 1 st to M th, each first logic gate circuit 212 includes a first and gate 2121, a second and gate 2122, and a first not gate 2123 connected to the first and second and gate 2121 and 2122, and each second logic gate circuit 213 includes a second not gate 2131.
The output terminal of the first and gate 2121 in the mth first logic gate 212 is connected to the 1 st row detection scan line 111 in the mth row pixel row 11, and in the mth first logic gate 212: the output of the first and gate 2121 is connected to the first input of the second and gate 2122 via a first not gate 2123; the output end of the second AND gate 2122 in the mth first logic gate 212 is connected to the first input end of the first AND gate 2121 in the (m+1) th first logic gate 212 through the second NOT gate 2131, and is connected to the 2 nd row detection scanning line 111 in the mth row pixel row 11, and m+1 is less than or equal to M; the mth detection scan signal output 211 is connected to the second input ends of the first and gate 2121 and the second and gate 2122 of the mth first logic gate 212; the first input terminal of the first and gate 2121 in the 1 st first logic gate 212 is connected to the detection scan signal trigger terminal 210, and the trigger signal output by the detection scan signal trigger terminal 210 is within the range of the detection scan signal output by the 1 st detection scan signal output terminal 211.
In this embodiment, although the number of detection scan lines 111 in each row of pixel rows 11 in the display area 1 is increased, by providing the aforementioned logic gate circuit combination in the non-display area 2, the front-end system can be implemented by adding only one detection scan signal trigger end 210, so that while improving the accuracy of the data transmitted by the detection line 112, PCBA (for short, english Printed Circuit Board Assembly) can be saved, that is, the PCB blank is subjected to SMT mounting or the whole process of DIP plug-in, and wiring On COF (Chip On Flex, or Chip On Film, commonly called flip Film) can be reduced, and the cost is reduced.
Alternatively, as shown in fig. 8, the rising edge of the trigger signal G output by the trigger terminal 210 of the detection scan signal may coincide with the rising edge of the detection scan signal G1 output by the 1 st detection scan signal output terminal 211; the ratio of the time T of the trigger signal G output by the trigger end 210 of the detection scanning signal to the time T of the detection scanning signal G1 output by the 1 st detection scanning signal output end 211 is 1/2, so as to ensure that the scanning time of the two rows of detection scanning lines 111 in each pixel row 11 is the same, thereby ensuring the data detection accuracy of each group of sub-pixels 114 in the minimum repeating unit.
Further, as shown in fig. 8, the durations of the detection scanning signals output by the M detection scanning signal output terminals 211 are equal, so as to ensure that the detection time of each pixel row 11 is the same, thereby ensuring that the detection is more balanced and the detection is increased accurately.
The front-end system, as shown in connection with fig. 2 to 4, 7 and 8, operates as follows:
when the trigger signal G output by the detection scan signal trigger end 210 and the detection scan signal G1 output by the 1 st detection scan signal output end 211 are both H (high level), the signal g1_0 output by the output end of the first and gate 2121 in the 1 st first logic gate 212 is H, when the trigger signal G output by the detection scan signal trigger end 210 is L (low level), the signal g1_0 output by the output end of the first and gate 2121 in the 1 st first logic gate 212 is L, the H time of the detection scan signal G1 output by the 1 st detection scan signal output end 211 is T, the H time of the trigger signal G output by the detection scan signal trigger end 210 is T, and the H time of the signal g1_0 output by the output end of the first and gate 2121 in the 1 st first logic gate 212 is T, t=2t; when the signal g1_0 output by the output terminal of the first and gate 2121 in the 1 st first logic gate 212 is changed from H to L, the detection scan signal G1 output by the 1 st detection scan signal output terminal 211 is still H, the signal g1_0 output by the output terminal of the first and gate 2121 in the 1 st first logic gate 212 is also changed from H through the first not gate 2123, the signal g1_1 output by the output terminal of the second and gate 2122 in the 1 st first logic gate 212 is H, and when the detection scan signal G1 output by the 1 st detection scan signal output terminal 211 is changed from H to L, the signal g1_1 output by the output terminal of the second and gate 2122 in the 1 st first logic gate 212 is L, and so on until the output terminal of the second and gate 2122 in the M first logic gate 212 outputs gm_1.
Example five
The embodiment of the disclosure provides a display device, as shown in fig. 9, which includes a timing controller 3 and the display panel described in any one of the first to fourth embodiments, where the timing controller 3 is connected to at least the aforementioned detection line 112 and detection scan line 111, and is used for controlling the detection scan line 111 to scan, and receiving data returned by the detection line 112.
It should be understood that the timing controller 3 may also be connected to the aforementioned row driving scan lines 110, data lines 115, etc. through other circuit structures, which are not described in detail herein.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present disclosure, unless explicitly specified and limited otherwise, the term "connected" and the like should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.
In the description of the present specification, reference to the term "exemplary" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present disclosure have been shown and described above, it should be understood that the above embodiments are illustrative and not to be construed as limiting the present disclosure, and that variations, modifications, alternatives, and variations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present disclosure, which is therefore intended to be within the scope of the present disclosure as defined by the claims and specification.
Claims (9)
1. A display panel, the display area of the display panel comprising M rows of pixel rows arranged in a column direction, the pixel rows comprising a plurality of minimal repeating units, each minimal repeating unit comprising a detection line and a plurality of sub-pixels, the sub-pixels comprising a light emitting device and a detection module, the detection module having a control end, a first end and a second end, the first end of the detection module being connected to an anode of the light emitting device, among the minimal repeating units: the detection line is connected with the second end of the detection module of each sub-pixel, and is characterized in that,
the plurality of sub-pixels in the minimal repeating unit are divided into Q groups;
the pixel row further comprises Q detection scanning lines, and the Q detection scanning lines can sequentially scan when the light emitting devices of the pixel row display;
the Q-th detection scanning line is only connected with the control end of the detection module of all sub-pixels of the Q-th group in the minimum repeating unit, Q is more than or equal to 1 and less than or equal to Q, and 1 is less than M; the pixel row further comprises a row driving scanning line, the minimum repeating unit further comprises a plurality of data lines and a power line, the data lines and the power line are in one-to-one correspondence with the sub-pixels, the sub-pixels further comprise data writing transistors, driving transistors and storage capacitors, the detection module is a detection transistor, and in the minimum repeating unit: the control end of the data writing transistor of each sub-pixel is only connected with the row driving scanning line of the pixel row where the data writing transistor is located, the first end of the data writing transistor of each sub-pixel is respectively connected with a corresponding data line, the second end of the data writing transistor of each sub-pixel is connected with the control end of the driving transistor and the first pole of the storage capacitor, the first end of the driving transistor of each sub-pixel is connected with the same power line, and the second end of the driving transistor of each sub-pixel and the second pole of the storage capacitor are connected with the anode of the light emitting device.
2. The display panel according to claim 1, wherein the non-display area of the display panel is provided with M detection scanning signal output groups arranged in a column direction, and each of the detection scanning signal output groups includes Q detection scanning signal output terminals independent of each other, and the Q detection scanning signal output terminals sequentially output detection scanning signals; wherein, the liquid crystal display device comprises a liquid crystal display device,
the q-th detection scanning signal output end in the M-th detection scanning signal output group is connected with the q-th detection scanning line in the M-th pixel row, wherein M is more than or equal to 1 and less than or equal to M.
3. The display panel according to claim 1, wherein Q is equal to 2, and the non-display area of the display panel is provided with a detection scanning signal trigger terminal, M detection scanning signal output terminals, M first logic gates and second logic gates connected to adjacent first logic gates, and the M detection scanning signal output terminals sequentially output detection scanning signals in the order of 1 st to M th, each of the first logic gates including a first and gate, a second and gate and a first not gate connected to the first and gate and the second and gate, each of the second logic gates including a second not gate; wherein, the liquid crystal display device comprises a liquid crystal display device,
the output end of the first AND gate in the mth first logic gate circuit is connected with the 1 st row detection scanning line in the mth row pixel row, and in the mth first logic gate circuit: the output end of the first AND gate is connected with the first input end of the second AND gate through the first NOT gate;
the output end of the second AND gate in the mth first logic gate circuit is connected with the first input end of the first AND gate in the (m+1) th first logic gate circuit through the second NOT gate, and is also connected with the 2 nd row detection scanning line in the mth row pixel row, and m+1 is less than or equal to M;
the output end of the mth detection scanning signal is connected with the second input ends of the first AND gate and the second AND gate of the mth first logic gate circuit;
the first input end of the first AND gate in the 1 st first logic gate circuit is connected with the detection scanning signal trigger end, and the trigger signal output by the detection scanning signal trigger end is positioned in the range of the detection scanning signal output by the 1 st detection scanning signal output end.
4. The display panel according to claim 3, wherein,
the rising edge of the trigger signal output by the trigger end of the detection scanning signal coincides with the rising edge of the detection scanning signal output by the 1 st detection scanning signal output end;
the ratio of the duration of the trigger signal output by the trigger end of the detection scanning signal to the duration of the detection scanning signal output by the 1 st detection scanning signal output end is 1/2;
the duration of the detection scanning signals output by the M detection scanning signal output ends is equal.
5. The display panel of claim 1, wherein Q is equal to 2 and each group of the minimal repeating units comprises at least two subpixels; wherein, the liquid crystal display device comprises a liquid crystal display device,
the plurality of sub-pixels in the minimum repeating unit are sequentially arranged in the row direction, in the pixel row, the control end of the detection module of the sub-pixel in the minimum repeating unit in the odd number is connected with one detection scanning line, and the control end of the detection module of the sub-pixel in the even number in the minimum repeating unit is connected with the other detection scanning line.
6. The display panel of claim 1, wherein each group of the minimal repeating units comprises two adjacent sub-pixels arranged in a row direction.
7. The display panel of claim 6, wherein any two of the pixels adjacent in the row direction in the minimal repeating unit are arranged in mirror image.
8. The display panel of claim 1, wherein the display panel comprises,
the data writing transistor, the driving transistor and the detecting transistor are all N-type transistors; and/or
The minimum repeated units positioned in the same column share the same detection line and the same power line, and the sub-pixels positioned in the same column share the same data line; and/or
The minimum repeating unit comprises four sub-pixels which are different in color and sequentially arranged in the row direction, wherein the four sub-pixels with different colors are respectively a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel.
9. A display device comprising a timing controller and the display panel according to any one of claims 1 to 8, wherein the timing controller is connected to at least the detection line and the detection scanning line.
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