CN115390323A

CN115390323A - Display panel and display device

Info

Publication number: CN115390323A
Application number: CN202210999126.9A
Authority: CN
Inventors: 常红燕; 黄世帅; 韩丙; 李振亚; 郑佳阳; 胡云钦; 王晓洁; 李荣荣
Original assignee: HKC Co Ltd; Beihai HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Beihai HKC Optoelectronics Technology Co Ltd
Priority date: 2022-08-19
Filing date: 2022-08-19
Publication date: 2022-11-25
Also published as: WO2024036813A1

Abstract

The application discloses display panel and display device relates to and shows technical field. The display panel comprises a plurality of pixel electrodes, a common electrode, a common signal line, a detection line and a processor. The plurality of pixel electrodes are coupled with the common electrode to form a capacitor. The common signal line is connected between the output end of the processor and the common electrode. The detection line is connected between the detection end of the processor and the common signal line. The processor is used for outputting a preset electric signal through the output end in a first time period and detecting the voltage of the common signal line through the detection end; the processor is also used for outputting a compensation electric signal through the output end according to the voltage of the common signal line in the second period. Therefore, the voltage changes of the common electrode of the array substrate and the common electrode of the color film substrate can be detected and compensated, so that the horizontal crosstalk problem of the display panel can be solved, and the display effect of the display panel is improved.

Description

Display panel and display device

Technical Field

The present disclosure relates to display technologies, and particularly to a display panel and a display device.

Background

The display panel comprises a plurality of data lines, a plurality of pixel electrodes, a plurality of array substrate common electrodes and a color film substrate common electrode. Each pixel electrode is used for being coupled with a common electrode of the color film substrate to form a capacitor, and each pixel electrode is also used for being coupled with a common electrode of the array substrate to form a capacitor. When the display panel works, the plurality of data lines are used for inputting voltages to the plurality of pixel electrodes. The voltages of the plurality of array substrate common electrodes and the color film substrate common electrode should be kept unchanged.

However, in the display panel, parasitic capacitances exist between the data lines and the common electrode of the array substrate and between the data lines and the common electrode of the color film substrate. In this case, when the voltage output from the data line to the pixel electrode changes, the parasitic capacitance affects the array substrate common electrode and the color filter substrate common electrode, so that the voltages of the array substrate common electrode and the color filter substrate common electrode also change. In the prior art, the voltage change of the common electrode of the array substrate and the common electrode of the color film substrate cannot be detected and compensated.

Disclosure of Invention

The application provides a display panel and a display device, which can solve the problem that the voltage change of an array substrate common electrode and a color film substrate common electrode cannot be detected and compensated in the related technology. The technical scheme is as follows:

in a first aspect, a display panel is provided, including: a plurality of pixel electrodes, a common electrode, a common signal line, and a processor;

the plurality of pixel electrodes are coupled with the common electrode to form a capacitor; the processor is provided with an output end, and the common signal wire is connected between the output end and the common electrode;

the display panel further comprises a detection line, the processor is further provided with a detection end, a first end of the detection line is connected with the detection end, and a second end of the detection line is connected with the common signal line, so that the detection line and the detection end form a detection channel for detecting the voltage of the common signal line;

the processor is configured to: in a first time period, outputting a preset electric signal through the output end, and detecting the voltage of the common signal line through the detection end; outputting a compensation electric signal through the output end according to the voltage of the common signal line in a second time period, so that the output end and the common signal line form a compensation channel for compensating the voltage of the common signal line; wherein the second period is after the first period so that the voltage of the compensation electrical signal is greater than the voltage of the preset electrical signal when the voltage of the common signal line is less than the voltage of the preset electrical signal.

In the present application, the display panel includes a plurality of pixel electrodes, a common electrode (including an array substrate common electrode and a color film substrate common electrode), a common signal line, a sensing line, and a processor. The plurality of pixel electrodes are coupled with the common electrode to form a capacitor. The common signal line is connected between the output end of the processor and the common electrode. The detection line is connected between the detection end of the processor and the common signal line. When the display panel works, the processor can output the preset electric signal to the public signal line in the first period, so that the preset electric signal is output to the public electrode. Meanwhile, the processor can detect the voltage of the common signal line through the detection line, so that the voltage change of the common electrode can be detected. The processor may output the compensation electrical signal to the common signal line in the second period, and when the voltage of the common signal line is less than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is greater than the voltage of the preset electrical signal. Therefore, the voltage change of the common electrode can be compensated. The display panel can detect and compensate voltage changes of the array substrate common electrode and the color film substrate common electrode, so that the horizontal crosstalk problem of the display panel can be solved, and the display effect of the display panel is improved.

Optionally, the common electrode includes a plurality of first and second common electrodes, the common signal line includes a first signal line and a second signal line, and the output terminal includes a first port and a second port;

one of the plurality of first common electrodes is coupled with one of the plurality of pixel electrodes to form a capacitor, and the second common electrode is coupled with each of the plurality of pixel electrodes to form a capacitor;

the first signal line is connected between the first port and the plurality of first common electrodes, and the second signal line is connected between the second port and the second common electrodes;

a second end of the detection line is connected with the first signal line or the second signal line, so that the detection line and the detection end form a first detection channel for detecting the voltage of the first signal line or a second detection channel for detecting the voltage of the second signal line;

the processor is configured to: outputting a preset electric signal through the first port and the second port in a first period, and detecting the voltage of the first signal line or the second signal line through the detection end; and in a second period, outputting a compensation electric signal through the first port or/and the second port according to the voltage of the first signal line or the second signal line, so that the first port and the first signal line form a first compensation channel for compensating the voltage of the first signal line, or/and the second port and the second signal line form a second compensation channel for compensating the voltage of the second signal line.

Optionally, the display panel includes an array substrate and a color filter substrate arranged in a box-to-box manner with the array substrate, and the color filter substrate includes the second common electrode;

the array substrate comprises a substrate, and the plurality of pixel electrodes, the plurality of first common electrodes, the first signal lines, the second signal lines and the detection lines which are positioned on the substrate;

along the extending direction of the substrate base plate, the substrate base plate comprises a first area and a second area surrounding the first area, the pixel electrodes and the common electrodes are all located in the first area, and the first signal lines, the second signal lines and the detecting lines are all located in the second area; orthographic projections of the first signal line, the second signal line and the detection line on the substrate base plate are not intersected with each other.

Optionally, the first signal line is connected to the first port, and the second end of the detection line is connected to the first signal line;

the plurality of first common electrodes are arranged in a plurality of rows, and the first signal line is connected to each of the plurality of first common electrodes arranged in the plurality of rows; on the substrate base plate, the first ports are located on one side of the first common electrodes arranged in multiple rows, and the second ends of the detection lines are located on the other side of the first common electrodes arranged in multiple rows.

Optionally, the second signal line is connected to the second port, and the second signal line is connected to the second common electrode through a first metal ball; the second end of the detection line is connected with the second common electrode through a second metal ball;

the plurality of first common electrodes are arranged in a plurality of rows, and the first signal line is connected to each of the plurality of first common electrodes arranged in the plurality of rows; on the substrate base plate, the second ports are positioned on one side of the plurality of first common electrodes arranged in a plurality of rows, and the second metal balls are positioned on the other side of the plurality of first common electrodes arranged in a plurality of rows.

Optionally, the first port includes a first sub-port and a second sub-port, a first end of the first signal line is connected with the first sub-port, a second end of the first signal line is connected with the second sub-port, and the first signal line surrounds the first region;

the detecting end is positioned on one side of the first sub-port, which is far away from the second sub-port, or the detecting end is positioned on one side of the second sub-port, which is far away from the first sub-port;

the second port comprises a third sub-port and a fourth sub-port, a first end of the second signal line is connected with the third sub-port, a second end of the second signal line is connected with the fourth sub-port, the detection end, the first sub-port and the second sub-port are all located between the third sub-port and the fourth sub-port, and the detection line and the first signal line are all located in the surrounding range of the second signal line.

Optionally, the detection terminal includes a first detection port and a second detection port, and the detection line includes a first detection signal line and a second detection signal line;

the first port comprises a first sub-port and a second sub-port, a first end of the first signal line is connected with the first sub-port, a second end of the first signal line is connected with the second sub-port, and the first signal line surrounds the first area;

the first sub-port and the second sub-port are located between the first detection port and the second detection port, a first end of the first detection signal line is connected with the first detection port, a first end of the second detection signal line is connected with the second detection port, and a second end of the first detection signal line and a second end of the second detection signal line are used for being connected with the first signal line or the second signal line;

the second port comprises a third sub-port and a fourth sub-port, a first end of the second signal line is connected with the third sub-port, a second end of the second signal line is connected with the fourth sub-port, the first detecting port, the second detecting port, the first sub-port and the second sub-port are all located between the third sub-port and the fourth sub-port, and the first detecting signal line, the second detecting signal line and the first signal line are all located in a surrounding range of the second signal line.

Optionally, the processor is configured to: detecting a first voltage through the first detection port and a second voltage through the second detection port in a first period; and taking an average value of the first voltage and the second voltage as a voltage of the common signal line.

Optionally, a difference between the voltage of the compensation electrical signal and the voltage of the preset electrical signal is equal to a difference between the voltage of the preset electrical signal and the voltage of the common signal line.

In a second aspect, a display device is further provided, which includes the display panel according to any one of the first aspect, and the display device further includes a backlight source, where the display panel is located on a light emitting side of the backlight source, so that the backlight source provides a light source for the display panel.

It is understood that the beneficial effects of the second aspect can be referred to the related description of the first aspect, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic longitudinal sectional structure diagram of a display panel according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a frame structure of a display panel according to an embodiment of the present disclosure;

fig. 3 is a schematic diagram illustrating positions of a plurality of pixel electrodes on a first substrate according to a second embodiment of the present disclosure;

fig. 4 is a schematic top view of a first array substrate according to a second embodiment of the present disclosure;

fig. 5 is a schematic longitudinal cross-sectional structure diagram of a first display panel according to a second embodiment of the present disclosure;

fig. 6 is a schematic top view of a second array substrate provided in the second embodiment of the present application;

fig. 7 is a schematic longitudinal sectional structure diagram of a second display panel provided in the second embodiment of the present application;

fig. 8 is a schematic top view of a third array substrate according to the second embodiment of the present disclosure;

fig. 9 is a schematic top view of a first array substrate according to a third embodiment of the present disclosure;

fig. 10 is a schematic top view of a second array substrate according to a third embodiment of the present application;

fig. 11 is a schematic top view illustrating a third array substrate according to a third embodiment of the present disclosure;

fig. 12 is a schematic top view of a fourth array substrate according to the third embodiment of the present application;

fig. 13 is a schematic top view of a fifth array substrate according to the third embodiment of the present disclosure;

fig. 14 is a schematic top view of a sixth array substrate according to the third embodiment of the present application;

fig. 15 is a schematic top view of a seventh array substrate according to the third embodiment of the present application;

fig. 16 is a schematic top view of an eighth array substrate according to the third embodiment of the present application;

fig. 17 is a schematic top view illustrating a ninth array substrate according to a third embodiment of the present disclosure;

fig. 18 is a schematic longitudinal sectional structure diagram of a display device according to a fourth embodiment of the present application.

Wherein, the meanings represented by the reference numerals of the figures are respectively as follows:

10. a display panel;

102. a common electrode;

12. an array substrate;

122. a first base substrate;

1222. a first region;

1224. a second region;

123. a connecting wire;

124. a first common electrode;

126. an insulating layer;

128. a pixel electrode;

130. a common signal line;

132. a first signal line;

134. a second signal line;

1342. a third portion;

1344. a fourth part;

14. a color film substrate;

142. a second substrate base plate;

144. a second common electrode;

150. detecting a line;

1502. a first detection signal line;

1504. a second detection signal line;

152. a first portion;

154. a second portion;

16. a liquid crystal layer;

160. a first metal ball;

170. a second metal ball;

18. a processor;

182. a flexible circuit board;

184. a data driver.

Detailed Description

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

It should be understood that reference to "a plurality" in this application means two or more. In the description of this application, "/" indicates an inclusive meaning, for example, A/B may indicate either A or B; "and/or" herein is only an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, for the convenience of clearly describing the technical solutions of the present application, the terms "first", "second", and the like are used to distinguish the same items or similar items having substantially the same functions and actions. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

The display panel provided in the embodiments of the present application is explained in detail below.

The first embodiment is as follows:

fig. 1 is a schematic longitudinal cross-sectional view of a display panel 10 according to an embodiment of the present disclosure. As shown in fig. 1, the display panel 10 includes an array substrate 12, a color filter substrate 14, and a liquid crystal layer 16. The array substrate 12 includes a first substrate 122, a plurality of pixel electrodes 128, and a plurality of first common electrodes 124. The color filter substrate 14 includes a second substrate 142 and a second common electrode 144.

Specifically, the first substrate 122 is used to carry other components of the array substrate 12, such as the plurality of pixel electrodes 128 and the plurality of first common electrodes 124. The first base substrate 122 is typically a transparent glass substrate. Generally, the plurality of pixel electrodes 128 and the plurality of first common electrodes 124 are located on the same surface of the first substrate 122. For convenience of description, in the embodiments of the present application, a first direction X, a second direction Y, and a third direction Z are defined. The first direction X and the second direction Y are both extending directions of the first substrate 122. That is, the first substrate base 122 extends in a plane in which the first direction X and the second direction Y are located. The third direction Z is a thickness direction of the first substrate 122. The first direction X, the second direction Y and the third direction Z are vertical to each other.

The first common electrode 124 is the common electrode of the array substrate. The plurality of pixel electrodes 128 and the plurality of first common electrodes 124 are located on the first substrate 122. Generally, the number of the pixel electrodes 128 in the array substrate 12 is equal to the number of the first common electrodes 124. In this case, each first common electrode 124 and each pixel electrode 128 may be located as shown in fig. 1, that is, one first common electrode 124 and one pixel electrode 128 are located at corresponding positions, and an insulating layer 126 is disposed between each first common electrode 124 and the corresponding pixel electrode 128, so that each first common electrode 124 and the corresponding pixel electrode 128 are coupled to form a storage capacitor. During operation of the display panel 10, each of the plurality of pixel electrodes 128 is used for inputting a voltage. The storage capacitor formed by coupling the first common electrode 124 and the corresponding pixel electrode 128 can be used to maintain the voltage on the pixel electrode 128 constant.

The color film substrate 14 and the array substrate 12 are arranged in a box-to-box manner. The color filter substrate 14 includes a second substrate 142 and a second common electrode 144 located on one surface of the second substrate 142. The second common electrode 144 is a color filter substrate common electrode. After the color filter substrate 14 and the array substrate 12 are set in an opposite manner, as shown in fig. 1, the plurality of pixel electrodes 128, the plurality of first common electrodes 124, and the second common electrode 144 are all located between the first substrate 122 and the second substrate 142. At this time, the second common electrode 144 is coupled with each of the plurality of pixel electrodes 128 to form a liquid crystal capacitance.

The liquid crystal layer 16 is located between the color filter substrate 14 and the array substrate 12. The liquid crystal layer 16 may include a plurality of liquid crystal cells each of which is positioned between one of the pixel electrodes 128 and the second common electrode 144. In this way, when a voltage difference exists between the pixel electrode 128 and the second common electrode 144, the liquid crystal cell located between the pixel electrode 128 and the second common electrode 144 rotates under the action of the liquid crystal capacitor, so that the display panel 10 achieves a display effect.

Generally, when the display panel 10 operates, the plurality of first common electrodes 124 and the second common electrodes 144 are used for inputting a voltage, and the voltage inputted by the plurality of first common electrodes 124 and the voltage inputted by the second common electrodes 144 should be equal and constant, so as to ensure the display effect of the display panel 10. For this reason, in the embodiment of the present application, the display panel 10 further includes the processor 18, the detection line 150, and the common signal line 130.

Fig. 2 is a schematic diagram of a frame structure of a display panel 10 according to an embodiment of the present disclosure. As shown in fig. 2, the processor 18 has an output terminal a and a sensing terminal b. The output end a of the processor 18 is used for outputting an electrical signal, and the detection end b of the processor 18 is used for detecting a voltage. The processor 18 may be a data driver, or may be a Chip On Film (COF) that binds the flexible circuit board and the data driver together. The sensing line 150 and the common signal line 130 are metal conductive lines. The common signal line 130 is connected between the output terminal a of the processor 18 and the common electrode 102 (including at least one of the first common electrode 124 and the second common electrode 144), so that an electrical signal output from the output terminal a of the processor 18 can be output to the common electrode 102 through the common signal line 130. The first end of the detection line 150 is connected to the detection end b of the processor 18, and the second end of the detection line 150 is connected to the common signal line 130, so that the processor 18 can detect the voltage of the common signal line 130 through the detection end b and the detection line 150. That is, the detection line 150 and the detection terminal b form a detection channel through which the voltage of the common signal line 130 can be detected.

The duration of the operation of the processor 18 may be divided into a plurality of cyclical duty cycles, each duty cycle comprising a first period of time and a second period of time. Wherein the second period is subsequent to the first period, and the start time of the second period may be an end time of the first period. In each duty cycle, the processor 18 is configured to perform the following steps S110 and S120.

S110, in the first period, the processor 18 outputs a preset electrical signal through the output terminal a and detects the voltage of the common signal line 130 through the detection terminal b.

The voltage of the preset electrical signal may be a rated voltage value of the first and second

common electrodes

124 and 144 in the display panel 10. For example, if the voltage inputted to the plurality of first and second

common electrodes

124 and 144 should be 3V (volts) when the display panel 10 is in operation, that is, the rated voltage value of the first and second

common electrodes

124 and 144 is 3V, the voltage of the first voltage signal may be 3V. In this case, the output terminal a of the processor 18 outputs an electrical signal of 3V, and the voltage is detected through the sensing terminal b.

And S120, in the second period, the processor 18 outputs the compensation electric signal through the output terminal a according to the voltage of the common signal line 130.

When the processor 18 executes step S110, the voltage can be detected through the detection terminal b, and the detected voltage is the voltage of the common signal line 130. In this way, when the processor 18 executes step S120, the compensation electrical signal can be output through the output terminal a according to the voltage of the common signal line 130 detected in step S110. The principle of the processor 18 outputting the compensated electrical signal is: when the voltage of the common signal line 130 is less than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is greater than the voltage of the preset electrical signal; when the voltage of the common signal line 130 is greater than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is less than the voltage of the preset electrical signal. For example, if the voltage of the preset electrical signal is 3V and the voltage of the common signal line 130 detected in step S110 is 2.8V, the voltage of the compensation electrical signal may be 3.2V or 3.5V. If the voltage of the preset electrical signal is 3V and the voltage of the common signal line 130 detected in step S110 is 3.3V, the voltage of the compensation electrical signal may be 2.6V or 2.7V. Thus, the voltage variation of the common electrode 102 connected to the common signal line 130 can be compensated. That is, in step S120, when the output terminal a outputs the compensation electrical signal, the output terminal and the common signal line may form a compensation channel, and the compensation channel is used for compensating the voltage of the common signal line.

In some specific embodiments, the difference between the voltage of the compensation electrical signal and the voltage of the preset electrical signal is equal to the difference between the voltage of the preset electrical signal and the voltage of the common signal line 130. That is, in this case, if the voltage of the preset electric signal is 3V and the voltage of the common signal line 130 detected in step S110 is 2.8V, the voltage of the compensation electric signal is 3.2V. If the voltage of the preset electrical signal is 3V and the voltage of the common signal line 130 detected in step S110 is 3.3V, the voltage of the compensation electrical signal is 2.7V.

In the embodiment of the present application, when the display panel 10 is in operation, the processor 18 may output the preset electrical signal to the common signal line 130 in the first period, so as to output the preset electrical signal to the common electrode 102. Meanwhile, the processor 18 can detect the voltage of the common signal line 130 through the detection line 150, so as to detect the voltage variation of the common electrode 102. The processor 18 may output the compensation electrical signal to the common signal line 130 in the second period, and when the voltage of the common signal line 130 is less than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is greater than the voltage of the preset electrical signal; when the voltage of the common signal line 130 is greater than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is less than the voltage of the preset electrical signal. In this way, compensation for voltage variation of the common electrode 102 can be achieved. The display panel 10 can detect and compensate voltage changes of the array substrate common electrode and the color film substrate common electrode, so that the problem of horizontal crosstalk of the display panel 10 can be solved, and the display effect of the display panel 10 is improved.

Example two:

first, the positions of the plurality of pixel electrodes 128 and the plurality of first common electrodes 124 on the first substrate 122 will be explained. Fig. 3 is a schematic diagram illustrating positions of a plurality of pixel electrodes 128 on the first substrate 122 according to a second embodiment of the present disclosure. As shown in fig. 3, the first substrate 122 includes a first area 1222 and a second area 1224 surrounding the first area 1222 in the extending direction of the first substrate 122, i.e., in the plane direction of the first direction X and the second direction Y (the dotted line in the figure is the boundary line of the first area 1222 and the second area 1224). When the array substrate 12 and the color filter substrate 14 are paired to form the display panel 10, the first region 1222 of the first substrate 122 corresponds to a display region (light-emitting region) of the display panel 10, and the second region 1224 of the first substrate 122 corresponds to a non-display region of the display panel 10. A plurality of pixel electrodes 128 are each located in the first region 1222. Generally, the plurality of pixel electrodes 128 are arranged in an array of rows and columns in the first region 1222. Fig. 4 is a schematic top view of the array substrate 12 according to the second embodiment of the present disclosure, in which a plurality of pixel electrodes 128 are not shown. As shown in fig. 4, corresponding to the positions of the plurality of pixel electrodes 128 on the first substrate 122 shown in fig. 3, the plurality of first common electrodes 124 are also located in the first region 1222 and are arranged in an array of rows and columns, so that each first common electrode 124 can be coupled with a corresponding pixel electrode 128 to form a storage capacitor.

Next, the display panel 10 provided in the second embodiment of the present application will be further described:

as previously described, the common electrode 102 may include a plurality of first and second

common electrodes

124 and 144. Based on this, the common signal line 130 may also include a first signal line 132 and a second signal line 134, and the output terminal a of the processor 18 may also include a first port a1 and a second port a2.

As shown in fig. 4, the first port a1 and the second port a2 are each for outputting an electrical signal. The first signal line 132 and the second signal line 134 are both metal wires, and the first signal line 132 and the second signal line 134 are both located on the first substrate 122. The first signal line 132 is connected between the first port a1 and the plurality of first common electrodes 124, so that when the first port a1 of the processor 18 outputs an electrical signal, the electrical signal can be transmitted to the plurality of first common electrodes 124 through the first signal line 132. Generally, as shown in fig. 4, the plurality of first common electrodes 124 may be connected to each other through a metal connection line 123, and connected to the first signal line 132 through the connection line 123. The second signal line 134 is connected between the second port a2 and the second common electrode 144, so that when the second port a2 of the processor 18 outputs an electrical signal, the electrical signal can be transmitted to the second common electrode 144 through the second signal line 134. Fig. 5 is a schematic longitudinal cross-sectional structure diagram of a display panel 10 according to a second embodiment of the present application, in which a liquid crystal layer 16 is not shown. In general, as shown in fig. 4 and 5, the second signal line 134 extending on the first substrate board 122 may be connected to the second common electrode 144 through the first metal ball 160 to enable electrical signal transmission between the second signal line 134 and the second common electrode 144.

The detection line 150 is also located on the first substrate 122, and the detection line 150, the first signal line 132 and the second signal line 134 are all located in the second region 1224 of the first substrate 122. In the embodiment of the present application, as shown in fig. 4, orthographic projections of the first signal lines 132, the second signal lines 134 and the detection lines 150 on the first substrate 122 do not intersect with each other. The orthographic projection of the first signal line 132 (or the second signal line 134, the detection line 150) on the first substrate 122 refers to a projection of the first signal line 132 (or the second signal line 134, the detection line 150) on the first substrate 122 along a direction perpendicular to the extending direction of the first substrate 122, that is, a projection of the first signal line 132 (or the second signal line 134, the detection line 150) on the first substrate 122 along the third direction Z. In the embodiment of the present application, orthographic projections of the first signal line 132, the second signal line 134 and the detection line 150 on the first substrate 122 are not intersected with each other, so that any two of the parasitic first signal line 132, the parasitic second signal line 134 and the detection line 150 can be prevented from being intersected to generate a parasitic capacitance.

In this embodiment, the first end of the detection line 150 is connected to the detection end b, and the second end of the detection line 150 can be connected to any one of the first signal line 132 and the second signal line 134. When the second end of the detection line 150 is connected to the first signal line 132, the detection line 150 and the detection end b are said to form a first detection channel. The first detection channel is used for detecting the voltage of the first signal line 132. When the second end of the detection line 150 is connected to the second signal line 134, the detection line 150 and the detection end b are called to form a second detection channel. The second detection channel is used for detecting the voltage of the second signal line 134.

The structure of the display panel 10 will be explained in detail below from two different cases, i.e., the first detection channel is formed by the detection line 150 and the detection terminal b, and the second detection channel is formed by the detection line 150 and the detection terminal b.

In the first case, the detection line 150 and the detection terminal b form a first detection channel.

As described above, the sensing lines 150 and the first signal lines 132 are located in the second region 1224 of the first substrate 122, so that the sensing lines 150 and the first signal lines 132 can be directly connected to form the structure shown in fig. 4.

In some specific embodiments, when the first port a1 outputs an electrical signal to the plurality of first common electrodes 124 through the first signal line 132, for the plurality of first common electrodes 124, the first common electrode 124 farther from the first port a1 has poorer voltage stability, i.e., the voltage changes more. Therefore, in this embodiment, as shown in fig. 4, the plurality of first common electrodes 124 are arranged in an array of rows and columns within the first region 1222 of the first substrate base 122. Two adjacent first common electrodes 124 of each row are connected by a connection line 123, and the first common electrodes 124 of each row are connected to the first signal line 132 by the connection line 123. In this case, the first port a1 may be located at one side of the plurality of first common electrodes 124 arranged in a plurality of rows, and the second end of the sensing line 150 is located at the other side of the plurality of first common electrodes 124 arranged in a plurality of rows on the first substrate 122. That is, the first port a1 and the second end of the sensing line 150 are located at opposite sides of the plurality of first common electrodes 124 arranged in a plurality of rows. For example, in the embodiment shown in fig. 4, the first port a1 is located above the plurality of first common electrodes 124 (in the paper surface direction), and the second end of the sensing line 150 is located below the plurality of first common electrodes 124 (in the paper surface direction). In this way, the detecting terminal b of the processor 18 can detect the voltage variation of the first common electrode 124 with the largest voltage variation, and compensate the voltage variation of the common electrode 102 according to the detection result, so as to improve the compensation effect of the voltage variation of the common electrode 102 and the display effect of the display panel 10.

In the second case, the detection line 150 and the detection terminal b form a second detection channel.

Fig. 6 is a schematic top view of another array substrate 12 according to the second embodiment of the present disclosure, in which a plurality of pixel electrodes 128 are not shown. Fig. 7 is a schematic longitudinal cross-sectional structure diagram of another display panel 10 according to the second embodiment of the present application, in which the liquid crystal layer 16 is not shown. As shown in fig. 6 and 7, the second signal line 134 and the detection line 150 are located in the second region 1224 of the first substrate 122 and extend on the first substrate 122. The second signal line 134 extending on the first substrate 122 is connected to the second port a2 and may be connected to the second common electrode 144 through the first metal ball 160, so that the second port a2 may transmit an electrical signal to the second common electrode 144 through the second signal line 134 and the first metal ball 160. The detection line 150 extending on the first substrate 122 may be connected to the second common electrode 144 through the second metal ball 170, so as to realize the electrical signal transmission between the detection line 150 and the second signal line 134. That is, in this embodiment, the sensing line 150 is connected to the second signal line 134 through the second metal ball 170, the second common electrode 144 and the first metal ball 160.

In some specific embodiments, when the second port a2 transmits an electrical signal to the second common electrode 144 through the second signal line 134 and the first metal ball 160, the voltage stability of the second common electrode 144 is worse, that is, the voltage variation is larger, at a position farther from the second port a2. Therefore, in this embodiment, as shown in fig. 6, the plurality of first common electrodes 124 are arranged in an array of rows and columns within the first region 1222 of the first substrate base 122. Two adjacent first common electrodes 124 of each row are connected by a connection line 123, and the first common electrodes 124 of each row are connected to the first signal line 132 by the connection line 123. In this case, the second port a2 may be positioned at one side of the plurality of first common electrodes 124 arranged in a plurality of rows and the second metal balls 170 may be positioned at the other side of the plurality of first common electrodes 124 arranged in a plurality of rows on the first substrate base 122. That is, the second port a2 and the second metal balls 170 are located at opposite sides of the plurality of first common electrodes 124 arranged in a plurality of rows. For example, in the embodiment shown in fig. 6, the second port a2 is located above the plurality of first common electrodes 124 (in the paper surface direction), and the second metal balls 170 are located below the plurality of first common electrodes 124 (in the paper surface direction). In this way, the detecting terminal b of the processor 18 can detect the voltage variation at the position where the voltage variation of the second common electrode 144 is large, and compensate the voltage variation of the common electrode 102 according to the detection result, so as to improve the compensation effect of the voltage variation of the common electrode 102 and the display effect of the display panel 10.

In other embodiments, fig. 8 is a schematic top view of another array substrate 12 provided in the second embodiment of the present application. As shown in fig. 8, the detecting lines 150 extending on the first substrate 122 can also be directly connected to the second signal lines 134. And will not be described in detail.

The following explains the operation of the processor 18 in detail from two different cases, namely, the first detection channel formed by the detection line 150 and the detection terminal b, and the second detection channel formed by the detection line 150 and the detection terminal b.

Step S110 may specifically be: during the first period, the processor 18 outputs a predetermined electrical signal through the first port a1 and the second port a2, and detects the voltage of the first signal line 132 through the detection terminal b. Step S120 may specifically be: during the second period, the processor 18 outputs the compensation electrical signal through the first port a1 or/and the second port a2 according to the voltage of the first signal line 132.

That is, in the first period, the first port a1 and the second port a2 each output a preset electric signal. At this time, since the second end of the detection line 150 is connected to the first signal line 132, the detection end b can only detect the voltage of the first signal line 132. During the second period, the processor 18 may output the compensation electrical signal to the first signal line 132 only through the first port a1 (i.e., compensate only the voltage variation of the plurality of first common electrodes 124, in which case the second port a2 still outputs the preset electrical signal during the second period); it is also possible to output the compensation electrical signal to the second signal line 134 only through the second port a2 (i.e., compensate only the voltage variation of the second common electrode 144, in which case the first port a1 still outputs the preset electrical signal during the second period); it is also possible to simultaneously output the compensation electrical signal to the first signal line 132 through the first port a1 and output the compensation electrical signal to the second signal line 134 through the second port a2 (i.e., simultaneously compensate for voltage variations of the plurality of first and second common electrodes 124 and 144). The voltage of the compensation electrical signal output by the first port a1 or/and the second port a2 of the processor 18 is obtained according to the voltage of the first signal line 132 detected by the detecting terminal b, and is not described again.

Step S110 may specifically be: during the first period, the processor 18 outputs a preset electrical signal through the first port a1 and the second port a2, and detects the voltage of the second signal line 134 through the detection terminal b. Step S120 may specifically be: during the second period, the processor 18 outputs the compensation electrical signal through the first port a1 or/and the second port a2 according to the voltage of the second signal line 134.

That is, in the first period, the first port a1 and the second port a2 each output a preset electric signal. At this time, since the second end of the detection line 150 is connected to the second signal line 134, the detection end b can only detect the voltage of the second signal line 134. During the second period, the processor 18 may output the compensation electrical signal to the first signal line 132 only through the first port a1 (i.e., compensate only the voltage variation of the plurality of first common electrodes 124, in which case the second port a2 still outputs the preset electrical signal during the second period); it is also possible to output the compensation electrical signal to the second signal line 134 only through the second port a2 (i.e., compensate only the voltage variation of the second common electrode 144, in which case the first port a1 still outputs the preset electrical signal during the second period); it is also possible to simultaneously output the compensation electrical signal to the first signal line 132 through the first port a1 and output the compensation electrical signal to the second signal line 134 through the second port a2 (i.e., simultaneously compensate for voltage variations of the plurality of first and second common electrodes 124 and 144). The voltage of the compensation electrical signal output by the first port a1 or/and the second port a2 of the processor 18 is obtained according to the voltage of the second signal line 134 detected by the detecting terminal b, and is not described again.

In the two different cases, the first port a1 outputs the compensation electrical signal, i.e., the first port a1 and the first signal line 132 form a first compensation channel. The first compensation channel is used for compensating the voltage of the first signal line 132. The second port a2 outputs the compensation electrical signal, that is, the second port a2 and the second signal line 134 form a second compensation channel. The second compensation channel is used for compensating the voltage of the second signal line 134. In the embodiments of the present application, only one of the first compensation channel and the second compensation channel may be present, or both of them may be present.

Example three:

the following explains in detail the implementation of "the orthographic projections of the first signal line 132, the second signal line 134 and the detection line 150 on the first substrate 122 do not intersect with each other" from three different embodiments.

In a first embodiment, fig. 9 to 11 are schematic top-view structural diagrams of various array substrates 12 provided in a third embodiment of the present application. As shown in fig. 9 to 11, each of the first port a1, the second port a2 and the detection terminal b is a single port. In the second direction Y, the processor 18 is located above the first substrate base plate 122. In (the opposite direction to) the first direction X, the processor 18 is connected to a portion of the second area 1224 located to the left of the first area 1222. That is, the first port a1, the second port a2, and the sensing terminal b are located at the left and upper sides of the first region 1222 of the first substrate 122. In this case, the detection terminal b may be located between the first port a1 and the second port a2, and the first port a1 is located on a side of the detection terminal b close to the first region 1222.

In this embodiment, the first signal lines 132 may extend in the second direction Y (the column direction in the paper direction). As shown in fig. 9, if the second end of the detection line 150 is connected to the first signal line 132, the detection line 150 may include a first portion 152 extending along the second direction Y and a second portion 154 not extending along the second direction Y. Wherein, the first end of the first portion 152 of the detection line 150 is connected to the detection end b. The first and second ends of the first portion 152 of the sensing line 150 are located at opposite sides of the plurality of first common electrodes 124 arranged in a plurality of rows. The second portion 154 of the detection line 150 is connected between the second end of the first portion 152 of the detection line 150 and the end of the first signal line 132 away from the first port a 1.

As shown in fig. 10 and 11, the second signal line 134 may include a third portion 1342 and a fourth portion 1344. The third portion 1342 extends along the second direction Y, and the fourth portion 1344 extends along the first direction X. A first end of the third portion 1342 is connected to the second port a2. The first and second ends of the third portion 1342 are positioned at opposite sides of the plurality of first common electrodes 124 arranged in a plurality of rows. An end of the fourth portion 1344 adjacent to the third portion 1342 is connected to a second end of the third portion 1342. If the second end of the detection line 150 is connected to the second signal line 134, the detection line 150 may extend along the second direction Y, and the first end and the second end of the detection line 150 are located at two opposite sides of the plurality of first common electrodes 124 arranged in a plurality of rows. The length of the detection line 150 is less than or equal to the length of the third portion 1342. When the length of the detection line 150 is less than the length of the third portion 1342, as shown in fig. 9, the second end of the detection line 150 may be connected to the second common electrode 144 through the second metal ball 170. When the length of the detection line 150 is equal to the length of the third portion 1342, as shown in fig. 11, the second end of the detection line 150 can be directly connected to the fourth portion 1344.

In a second embodiment, fig. 12 and 13 are schematic top-view structural diagrams of two different array substrates 12 provided in the third embodiment of the present application. As shown in fig. 12 and 13, the first port a1 includes a first sub-port a11 and a second sub-port a12. The second port a2 includes a third sub-port a21 and a fourth sub-port a22. The detecting terminal b is only one port.

In this embodiment, a first end of the first signal line 132 is connected to the first sub-port a11, and a second end of the first signal line 132 is connected to the second sub-port a12, that is, the first signal line 132 is connected between the first sub-port a11 and the second sub-port a12. The first signal line 132 surrounds the first region 1222. A first end of the second signal line 134 is connected to the third sub-port a21, and a second end of the second signal line 134 is connected to the fourth sub-port a22, that is, the second signal line 134 is connected between the third sub-port a21 and the fourth sub-port a22. The detection terminal b is located at a side of the first sub-port a11 away from the second sub-port a12 (as shown in fig. 12), or the detection terminal b is located at a side of the second sub-port a12 away from the first sub-port a11 (as shown in fig. 13); and the sense terminal b, the first sub-port a11 and the second sub-port a12 are all located between the third sub-port a21 and the fourth sub-port a22. That is, the first and second sub-ports a11 and a12 are located between the third and fourth sub-ports a21 and a22, wherein the third sub-port a21 is adjacent to the first sub-port a 11. The detecting terminal b may be located between the adjacent third sub-port a21 and the first sub-port a11 (as shown in fig. 12), or may be located between the second sub-port a12 and the fourth sub-port a22 (as shown in fig. 13). Thus, the detection line 150 and the first signal line 132 are both located within the surrounding range of the second signal line 134, and the detection line 150 is located outside the surrounding range of the first signal line 132, so that the orthographic projections of the first signal line 132, the second signal line 134 and the detection line 150 on the first substrate 122 are not intersected with each other.

In a third embodiment, fig. 14 and fig. 15 are schematic top view structural diagrams of two different array substrates 12 provided in the third embodiment of the present application. As shown in fig. 14 and 15, the first port a1 includes a first sub-port a11 and a second sub-port a12. The second port a2 includes a third sub-port a21 and a fourth sub-port a22. The detection terminal b includes a first detection port b1 and a second detection port b2, and the detection line 150 includes a first detection signal line 1502 and a second detection signal line 1504.

In this embodiment, a first end of the first signal line 132 is connected to the first sub-port a11, and a second end of the first signal line 132 is connected to the second sub-port a12, that is, the first signal line 132 is connected between the first sub-port a11 and the second sub-port a12. The first signal line 132 surrounds the first region 1222. A first end of the second signal line 134 is connected to the third sub-port a21, and a second end of the second signal line 134 is connected to the fourth sub-port a22, that is, the second signal line 134 is connected between the third sub-port a21 and the fourth sub-port a22. The first sub-port a11 and the second sub-port a12 are located between the first detection port b1 and the second detection port b2, and the first sub-port a11, the second sub-port a12, the first detection port b1 and the second detection port b2 are located between the third sub-port a21 and the fourth sub-port a22. In this case, the third sub-port a21, the first detection port b1, the first sub-port a11, the second sub-port a12, the second detection port b2, and the fourth sub-port a22 may be sequentially arranged along the first direction X (as shown in fig. 14).

A first end of the first detection signal line 1502 is connected to the first detection port b1, and a first end of the second detection signal line 1504 is connected to the second detection port b 2. As an example, a second end of the first detecting signal line 1502 and a second end of the second detecting signal line 1504 are connected to the first signal line 132, as shown in fig. 14. As another example, one of the second end of the first detection signal line 1502 and the second end of the second detection signal line 1504 is connected to the first signal line 132, and the other is connected to the second common electrode 144 via the second metal ball 170, so as to be connected to the second signal line 134, as shown in fig. 15. As another example, the second end of the first detecting signal line 1502 and the second end of the second detecting signal line 1504 are both connected to the second signal line 134. Thus, the first detection signal line 1502, the second detection signal line 1504, and the first signal line 132 are all located within the surrounding range of the second signal line 134, and the first detection signal line 1502 and the second detection signal line 1504 are all located outside the surrounding range of the first signal line 132, so that the orthographic projections of the first signal line 132, the second signal line 134, the first detection signal line 1502, and the second detection signal line 1504 on the first substrate 122 are not intersected with each other.

In the third embodiment, since the detection terminal b includes the first detection port b1 and the second detection port b2, the processor 18 can detect the voltage through the first detection port b1 and also can detect the voltage through the second detection port b 2. Therefore, the "detecting the voltage of the common signal line 130 through the detection terminal b" in the step S110 executed by the processor 18 may be that the processor 18 detects the voltage through the first detection port b1 only, or that the processor 18 detects the voltage through the second detection port b2 only. In some specific embodiments, when the processor 18 executes the "detecting the voltage of the common signal line 130 through the detecting terminal b" in step S110, it may further be:

the processor 18 detects a voltage through the first detection port b1 (hereinafter, the voltage detected by the first detection port b1 is referred to as a first voltage), and detects a voltage through the second detection port b2 (hereinafter, the voltage detected by the second detection port b2 is referred to as a second voltage); the processor 18 takes the average of the first voltage and the second voltage as the voltage of the common signal line 130. That is, in the embodiment of the present application, only one or both of the first detection channel and the second detection channel may exist.

Specifically, during the first period, the processor 18 detects the voltage of the common signal line 130 (one of the first signal line 132 and the second signal line 134) to which the first detection signal line 1502 is connected through the first detection port b1, and for convenience of description, the voltage detected by the first detection port b1 is referred to as a first voltage. During the first period, the processor 18 also detects the voltage of the common signal line 130 (one of the first signal line 132 and the second signal line 134) connected to the second detection signal line 1504 through the second detection port b2, and for convenience of description, the voltage detected by the second detection port b2 is referred to as a second voltage. After that, the processor 18 may calculate an average value of the first voltage and the second voltage as "the voltage of the common signal line 130" described in step S110.

Fig. 16 and 17 are schematic top-view structural diagrams of two different array substrates 12 according to the third embodiment of the present application. In the embodiment shown in fig. 16 and 17, the processor 18 is a flip-chip film that binds the flexible wiring board 182 and the data driver 184 together. In the embodiment shown in fig. 16, the first detection signal line 1502 and the second detection signal line 1504 are connected to the first signal line 132, and in the embodiment shown in fig. 17, the first detection signal line 1502 and the second detection signal line 1504 are connected to the second signal line 134.

As shown in fig. 16 and 17, in the embodiment of the present application, the display panel 10 may include a plurality of second signal lines 134. Each of the plurality of second signal lines 134 is adapted to be connected to the second common electrode 144 through a first metal ball (not shown) to transmit an electrical signal to the second common electrode 144. The orthographic projection of any second signal line 134 on the first substrate 122 does not intersect the orthographic projection of other second signal lines 134 on the first substrate 122, and the orthographic projection of any second signal line 134 on the first substrate 122 does not intersect the orthographic projection of the first signal line 132, the first detection signal line 1502 and the second detection signal line 1504 on the substrate.

In some specific embodiments, as shown in fig. 17, the display panel 10 includes a plurality of second signal lines 134 therein. The plurality of second signal lines 134 include second signal lines 134 surrounding the first region 1222 of the first substrate 122, and second signal lines 134 located above the first region 1222 in the third direction Y. The port connected to each second signal line 134 is a sub-port of the second port a2 (not shown), and the sub-ports connected to different second signal lines 134 may be different. For example, the ports to which the second signal lines 134 surrounding the first region 1222 of the first substrate 122 are connected are still the third sub-port a21 and the fourth sub-port a22 (not shown in the drawings).

In this case, the second compensation channel formed by the second port a2 and the second signal line 134 may include a first sub-channel and a second sub-channel. Wherein the first sub-channel refers to a compensation channel formed by the second signal line 134 surrounding the first region 1222 of the first substrate base plate 122 and the connected sub-port. The second sub-channel refers to a compensation channel formed by the second signal line 134 located above the first region 1222 in the third direction Y and the connected sub-port. In the embodiment of the present application, only any one of the first compensation channel, the first sub-channel, and the second sub-channel may be present, or a plurality of the first compensation channel, the first sub-channel, and the second sub-channel may be present.

Example four:

the embodiment of the present application further provides a display device, which includes the display panel 10 and the backlight source in any of the above embodiments. Fig. 18 is a schematic longitudinal sectional structure diagram of a display device according to a fourth embodiment of the present application. As shown in fig. 18, the display panel 10 is located on the light-emitting side of the backlight, so that the backlight can provide light sources for the display panel 10.

Specifically, the display panel 10 includes a plurality of pixel electrodes 128, a common electrode 102, a common signal line 130, and a processor 18. The plurality of pixel electrodes 128 are coupled to the common electrode 102 to form a capacitor. The processor 18 has an output terminal a, and the common signal line 130 is connected between the output terminal a and the common electrode 102. The display panel 10 further includes a detection line 150, and the processor 18 further has a detection terminal b, wherein a first end of the detection line 150 is connected to the detection terminal b, and a second end of the detection line 150 is connected to the common signal line 130, so that the detection line 150 and the detection terminal b form a detection channel for detecting a voltage of the common signal line 130.

The processor 18 is configured to: in the first period, a predetermined electrical signal is output through the output terminal a, and the voltage of the common signal line 130 is detected through the sensing terminal b. Outputting a compensation electric signal through the output terminal a according to the voltage of the common signal line 130 in a second period, so that the output terminal a and the common signal line 130 form a compensation channel for compensating the voltage of the common signal line 130; wherein, when the voltage of the common signal line 130 is less than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is greater than the voltage of the preset electrical signal, and the second period is after the first period.

In some embodiments, the common electrode 102 includes a plurality of first and second

common electrodes

124 and 144, the common signal line 130 includes first and

second signal lines

132 and 134, and the output terminal a includes first and second ports a1 and a2. One of the plurality of first common electrodes 124 is coupled to one of the plurality of pixel electrodes 128 to form a capacitor, and the second common electrode 144 is coupled to each of the plurality of pixel electrodes 128 to form a capacitor. The first signal line 132 is connected between the first port a1 and the plurality of first common electrodes 124, and the second signal line 134 is connected between the second port a2 and the second common electrode 144. The second end of the detection line 150 is connected to the first signal line 132 or the second signal line 134, so that the detection line 150 and the detection end b form a first detection channel for detecting the voltage of the first signal line 132 or a second detection channel for detecting the voltage of the second signal line 134.

The processor 18 is configured to: in the first period, a predetermined electrical signal is output through the first port a1 and the second port a2, and the voltage of the first signal line 132 or the second signal line 134 is detected through the sensing terminal b. In the second period, a compensation electrical signal is output through the first port a1 or/and the second port a2 according to the voltage of the first signal line 132 or the second signal line 134, so that the first port a1 and the first signal line 132 form a first compensation channel for compensating the voltage of the first signal line 132, or/and the second port a2 and the second signal line 134 form a second compensation channel for compensating the voltage of the second signal line 134.

In some embodiments, the display panel 10 includes an array substrate 12 and a color filter substrate 14 disposed in a box-to-box manner with the array substrate 12, and the color filter substrate 14 includes a second common electrode 144. The array substrate 12 includes a first substrate 122, and a plurality of pixel electrodes 128, a plurality of first common electrodes 124, a first signal line 132, a second signal line 134 and a detection line 150 on the first substrate 122. Along the extending direction of the first substrate 122, the first substrate 122 includes a first area 1222 and a second area 1224 surrounding the first area 1222, the plurality of pixel electrodes 128 and the plurality of first common electrodes 124 are located in the first area 1222, and the first signal line 132, the second signal line 134 and the detection line 150 are located in the second area 1224. Orthographic projections of the first signal line 132, the second signal line 134 and the detection line 150 on the first substrate 122 are not intersected with each other.

When the array substrate 12 and the color filter substrate 14 are set in a box-to-box manner to form the display panel 10, the first region 1222 of the first substrate 122 is a display region of the display panel 10, and the second region 1224 of the first substrate 122 is a non-display region of the display panel 10. Therefore, the backlight should provide light sources for at least the first area 1222 of the first substrate 122.

In some embodiments, the first signal line 132 is connected to the first port a1, and the second end of the detection line 150 is connected to the first signal line 132. The plurality of first common electrodes 124 are arranged in a plurality of rows, and the first signal line 132 is connected to each of the plurality of first common electrodes 124 arranged in a plurality of rows. On the first substrate 122, the first port a1 is located at one side of the plurality of first common electrodes 124 arranged in a plurality of rows, and the second end of the sensing line 150 is located at the other side of the plurality of first common electrodes 124 arranged in a plurality of rows.

In some embodiments, the second signal line 134 is connected to the second port a2, and the second signal line 134 is connected to the second common electrode 144 through the first metal ball 160. The second end of the sensing line 150 is connected to the second common electrode 144 through the second metal ball 170. The plurality of first common electrodes 124 are arranged in a plurality of rows, and the first signal line 132 is connected to each of the plurality of first common electrodes 124 arranged in a plurality of rows. On the first base substrate 122, the second port a2 is positioned at one side of the plurality of first common electrodes 124 arranged in a plurality of rows, and the second metal ball 170 is positioned at the other side of the plurality of first common electrodes 124 arranged in a plurality of rows.

In some embodiments, the first port a1 includes a first sub-port a11 and a second sub-port a12, a first end of the first signal line 132 is connected with the first sub-port a11, a second end of the first signal line 132 is connected with the second sub-port a12, and the first signal line 132 surrounds the first region 1222. The detecting terminal b is located at a side of the first sub-port a11 away from the second sub-port a12, or the detecting terminal b is located at a side of the second sub-port a12 away from the first sub-port a 11. The second port a2 includes a third sub-port a21 and a fourth sub-port a22, a first end of the second signal line 134 is connected to the third sub-port a21, a second end of the second signal line 134 is connected to the fourth sub-port a22, the sensing terminal b, the first sub-port a11 and the second sub-port a12 are all located between the third sub-port a21 and the fourth sub-port a22, and the sensing line 150 and the first signal line 132 are all located within a surrounding range of the second signal line 134.

In some embodiments, the detection terminal b includes a first detection port b1 and a second detection port b2, and the detection line 150 includes a first detection signal line 1502 and a second detection signal line 1504. The first port a1 includes a first sub-port a11 and a second sub-port a12, a first end of the first signal line 132 is connected to the first sub-port a11, a second end of the first signal line 132 is connected to the second sub-port a12, and the first signal line 132 surrounds the first region 1222. The first sub-port a11 and the second sub-port a12 are located between the first detection port b1 and the second detection port b2, a first end of the first detection signal line 1502 is connected to the first detection port b1, a first end of the second detection signal line 1504 is connected to the second detection port b2, and a second end of the first detection signal line 1502 and a second end of the second detection signal line 1504 are used for being connected to the first signal line 132 or the second signal line 134. The second port a2 includes a third sub-port a21 and a fourth sub-port a22, the first end of the second signal line 134 is connected to the third sub-port a21, the second end of the second signal line 134 is connected to the fourth sub-port a22, the first detection port b1, the second detection port b2, the first sub-port a11 and the second sub-port a12 are located between the third sub-port a21 and the fourth sub-port a22, and the first detection signal line 1502, the second detection signal line 1504 and the first signal line 132 are located within a surrounding range of the second signal line 134.

In some embodiments, the processor 18 is configured to: in the first period, the first voltage is detected through the first detection port b1, and the second voltage is detected through the second detection port b 2. The average value of the first voltage and the second voltage is taken as the voltage of the common signal line 130.

In some embodiments, the difference between the voltage of the compensation electrical signal and the voltage of the preset electrical signal is equal to the difference between the voltage of the preset electrical signal and the voltage of the common signal line 130.

In the embodiment of the present application, the display panel 10 includes a plurality of pixel electrodes 128, a common electrode 102 (including an array substrate common electrode and a color film substrate common electrode), a common signal line 130, a detection line 150, and a processor 18. The plurality of pixel electrodes 128 are coupled to the common electrode 102 to form a capacitor. The common signal line 130 is connected between the output terminal a of the processor 18 and the common electrode 102. The detection line 150 is connected between the detection terminal b of the processor 18 and the common signal line 130. In operation of the display panel 10, the processor 18 may output a preset electrical signal to the common signal line 130 during a first period of time, so as to output the preset electrical signal to the common electrode 102. Meanwhile, the processor 18 can detect the voltage of the common signal line 130 through the detection line 150, so as to detect the voltage variation of the common electrode 102. The processor 18 may output the compensation electrical signal to the common signal line 130 in the second period, and when the voltage of the common signal line 130 is less than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is greater than the voltage of the preset electrical signal. In this way, compensation for voltage variation of the common electrode 102 can be achieved. The display panel 10 can detect and compensate voltage changes of the array substrate common electrode and the color film substrate common electrode, so that the problem of horizontal crosstalk of the display panel 10 can be solved, and the display effect of the display panel 10 is improved.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A display panel, comprising: a plurality of pixel electrodes, a common electrode, a common signal line, and a processor;

the plurality of pixel electrodes are coupled with the common electrode to form a capacitor; the processor is provided with an output end, and the common signal line is connected between the output end and the common electrode;

the display panel is characterized by further comprising a detection line, the processor is further provided with a detection end, a first end of the detection line is connected with the detection end, and a second end of the detection line is connected with the common signal line, so that the detection line and the detection end form a detection channel for detecting the voltage of the common signal line;

the processor is configured to: in a first time period, outputting a preset electric signal through the output end, and detecting the voltage of the common signal line through the detection end; outputting a compensation electric signal through the output end according to the voltage of the common signal line in a second time period, so that the output end and the common signal line form a compensation channel for compensating the voltage of the common signal line; wherein when the voltage of the common signal line is less than the voltage of the preset electrical signal, the voltage of the compensation electrical signal is greater than the voltage of the preset electrical signal, and the second period is after the first period.

2. The display panel according to claim 1, wherein the common electrode includes a plurality of first and second common electrodes, the common signal line includes a first signal line and a second signal line, and the output terminal includes a first port and a second port;

3. The display panel according to claim 2, wherein the display panel comprises an array substrate and a color film substrate arranged in a box-to-box manner with the array substrate, and the color film substrate comprises the second common electrode;

the substrate base plate comprises a first area and a second area surrounding the first area along the extending direction of the substrate base plate, the pixel electrodes and the common electrodes are located in the first area, and the first signal lines, the second signal lines and the detecting lines are located in the second area; orthographic projections of the first signal line, the second signal line and the detection line on the substrate base plate are not intersected with each other.

4. The display panel according to claim 3, wherein the first signal line is connected to the first port, and a second end of the detection line is connected to the first signal line;

5. The display panel according to claim 3, wherein the second signal line is connected to the second port, and the second signal line is connected to the second common electrode through a first metal ball; the second end of the detection line is connected with the second common electrode through a second metal ball;

the plurality of first common electrodes are arranged in a plurality of rows, and the first signal line is connected to each of the plurality of first common electrodes arranged in the plurality of rows; on the substrate base plate, the second ports are positioned on one side of the first common electrodes arranged in a plurality of rows, and the second metal balls are positioned on the other side of the first common electrodes arranged in a plurality of rows.

6. The display panel according to claim 3, wherein the first port includes a first sub-port and a second sub-port, a first end of the first signal line is connected with the first sub-port, a second end of the first signal line is connected with the second sub-port, and the first signal line surrounds the first region;

the second port comprises a third sub-port and a fourth sub-port, the first end of the second signal line is connected with the third sub-port, the second end of the second signal line is connected with the fourth sub-port, the detecting end, the first sub-port and the second sub-port are all located between the third sub-port and the fourth sub-port, and the detecting line and the first signal line are all located in the surrounding range of the second signal line.

7. The display panel according to claim 3, wherein the detection terminal includes a first detection port and a second detection port, and the detection line includes a first detection signal line and a second detection signal line;

8. The display panel of claim 7, wherein the processor is to: detecting a first voltage through the first detection port and a second voltage through the second detection port in a first period; an average value of the first voltage and the second voltage is taken as a voltage of the common signal line.

9. The display panel according to any one of claims 1 to 8, wherein a difference between a voltage of the compensation electric signal and a voltage of the preset electric signal is equal to a difference between a voltage of the preset electric signal and a voltage of the common signal line.

10. A display device comprising the display panel according to any one of claims 1 to 9, and further comprising a backlight, wherein the display panel is located on a light exit side of the backlight, so that the backlight provides a light source for the display panel.