CN114787701B - Display substrate, display panel and display device - Google Patents
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- CN114787701B CN114787701B CN202080002011.7A CN202080002011A CN114787701B CN 114787701 B CN114787701 B CN 114787701B CN 202080002011 A CN202080002011 A CN 202080002011A CN 114787701 B CN114787701 B CN 114787701B
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- 239000000758 substrate Substances 0.000 title claims abstract description 96
- 239000010409 thin film Substances 0.000 claims abstract description 18
- 239000004973 liquid crystal related substance Substances 0.000 claims description 8
- 230000003071 parasitic effect Effects 0.000 abstract description 2
- 239000011159 matrix material Substances 0.000 description 10
- 230000005684 electric field Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 2
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- 230000008569 process Effects 0.000 description 2
- 241001270131 Agaricus moelleri Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- 239000000126 substance Substances 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Crystallography & Structural Chemistry (AREA)
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Abstract
A display substrate, a display panel and a display device, the display substrate includes: a first substrate, a plurality of gate lines (4) and a plurality of data lines (5) which are positioned on the first substrate, wherein the gate lines (4) extend along a first direction, and the data lines (5) extend along a second direction; the plurality of gate lines (4) and the plurality of data lines (5) define a plurality of pixel cells, the pixel cells including: the pixel structure comprises a thin film transistor (7), a pixel electrode (8) and a common electrode (9), wherein at least part of pixel units are provided with conductive bridge wires (10), and the conductive bridge wires (10) and the pixel electrode (8) are arranged on the same layer; in a pixel unit configured with a conductive bridge wire (10), a first hollow structure (13) is arranged at a first side of a first end part or a second end part of a pixel electrode (8), the end part of the conductive bridge wire (10) is positioned in the first hollow structure (13) and connected with a via hole of a common electrode (9), and a second hollow structure (14) is arranged at a second side of the first end part of the pixel electrode (8), so that the absolute value of the difference of parasitic capacitances formed by the pixel electrode (8) and the nearest data wires (5) positioned at two sides is smaller than or equal to a preset capacitance difference value.
Description
Technical Field
The disclosure relates to the field of display, and in particular relates to a display substrate, a display panel and a display device.
Background
Advanced super-Dimension Switch (Advanced) display mode has the advantages of wide viewing angle, high response speed, high transmittance and the like, becomes a popular display mode and is used in product design by a plurality of panel manufacturers. However, in practical applications, it is found that the picture displayed by the existing ADS type display device has a significant moire (mura).
Disclosure of Invention
The present disclosure aims to solve at least one of the technical problems in the prior art, and proposes a display substrate, a display panel and a display device.
In a first aspect, an embodiment of the present disclosure provides a display substrate, including: the display device comprises a first substrate, a plurality of grid lines and a plurality of data lines, wherein the grid lines and the data lines are arranged on the first substrate, the grid lines extend along a first direction, the data lines extend along a second direction, and the first direction and the second direction are crossed and are parallel to a plane where the first substrate is positioned;
the plurality of gate lines and the plurality of data lines define a plurality of pixel units, the pixel units including: the pixel electrodes are positioned on one side, far away from the first substrate, of the common electrode, the pixel electrodes and the region where the pixel electrodes are positioned in the same pixel unit are distributed along a second direction, one end, close to the thin film transistor, of each pixel electrode is a first end, one end, far away from the thin film transistor, of each pixel electrode is a second end, at least part of each pixel unit is provided with a conductive bridge wire, and the conductive bridge wires and the pixel electrodes are arranged on the same layer;
in the pixel unit configured with the conductive bridge wire, a first hollow structure is arranged on a first side of the first end part or the second end part of the pixel electrode, the end part of the conductive bridge wire is positioned in the first hollow structure and is connected with the common electrode via hole, and a second hollow structure is arranged on a second side of the first end part of the pixel electrode, so that the absolute value of the difference of lateral capacitance formed by the pixel electrode and the nearest data wire positioned on two sides is smaller than or equal to a preset capacitance difference value;
the first side and the second side are opposite sides of the pixel electrode in a first direction.
In some embodiments, the second hollowed-out structure and the first hollowed-out structure have equal lengths in the second direction.
In some embodiments, in the pixel unit configured with the conductive bridge line, a third hollowed structure is disposed on a second side of the second end portion of the pixel electrode, and the second hollowed structure and the third hollowed structure are configured such that an absolute value of a difference between lateral capacitances formed by the pixel electrode and the data lines located on two sides and closest to each other is smaller than or equal to a preset capacitance difference value.
In some embodiments, the sum of the lengths of the second hollow structure and the third hollow structure in the second direction is equal to the length of the first hollow structure in the second direction.
In some embodiments, the length of the third hollow structure in the first direction is less than or equal to the length of the first hollow structure in the first direction.
In some embodiments, the length of the second hollowed-out structure in the first direction is less than or equal to the length of the first hollowed-out structure in the first direction.
In some embodiments, the pixel electrode is equal to lateral capacitance formed by the data lines located at two sides and nearest to each other.
In some embodiments, in the pixel unit configured with the conductive bridge line, the pixel electrode has a first orthographic projection on the first substrate, the data line located at two sides of the pixel electrode and nearest to the pixel electrode has a second orthographic projection on the first substrate, and a space region is formed between the first orthographic projection and the second orthographic projection;
in the pixel unit provided with the conductive bridge line, the common electrode is a block-shaped common electrode, and the orthographic projection of the edge, close to the data line, of the block-shaped common electrode on the first substrate is located in the interval region.
In some embodiments, further comprising: the common electrode wire and the grid wire are arranged on the same layer;
the plurality of pixel units arranged along the first direction correspond to the same common electrode wire, the common electrode in the pixel units is electrically connected with the corresponding common electrode wire, and the orthographic projection of the second end part of the pixel electrode in the pixel units on the first substrate is overlapped with the orthographic projection of the corresponding common electrode wire on the first substrate.
In some embodiments, the drain of the thin film transistor is connected to the pixel electrode via;
when the first hollow structure is positioned at the first side of the first end part of the pixel electrode, a via hole for connecting the drain electrode with the pixel electrode is positioned between the first hollow structure and the second hollow structure.
In a second aspect, embodiments of the present disclosure further provide a display panel, including: the display substrate and the box-matching substrate are oppositely arranged, a liquid crystal layer is filled between the display substrate and the box-matching substrate, and the display substrate adopts the display substrate provided by the first aspect.
In a third aspect, an embodiment of the present disclosure further provides a display apparatus, including: the display panel and the light source as provided in the second aspect described above.
Drawings
FIG. 1 is a top view of a pixel cell configured with conductive bridge lines according to the related art;
FIG. 2 is another top view of a pixel cell configured with conductive bridge lines according to the related art;
fig. 3 is a schematic circuit structure diagram of a pixel unit in the present disclosure when a Z inversion arrangement mode is adopted;
FIG. 4 is a schematic circuit diagram of two pixel units located in the same column and adjacent rows in FIG. 3;
fig. 5 is a schematic top view of a display substrate according to an embodiment of the disclosure;
FIG. 6a is a top view of the pixel cell of FIG. 5 with conductive bridge lines disposed therein;
FIG. 6b is another top view of the pixel cell of FIG. 5 with conductive bridge lines disposed therein;
FIG. 7 is a schematic cross-sectional view taken in the direction A-A' of FIG. 6 a;
FIG. 8 is a schematic top view of another display substrate according to an embodiment of the disclosure;
FIG. 9a is a top view of the pixel cell of FIG. 8 with conductive bridge lines disposed therein;
fig. 9b is another top view of the pixel cell of fig. 8 configured with conductive bridge lines.
Detailed Description
In order to better understand the technical solutions of the present disclosure, a display substrate, a display panel and a display device provided by the present disclosure are described in detail below with reference to the accompanying drawings.
In order to solve the problem that the display device in the related art has obvious moire, the present disclosure analyzes the cause of moire in the related art, and provides a corresponding solution.
In order to avoid the problem of fatigue of liquid crystal caused by the constant deflection of liquid crystal molecules in a certain direction in a liquid crystal display device, a polarity inversion method is adopted in the display driving process, and common polarity inversion methods include: horizontal inversion, column inversion, and dot inversion.
In the ADS type display device, since the distance between the pixel electrode in the pixel unit and the data on both sides (generally, 3um to 5 um) is relatively short, a lateral capacitance (also referred to as a fringe capacitance) is formed between the pixel electrode and the data line on both sides and nearest to the pixel electrode. When the polarity of the data voltage loaded in the data line is reversed, the data voltage in the data line is greatly jumped, and the voltage loaded by the pixel electrode is changed through lateral capacitive coupling between the data line and the pixel electrode. In order to reduce the influence of polarity inversion of the data voltages in the data lines on the voltages applied to the pixel electrodes as much as possible, the polarities of the data voltages in the adjacent two data lines on the display panel are often set to be opposite. At this time, when the polarity of the data voltage in the nearest data line is inverted on both sides of any pixel unit, one data line jumps from positive polarity to negative polarity (the lateral capacitance between the data line and the pixel electrode pulls down the voltage applied to the pixel electrode), and the other data line jumps from negative polarity to positive polarity (the lateral capacitance between the data line and the pixel electrode pulls up the voltage applied to the pixel electrode), so as to balance the influence of the polarity inversion of the data voltage in the data line on the voltage applied to the pixel electrode.
Fig. 1 is a top view of a pixel unit provided with a conductive bridge line in the related art, and fig. 2 is another top view of a pixel unit provided with a conductive bridge line in the related art, as shown in fig. 1 and 2, generally, the pixel electrode 1 in the pixel unit has a parallelogram (e.g., a rectangle) overall; however, in the ADS row display panel, a part of the pixel units needs to be configured to accommodate the conductive bridge line 3 (electrically connected to the common electrode through the via hole), and the conductive bridge line 3 is disposed in the same layer as the pixel electrode 1; since the conductive bridge wire 3 occupies a part of the area on the pixel electrode 1, the pixel electrode 1 needs to be provided with a hollow structure 2 to accommodate the end of the conductive bridge wire 3. Fig. 1 exemplarily shows a case where the hollowed-out structure 2 for accommodating the end portion of the conductive bridge line 3 is located at the lower left corner of the pixel electrode 1, and fig. 2 exemplarily shows a case where the hollowed-out structure 2 for accommodating the end portion of the conductive bridge line 3 is located at the upper left corner of the pixel electrode 1.
With continued reference to fig. 1 and 2, the length of the first portion of the pixel electrode 1 capable of generating lateral capacitance with the left data line d_l is L1, the length of the second portion of the pixel electrode 1 capable of generating lateral capacitance with the right data line d_r is L2, the lateral capacitance between the first portion and the left data line d_l is cpd_l, the lateral capacitance between the second portion and the left data line d_l is cpd_r, and the difference between cpd_l < cpd_r, cpd_l and cpd_r is denoted as Δcpd, Δcpd= |cpd_l-cpd_r|. By practical measurement, L2-L1 > 20 micrometers (um), ΔCpd= |Cpd_L-Cpd_R| > 1.2 femtofarads (fF). Because the Δcpd value is large, even if the data lines on the left and right sides are simultaneously inverted in polarity, the voltage applied to the pixel electrode 1 will be changed greatly, and the brightness change of the pixel unit is greater than 2 gray scales, so that the user can obviously feel abnormal brightness.
Fig. 3 is a schematic circuit structure diagram of a pixel unit in the present disclosure in a Z inversion arrangement mode, as shown in fig. 3, taking a Z inversion arrangement mode as an example for the pixel unit in the display substrate; specifically, the pixel cells in the i-th row are connected to the i-th gate line G1/G2/G3/G4, each pixel cell in the odd-numbered row is connected to one data line located at the first side (left side of the pixel cell in the drawing) and closest thereto, and each pixel cell in the even-numbered row is connected to one data line located at the second side (right side of the pixel cell in the drawing) and closest thereto. When the pixel is driven, the column inversion mode is adopted for driving, namely, the polarities of the data voltages loaded in the adjacent data lines are opposite, so that the display panel can achieve the effect of dot inversion. Fig. 3 illustrates a case where the data voltages applied to the data lines D1, D3, D5, D7, D9 in the odd columns have positive polarity (+), and the data voltages applied to the data lines D2, D4, D6, D8 in the even columns have positive polarity (-).
Fig. 4 is a schematic circuit diagram of two pixel units located in the same column and adjacent rows in fig. 3, as shown in fig. 4, the voltage applied to the pixel electrode 1 in the pixel units located in M rows is positive, the voltage applied to the pixel electrode 1 in the pixel units located in m+1 rows is negative, the data voltage applied to the left data line d_l jumps from positive to negative, and the data voltage applied to the right data line d_r jumps from negative to positive.
When the polarity of the data voltage applied to the left data line d_l is inverted (from positive polarity to negative polarity), the voltage applied to the pixel electrode 1 is pulled down by Δvp_l by the coupling action of the lateral capacitance between the left data line d_l and the pixel electrode 1:
ΔVp_L＝Cpd_L*ΔVd_L/(Cpd_L+Cpd_R+Cst+Clc+Cgp)；
cpd_l represents a lateral capacitance formed between the pixel electrode 1 and the left data line d_l, cpd_r represents a lateral capacitance formed between the pixel electrode 1 and the right data line d_r, Δvd_l represents a voltage variation amount of polarity inversion of the data voltage in the left data line d_l (an absolute value of a difference between the data voltage after polarity inversion and the data voltage before polarity inversion), cst represents a storage capacitance between the pixel electrode 1 and the common electrode, clc represents a liquid crystal capacitance at the pixel cell, and Cst represents a lateral capacitance between the pixel electrode 1 and the gate line.
When the polarity of the data voltage applied to the right data line d_r is inverted (from negative polarity to positive polarity), the voltage applied to the pixel electrode 1 is pulled up by Δvp_r by the coupling action of the lateral capacitance between the left data line d_l and the pixel electrode 1:
ΔVp_R＝Cpd_R*ΔVd_R/(Cpd_L+Cpd_R+Cst+Clc+Cgp)
Δvd_r represents the voltage change amount (absolute value of the difference between the data voltage after polarity inversion and the data voltage before polarity inversion) of the polarity inversion of the data voltage in the right data line d_r.
For convenience of description, let Δvd_l=Δvd_r, then after polarity inversion of the data voltages in the data lines on the left and right sides, the voltage variation on the pixel electrode 1 is |Δvp_l- Δvp_r|:
|ΔVp_L-ΔVp_R|＝|Cpd_L-Cpd_R|*ΔVd_R/(Cpd_L+Cpd_R+Cst+Clc+Cgp)
taking the case shown in fig. 1 as an example of the pixel electrode 1, cpd_l < cpd_r, the voltage on the pixel electrode 1 is pulled up (cpd_r-cpd_l) by Δvd_r/(cpd_l+cpd_r+cst+clc+cgp). For the pixel units of M rows, the voltage of the positive polarity voltage applied to the pixel units rises, and the display brightness is increased; for the pixel units in M+1 rows, the voltage of the negative polarity voltage applied to the pixel units is reduced, and the display brightness is reduced; the difference in luminance between the pixel units in two adjacent rows is significant, lateral mura is generated, and the larger the value of |cpd_l-cpd_r| is, the more significant the difference in luminance is.
In order to solve the technical problem that in the related art, due to the fact that the hollowed-out structure for accommodating the conductive bridge wire is arranged on the pixel electrode, the difference of lateral capacitances formed by the pixel electrode and the data wires on the left side and the right side is large, and further the pixel unit is obviously abnormal in the display process, the embodiment of the disclosure provides a corresponding solution.
Fig. 5 is a schematic top view of a display substrate according to an embodiment of the disclosure, fig. 6a is a top view of a pixel unit with conductive bridge lines in fig. 5, fig. 6b is another top view of a pixel unit with conductive bridge lines in fig. 5, fig. 7 is a schematic cross-sectional view of A-A' in fig. 6a, and as shown in fig. 5 to 7, the display substrate is an ADS-type display substrate, and the display substrate includes: the first substrate 20, a plurality of gate lines 4 and a plurality of data lines 5 positioned on the first substrate 20, wherein the gate lines 4 extend along a first direction X, the data lines 5 extend along a second direction Y, and the first direction X and the second direction Y are crossed and are parallel to a plane where the first substrate 20 is positioned. In the embodiment of the present disclosure, an exemplary description is given taking the first direction X as a row direction and the second direction Y as a column direction as an example.
The plurality of gate lines 4 and the plurality of data lines 5 define a plurality of pixel units including: the pixel electrode 8 is a slit electrode and is positioned on one side, far away from the first substrate base plate 20, of the common electrode 9, the region where the pixel electrode 8 is positioned and the region where the thin film transistor 7 is positioned in the same pixel unit are distributed along the second direction Y, one end, close to the thin film transistor 7, of the pixel electrode 8 is a first end, one end, far away from the thin film transistor 7, of the pixel electrode 8 is a second end, at least part of the pixel units are provided with conducting bridge wires 10, and the conducting bridge wires 10 and the pixel electrode 8 are arranged on the same layer.
Wherein the thin film transistor 7 includes: a gate electrode, a source electrode 18, a drain electrode 16, and an active layer 17. Fig. 5 illustrates only an example in which the gate electrode of the thin film transistor 7 in each pixel unit is connected to the corresponding row gate line 4, and the source electrode 18 of the thin film transistor 7 in each pixel unit is connected to the nearest data line 5 on the right side thereof, which serves as an example only, without limiting the technical scheme of the present disclosure. Other arrangements of the pixel units in the disclosure may be adopted, for example, an arrangement adopting a Z-inversion arrangement.
In addition, it is only exemplarily shown in fig. 5 that 1 pixel cell is configured with the conductive bridge line 10 every 3 pixel cells, which serves only as an example, which does not limit the technical solution of the present disclosure. In practical applications, the conductive bridge line 10 may be disposed in each pixel unit, or the conductive bridge line 10 may be disposed in a part of the pixel units.
Referring to fig. 6a and 6b, in some embodiments, in a pixel unit configured with a conductive bridge line 10, a first hollowed structure 13 is disposed at a first side of a first end or a second end of a pixel electrode 8, the end of the conductive bridge line 10 is disposed in the first hollowed structure 13 and connected to a via hole of a common electrode 9, and a second hollowed structure 14 is disposed at a second side of the first end of the pixel electrode 8, so that an absolute value of a difference between lateral capacitances formed by the pixel electrode 8 and the data lines 5 disposed at two sides and closest to each other is less than or equal to a preset capacitance difference; the first side and the second side are opposite sides of the pixel electrode 8 in the first direction X.
Taking the case shown in fig. 5, 6a and 6b as an example, in any pixel unit, the thin film transistor 7 is located below the corresponding pixel electrode 8, the first end of the pixel electrode 8 is the lower end of the pixel electrode 8, and the second end of the pixel electrode 8 is the upper end of the pixel electrode 8; the first side is specifically referred to as the left side and the second side is specifically referred to as the right side.
Fig. 6a illustrates a case where the first end portion of the pixel electrode 8 is provided with the first hollow structure 13 (the first hollow structure 13 is located at the lower left corner of the pixel electrode 8), and fig. 6b illustrates a case where the second end portion of the pixel electrode 8 is provided with the first hollow structure 13 (the first hollow structure 13 is located at the upper left corner of the pixel electrode 8). In fig. 6a and 6b, the second hollowed-out structure 14 is located at the right side of the lower end portion of the pixel electrode 8. It should be noted that the cases shown in fig. 6a and fig. 6b serve as examples, and do not limit the technical solutions of the present disclosure.
In some embodiments, the second hollowed-out structures 14 are equal to the first hollowed-out structures 13 in length in the second direction Y. By this design it is advantageous to achieve that the pixel electrode 8 and the closest data line 5 on both sides respectively form an equal or approximately equal lateral capacitance.
In general, a portion of the pixel electrode 8 which is spaced apart from the data line 5 by less than 6um in the horizontal direction can form a lateral capacitance with the data line 5. For convenience of description, a portion of the pixel electrode 8 capable of forming a lateral capacitance with the left data line 5 in fig. 6a and 6b is referred to as a first portion, and a portion of the pixel electrode 8 capable of forming a lateral capacitance with the right data line 5 is referred to as a second portion.
In the embodiment of the disclosure, the second hollow structure 14 is disposed on the pixel electrode 8 provided with the first hollow structure 13, and the length of the second hollow structure 14 in the second direction Y is equal to or similar to that of the first hollow structure 13 in the second direction X, so that the length L1 of the first portion of the pixel electrode 8 in the second direction Y is equal to or similar to that of the second portions of the pixel electrode 8 in the second direction Y, and the lengths L2, L1 and L2 of the second portion of the pixel electrode 8 in the second direction Y are equal to or similar to each other, so that the lateral capacitance cpd_l formed between the first portion and the left data line 5, and the lateral capacitance cpd_2 formed between the second portion and the right data line 5 are smaller than or equal to the preset capacitance difference, thereby effectively reducing or even eliminating the influence of the data voltage on the pixel electrode 8 when the data voltages on both sides of the pixel electrode 8 are reversed in polarity.
Considering that if the length of the second hollow structure 14 in the second direction Y is too long, a certain influence is caused on the pixel aperture ratio; for this reason, in some embodiments, the length of the second hollowed-out structure 14 in the second direction Y may be not greater than the length of the first hollowed-out structure in the Y direction if the |cpd_l-cpd_r| is smaller than or equal to the preset capacitance difference.
In some embodiments, the preset capacitance difference is less than or equal to 1.0fF. When the lateral capacitances formed by the pixel electrode 8 and the data lines 5 located at both sides and closest to each other are equal, i.e., cpd_l=cpd_r, the influence of the data voltages on the data lines 5 at both sides of the pixel electrode 8 on the voltage applied to the pixel electrode 8 when the polarities of the data voltages are reversed at the same time can be effectively eliminated, so that mura can be effectively eliminated.
In practical applications, it is found that the portion of the pixel electrode 8 that is more than 6um away from the data line 5 in the first direction X does not generate significant lateral capacitance due to the relatively large distance from the data line 5. In addition, the length of the second hollow structure 14 in the first direction X is not too large, because the larger the length thereof in the first direction X is, the smaller the overall size of the pixel electrode 8 is, the smaller the storage capacitance formed between the pixel electrode 8 and the common electrode 9 is, and the capability of the pixel electrode 8 to maintain the gray scale voltage is reduced. Based on the above factors, in the embodiment of the present disclosure, the length of the second hollow structure 14 in the first direction X is greater than or equal to 6um and less than or equal to the length of the first hollow structure 13 in the first direction X.
Referring to fig. 6a, 6b, and 7, in some embodiments, in a pixel unit configured with a conductive bridge line 10, a pixel electrode 8 has a first orthographic projection on a first substrate 20, and data lines 5 located at both sides of the pixel electrode 8 and closest to the pixel electrode have a second orthographic projection on the first substrate 20, and a space region 11 is formed between the first orthographic projection and the second orthographic projection; in the pixel unit provided with the conductive bridge line 10, the common electrode 9 is a block-shaped common electrode 9, and the orthographic projection of the edge of the block-shaped common electrode 9 near the data line 5 on the first substrate 20 is located in the space region 7.
As shown in fig. 7, in the pixel cell provided with the conductive bridge line 10, the left side edge of the common electrode 9 is taken as an example. In the first direction X, the left edge of the common electrode 9 is located between the left edge of the pixel electrode 8 and the left data line 5, and at this time, an electric field formed between the left edge of the common electrode 9 and the left data line 5 may play a role in shielding the electric field formed between the left edge of the pixel electrode 8 and the left data line 5 to a certain extent, so that the electric field strength formed between the left edge of the pixel electrode 8 and the left data line 5 is reduced; since the lateral capacitance is related to the electric field strength, the lateral capacitance is smaller as the electric field strength is smaller, so that the lateral capacitance between the pixel electrode 8 and the left data line 4 can be reduced by the above design. Similarly, when the right edge of the common electrode 9 is located between the right edge of the pixel electrode 8 and the right data line 5, the lateral capacitance between the pixel electrode 8 and the right data line 4 can also be reduced.
In the embodiment of the disclosure, the lateral capacitances formed by the pixel electrode 8 and the data lines 5 located at two sides and closest to each other are reduced by the above design, which is beneficial to reducing the influence on the voltage applied to the pixel electrode 8 when the polarity of the data voltages in the data lines 5 at two sides of the pixel electrode 8 is reversed.
In some embodiments, the display substrate further includes a common electrode line 6, the common electrode line 6 and the gate line 4 are disposed in the same layer, the plurality of pixel units arranged along the first direction X corresponds to the same common electrode line 6, the common electrode 9 in the pixel units is electrically connected to the corresponding common electrode line 6, and the orthographic projection of the second end portion of the pixel electrode 8 on the first substrate 20 overlaps with the orthographic projection of the corresponding common electrode line 6 on the first substrate 20.
It should be noted that, in the present disclosure, the "co-layer arrangement" of two structures means that the two structures are obtained based on patterning of a thin film of the same material, and the distances between the two structures and the substrate may be equal or different.
With continued reference to fig. 5, in some embodiments, the gate line 4 includes first conductive patterns 4a and second conductive patterns 4b alternately arranged along the first direction X, the length of the first conductive patterns 4a in the second direction Y being greater than the length of the second conductive patterns 4b in the second direction Y; the front projection of the first conductive pattern 4a on the first substrate 20 does not overlap with the front projection of the data line 5 on the first substrate 20, and a portion in the first conductive pattern 4a serves as a gate electrode in the thin film transistor 7; the orthographic projection of the conductive bridge line 10 on the first substrate 20 does not overlap with the orthographic projection of the first conductive pattern 4a on the first substrate 20.
In the embodiment of the disclosure, the length of the first conductive pattern 4a in the second direction Y is larger, so that the overall resistance of the gate line 4 can be effectively reduced, and loading and transmission of signals are facilitated. Meanwhile, the length of the second conductive pattern 4b in the second direction Y is smaller, and the front-to-back plate between the second conductive pattern and the data line 5 and the conductive bridge line 10 is smaller, so that the parasitic capacitance formed is smaller, and the signal crosstalk between the gate line 4 and the data line 5 and the conductive bridge line 10 can be reduced effectively.
Fig. 8 is a schematic top view of another display substrate provided in the embodiment of the disclosure, fig. 9a is a top view of the pixel unit configured with the conductive bridge line in fig. 8, fig. 9b is another top view of the pixel unit configured with the conductive bridge line in fig. 8, and as shown in fig. 8 to 9b, in this embodiment, in the pixel unit configured with the conductive bridge line 10, not only the second side of the first end portion of the pixel electrode 8 is provided with the second hollow structure 14, but also the second side of the second end portion of the pixel electrode 8 is provided with the third hollow structure 15; the second hollow structure 14 and the third hollow structure 15 are configured such that an absolute value of a difference between lateral capacitances formed by the pixel electrode 8 and the data lines 5 located at two sides and closest to each other is smaller than or equal to a preset capacitance difference.
Compared to the length of the second hollow structure 14 in the second direction Y in fig. 5, 6a and 6b, the length of the second hollow structure 14 and the length of the third hollow structure 15 in the second direction Y in the present embodiment are shorter. Normally, both the upper right corner area and the lower right corner area of the pixel electrode 8 are covered by the black matrix on the opposite-box substrate, and if the length of the second hollow structure 14 in the second direction Y is too long, the second hollow structure 14 is not covered by the existing black matrix, the coverage area of the black matrix needs to be increased, so that the aperture ratio of the pixel unit is reduced. In this embodiment, the length of the second hollow structure 14 in the second direction Y can be reduced by setting the third hollow structure 15, and when the lengths of the second hollow structure 14 and the third hollow structure 15 in the second direction Y are both shorter, the second hollow structure 14 and the third hollow structure 15 are both disposed in the area covered by the existing black matrix, so that the aperture ratio of the pixel unit is not affected.
It should be noted that, in the embodiment of the present disclosure, the length of the second hollow structure 14 in the second direction Y and the length of the third hollow structure 15 in the second direction Y can be set and adjusted according to actual needs.
In some embodiments, the sum of the lengths of the second hollow structure 14 and the third hollow structure 15 in the second direction Y is equal to the length of the first hollow structure in the second direction Y. By this design it is advantageous to achieve that the pixel electrode 8 and the closest data line 5 on both sides respectively form an equal or approximately equal lateral capacitance.
In some embodiments, the length of the third hollow structure 15 in the first direction X is greater than or equal to 6um and less than or equal to the length of the first hollow structure 13 in the first direction X.
In some embodiments, the common electrode 9 is directly overlapped on the common electrode line 6. Since the orthographic projection of the second end portion of the pixel electrode 8 on the first substrate 20 overlaps with the orthographic projection of the common electrode line 6 on the first substrate 20, the third hollowed-out structure 15 provided at the second end portion overlaps with the common electrode line 6. Since the area of the common electrode line 6 is covered by the black matrix, the arrangement of the third hollow structure 15 does not substantially affect the aperture ratio of the pixel unit. Preferably, the orthographic projection of the third hollow structure 15 on the first substrate 20 is located in an area defined by the orthographic projection of the common electrode line 6 on the first substrate 20, and the arrangement of the third hollow structure 15 does not affect the aperture ratio of the pixel unit.
Referring to fig. 6a and 9a, in some embodiments, the drain electrode of the thin film transistor 7 is connected to the pixel electrode through the via hole 12, and when the first hollow structure 13 is located on the first side of the first end portion of the pixel electrode 8, the via hole 12 for connecting the drain electrode to the pixel electrode 8 is located between the first hollow structure 13 and the second hollow structure 14.
The embodiment of the disclosure also provides a display panel, which includes: the display substrate and the opposite box substrate are arranged oppositely, a liquid crystal layer is filled between the display substrate and the opposite box substrate, the display substrate provided by the embodiment is adopted by the display substrate, and the description of the display substrate can be found in the previous embodiment and is not repeated here.
In some embodiments, the counter substrate is a color film substrate comprising: the display device comprises a second substrate, a black matrix and a color film pattern, wherein the black matrix and the color film pattern are positioned on the second substrate; the black matrix defines a plurality of pixel light outlets (the shape of the pixel light outlets can be designed according to actual needs), the pixel light outlets are in one-to-one correspondence with the pixel units to define light outlet areas of the pixel units, and the color film patterns are positioned in the pixel light outlets; the orthographic projection of the black matrix on the first substrate completely covers the orthographic projection of the grid line, the data line, the thin film transistor, the first hollowed-out structure and the second hollowed-out structure on the first substrate. When the display substrate is further provided with a third hollow structure, the orthographic projection of the black matrix on the first substrate also covers the orthographic projection of the third hollow structure on the first substrate.
The embodiment of the disclosure further provides a display device, which includes a display panel and a light source, the display panel adopts the display panel in the above embodiment, and the description of the display panel can be referred to the content in the previous embodiment, which is not repeated here.
The display device provided by the embodiment of the disclosure may be any product or component with a display function, such as a liquid crystal display device, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (11)
1. A display substrate, comprising: the display device comprises a first substrate, a plurality of grid lines and a plurality of data lines, wherein the grid lines and the data lines are arranged on the first substrate, the grid lines extend along a first direction, the data lines extend along a second direction, and the first direction and the second direction are crossed and are parallel to a plane where the first substrate is positioned;
the plurality of gate lines and the plurality of data lines define a plurality of pixel units, the pixel units including: the pixel electrodes are positioned on one side, far away from the first substrate, of the common electrode, the pixel electrodes and the region where the pixel electrodes are positioned in the same pixel unit are distributed along a second direction, one end, close to the thin film transistor, of each pixel electrode is a first end, one end, far away from the thin film transistor, of each pixel electrode is a second end, at least part of each pixel unit is provided with a conductive bridge wire, and the conductive bridge wires and the pixel electrodes are arranged on the same layer;
in the pixel unit configured with the conductive bridge wire, a first hollow structure is arranged on a first side of the first end part or the second end part of the pixel electrode, the end part of the conductive bridge wire is positioned in the first hollow structure and is connected with the common electrode via hole, and a second hollow structure is arranged on a second side of the first end part of the pixel electrode, so that the absolute value of the difference of lateral capacitance formed by the pixel electrode and the nearest data wire positioned on two sides is smaller than or equal to a preset capacitance difference value;
the first side and the second side are opposite sides of the pixel electrode in a first direction;
in the pixel unit configured with the conductive bridge line, a third hollow structure is arranged on a second side of the second end part of the pixel electrode, and the second hollow structure and the third hollow structure are configured so that the absolute value of the difference between the lateral capacitances formed by the pixel electrode and the data lines which are positioned on two sides and are nearest to each other is smaller than or equal to a preset capacitance difference value;
the display substrate further includes: the common electrode wire and the grid wire are arranged on the same layer; the plurality of pixel units arranged along the first direction correspond to the same common electrode line, and the common electrode in the pixel units is electrically connected with the corresponding common electrode line;
the orthographic projection of the third hollowed-out structure on the first substrate is positioned in an area defined by the orthographic projection of the common electrode wire on the first substrate.
2. The display substrate of claim 1, wherein the second hollowed-out structure is equal in length to the first hollowed-out structure in the second direction.
3. The display substrate of claim 1, wherein a sum of lengths of the second and third hollowed structures in the second direction is equal to a length of the first hollowed structure in the second direction.
4. The display substrate of claim 1, wherein a length of the third hollowed-out structure in the first direction is less than or equal to a length of the first hollowed-out structure in the first direction.
5. The display substrate of claim 1, wherein a length of the second hollowed-out structure in the first direction is less than or equal to a length of the first hollowed-out structure in the first direction.
6. The display substrate according to claim 1, wherein the pixel electrode has an equal lateral capacitance to that of the data lines located at both sides and closest thereto.
7. The display substrate according to claim 1, wherein, within the pixel unit configured with the conductive bridge line, the pixel electrode has a first orthographic projection on the first substrate, the data line located on both sides of the pixel electrode and closest to the pixel electrode has a second orthographic projection on the first substrate, and a space region is formed between the first orthographic projection and the second orthographic projection;
in the pixel unit provided with the conductive bridge line, the common electrode is a block-shaped common electrode, and the orthographic projection of the edge, close to the data line, of the block-shaped common electrode on the first substrate is located in the interval region.
8. The display substrate according to claim 1, wherein,
an orthographic projection of the second end portion of the pixel electrode in the pixel unit on the first substrate overlaps with an orthographic projection of the corresponding common electrode line on the first substrate.
9. The display substrate according to any one of claims 1-8, wherein a drain electrode of the thin film transistor is connected to the pixel electrode via;
when the first hollow structure is positioned at the first side of the first end part of the pixel electrode, a via hole for connecting the drain electrode with the pixel electrode is positioned between the first hollow structure and the second hollow structure.
10. A display panel, comprising: a display substrate and a pair of box substrates which are oppositely arranged, wherein a liquid crystal layer is filled between the display substrate and the pair of box substrates, and the display substrate adopts the display substrate as set forth in any one of the claims 1-9.
11. A display device, comprising: the display panel and the light source as claimed in claim 10.
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2020/115949 WO2022056782A1 (en) | 2020-09-17 | 2020-09-17 | Display substrate, display panel and display device |
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| US7423713B2 (en) * | 2005-03-28 | 2008-09-09 | Epson Imaging Devices Corporation | Liquid crystal device and electronic equipment |
| CN105097832B (en) * | 2015-06-25 | 2018-09-11 | 合肥鑫晟光电科技有限公司 | A kind of array substrate and preparation method thereof, display device |
| CN105116648A (en) * | 2015-06-26 | 2015-12-02 | 武汉华星光电技术有限公司 | Pixel composition, array substrate and display device |
| CN109188813B (en) * | 2018-10-09 | 2021-11-12 | 京东方科技集团股份有限公司 | Pixel structure, array substrate and display panel |
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| JP2008151880A (en) * | 2006-12-15 | 2008-07-03 | Hitachi Displays Ltd | Display device |
| JP2009151098A (en) * | 2007-12-20 | 2009-07-09 | Toshiba Matsushita Display Technology Co Ltd | Flat-panel display device, array substrate, and its manufacturing method |
| CN106125436A (en) * | 2016-08-31 | 2016-11-16 | 京东方科技集团股份有限公司 | A kind of array base palte, display floater and manufacture method |
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| WO2022056782A1 (en) | 2022-03-24 |
| US11768412B2 (en) | 2023-09-26 |
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