CN116029251B - Circuit wiring optimization method and device based on circuit performance equalization - Google Patents
Circuit wiring optimization method and device based on circuit performance equalization Download PDFInfo
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- CN116029251B CN116029251B CN202310291827.1A CN202310291827A CN116029251B CN 116029251 B CN116029251 B CN 116029251B CN 202310291827 A CN202310291827 A CN 202310291827A CN 116029251 B CN116029251 B CN 116029251B
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Abstract
The invention relates to the technical field of integrated circuits, and discloses a circuit wiring optimization method and device based on circuit performance equalization, wherein the method comprises the following steps: the loops in the circuit topological graph are sequenced to obtain a loop sequence, the loops to be optimized are split to obtain an original node branch set, the node branches are initialized to obtain an initial node branch set, the circuit length of the node branches to be optimized is adjusted to obtain a dynamic optimized loop, the circuit length of the node branches to be optimized when the minimum impedance value is obtained to obtain an optimized branch, the loops to be optimized are used as the optimized loops if the node branches to be optimized do not exist in the initial node branch set, and the circuit wiring optimization of the circuit topological graph is completed if the loops to be optimized do not exist in the loop sequence. The invention also provides a circuit wiring optimization device based on circuit performance equalization. The invention can solve the problems of general circuit performance and larger circuit impedance existing in the current circuit wiring mode.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a circuit wiring optimization method and apparatus based on circuit performance equalization.
Background
An integrated circuit is a circuit with a characteristic function that integrates electronic components together using semiconductor technology. The process of fabricating the integrated circuit may include: circuit division, layout planning, layout, overall wiring, detailed wiring, packaging and the like.
In the process of manufacturing an integrated circuit, wiring is one of main difficulties, and reasonable wiring has the advantages of optimizing a circuit structure, reducing circuit impedance, improving circuit performance and the like. The wiring mode of the current circuit is mainly determined according to the circuit layout, namely, various components are distributed in a scattered manner in the circuit, then the circuit which is laid out well is tested, and the circuit can be put into use after the test, and the layout mode does not consider the definition of the length of the branch by utilizing the impedance of each branch in the circuit, so the current circuit wiring mode has the defects of common circuit performance and larger circuit impedance.
Disclosure of Invention
The invention provides a circuit wiring optimization method and device based on circuit performance equalization, and mainly aims to solve the problems of general circuit performance and large circuit impedance existing in the current circuit wiring mode.
In order to achieve the above object, the present invention provides a circuit wiring optimization method based on circuit performance equalization, including: and obtaining a circuit topological graph, and sequencing all loops in the circuit topological graph according to the circuit length to obtain a loop sequence.
Sequentially extracting loops to be optimized from the loop sequence, and splitting the loops to be optimized by using element nodes in the loops to be optimized to obtain an original node branch set.
Initializing the circuit length of each section of node branch in the original node branch set according to the circuit length of the loop to be optimized and the impedance of each node branch in the original node branch set by using a pre-constructed circuit allocation formula to obtain an initial node branch set, wherein the circuit allocation formula is as follows:
wherein l mi Representing the circuit length L of the ith node branch in the mth loop to be optimized m The circuit length of the mth loop to be optimized is represented, m represents the serial number of the loop to be optimized in the loop sequence, i represents the serial number of the node branch in the loop to be optimized, j represents the number of the node branch in the loop to be optimized, and r mi Representing the impedance of the ith node branch in the mth loop to be optimized.
And sequentially extracting node branches to be optimized from the initial node branch set, and adjusting the circuit length of the node branches to be optimized to obtain a dynamic optimization loop.
The adjusting the circuit length of the node branch to be optimized to obtain a dynamic optimization loop comprises the following steps: and identifying the termination point positions of the node branches to be optimized, and taking the termination point positions of the node branches to be optimized as optimized dynamic point positions.
And carrying out bidirectional movement along the loop to be optimized from the optimized dynamic point location to obtain a dynamic optimized loop.
The bidirectional movement is carried out along the loop to be optimized from the optimized dynamic point position to obtain a dynamic optimized loop, which comprises the following steps: and acquiring a front element distance threshold value and a rear element distance threshold value of the element at the optimized dynamic point position and the front element and the rear element in the loop to be optimized.
And moving forwards from the optimized dynamic point position to obtain the dynamic distance of the front element of the element at the optimized dynamic point position.
And judging whether the dynamic distance of the front element is larger than a front element distance threshold value.
And if the front element dynamic distance is larger than a front element distance threshold value, keeping the optimized dynamic point position moving forwards.
And if the front element dynamic distance is not greater than the front element distance threshold, stopping forward movement of the optimized dynamic point.
And moving backwards from the optimized dynamic point position to obtain the dynamic distance of the rear element of the element at the optimized dynamic point position.
And judging whether the dynamic distance of the rear element is larger than the distance threshold value of the rear element.
And if the rear element dynamic distance is larger than the rear element distance threshold value, keeping the optimized dynamic point to move backwards.
And if the dynamic distance of the rear element is not greater than the distance threshold of the rear element, stopping the forward movement of the optimized dynamic point location to obtain the dynamic optimized loop.
And obtaining the circuit length of the node branch to be optimized when the circuit topological graph is at the minimum impedance value, and obtaining the optimized branch.
Judging whether node branches to be optimized exist in the initial node branch set.
And if the node branches to be optimized exist in the initial node branch set, returning to the step of sequentially extracting the node branches to be optimized in the initial node branch set.
And if the node branches to be optimized do not exist in the initial node branch set, taking the loop to be optimized as an optimized loop.
And judging whether a loop to be optimized exists in the loop sequence.
And if the loop sequence has the loop to be optimized, returning to the step of sequentially extracting the loop to be optimized in the loop sequence.
And if the loop sequence does not have a loop to be optimized, completing the circuit wiring optimization of the circuit topological graph.
Optionally, the splitting the loop to be optimized by using element nodes in the loop to be optimized to obtain an original node branch set includes: and taking the element nodes in the loop to be optimized as loop dividing points.
And carrying out line segmentation on the loop to be optimized according to the loop segmentation points to obtain a segmented branch set.
And sequencing the segmented branch sets according to the signal transmission sequence in the loop to be optimized to obtain the original node branch set.
Optionally, the sorting each loop in the circuit topology map according to the circuit length to obtain a loop sequence includes: loop start points are identified in the circuit topology map.
And searching a loop termination point along a single circuit at the loop start point.
And taking a circuit between the loop starting point and the loop ending potential as a loop to obtain a loop set.
And sequencing the loops in the loop set according to the sequence from the large circuit length to the small circuit length of the loops to obtain a loop sequence.
Optionally, the initializing the circuit length of each segment of the node branches in the original node branch set according to the circuit length of the loop to be optimized and the impedance of each node branch in the original node branch set by using a pre-constructed circuit allocation formula to obtain an initial node branch set includes: and calculating the initialized circuit length of each section of node branch in the original node branch set according to the circuit length of the loop to be optimized and the impedance of each node branch in the original node branch set by utilizing a pre-constructed circuit distribution formula.
And identifying the initial point position of the loop to be optimized, and extracting the termination point position of each section of node branch in the loop to be optimized according to the initial point position and the initialization circuit length of each section of node branch.
And cutting the loop to be optimized according to the termination points of the node branches of each section to obtain an initial node branch set.
Optionally, the extracting, in the loop to be optimized, the termination point of each segment node branch according to the start point and the initializing circuit length of each segment node branch includes: and sequentially extracting the initialized circuit length of each section of node branch in the original node branch set to obtain a circuit length positioning sequence.
And determining termination points of each section of node branch in the loop to be optimized according to the circuit length positioning sequence.
Optionally, the obtaining the circuit length of the node branch to be optimized when the circuit topology diagram is at the minimum impedance value, to obtain an optimized branch includes: and calculating the real-time impedance value of the circuit topological graph by using a pre-constructed impedance value calculation formula to obtain an impedance value set.
And extracting the circuit length of the node branch to be optimized corresponding to the minimum impedance value from the impedance value set.
And taking the circuit length of the node branch to be optimized corresponding to the minimum impedance value as the circuit length of the node branch to be optimized to obtain the optimized branch.
Optionally, the impedance value calculation formula is as follows:
r t ＝r dq +r dh
wherein r is t Representing the impedance value of the circuit topology at the time t, r dq Representing the total impedance value, r, of the circuit topology diagram before the optimal dynamic point location at time t dh And representing the total impedance value of the circuit topology diagram positioned behind the optimized dynamic point at the time t.
In order to solve the above problems, the present invention also provides a circuit wiring optimizing apparatus based on circuit performance equalization, the apparatus comprising: the circuit sequencing module is used for acquiring a circuit topological graph, sequencing each circuit in the circuit topological graph according to the circuit length, and obtaining a circuit sequence.
The circuit splitting module to be optimized is used for sequentially extracting the circuit to be optimized from the circuit sequence, and splitting the circuit to be optimized by utilizing element nodes in the circuit to be optimized to obtain an original node branch set.
The circuit length initializing module is used for initializing the circuit length of each section of node branch in the original node branch set according to the circuit length of the loop to be optimized and the impedance of each node branch in the original node branch set by utilizing a pre-constructed circuit allocation formula to obtain an initial node branch set, wherein the circuit allocation formula is as follows:
Wherein l mi Representing the circuit length L of the ith node branch in the mth loop to be optimized m The circuit length of the mth loop to be optimized is represented, m represents the serial number of the loop to be optimized in the loop sequence, i represents the serial number of the node branch in the loop to be optimized, j represents the number of the node branch in the loop to be optimized, and r mi Representing the impedance of the ith node branch in the mth loop to be optimized.
And the dynamic optimization loop acquisition module is used for sequentially extracting node branches to be optimized in the initial node branch set, and adjusting the circuit length of the node branches to be optimized to obtain a dynamic optimization loop. The adjusting the circuit length of the node branch to be optimized to obtain a dynamic optimization loop comprises the following steps: and identifying the termination point positions of the node branches to be optimized, and taking the termination point positions of the node branches to be optimized as optimized dynamic point positions. And carrying out bidirectional movement along the loop to be optimized from the optimized dynamic point location to obtain a dynamic optimized loop. The bidirectional movement is carried out along the loop to be optimized from the optimized dynamic point position to obtain a dynamic optimized loop, which comprises the following steps: and acquiring a front element distance threshold value and a rear element distance threshold value of the element at the optimized dynamic point position and the front element and the rear element in the loop to be optimized. And moving forwards from the optimized dynamic point position to obtain the dynamic distance of the front element of the element at the optimized dynamic point position. And judging whether the dynamic distance of the front element is larger than a front element distance threshold value. And if the front element dynamic distance is larger than a front element distance threshold value, keeping the optimized dynamic point position moving forwards. And if the front element dynamic distance is not greater than the front element distance threshold, stopping forward movement of the optimized dynamic point. And moving backwards from the optimized dynamic point position to obtain the dynamic distance of the rear element of the element at the optimized dynamic point position. And judging whether the dynamic distance of the rear element is larger than the distance threshold value of the rear element. And if the rear element dynamic distance is larger than the rear element distance threshold value, keeping the optimized dynamic point to move backwards. And if the dynamic distance of the rear element is not greater than the distance threshold of the rear element, stopping the forward movement of the optimized dynamic point location to obtain the dynamic optimized loop.
And the loop iteration optimization module is used for obtaining the circuit length of the node branch to be optimized when the circuit topological graph is at the minimum impedance value, and obtaining an optimized branch. Judging whether node branches to be optimized exist in the initial node branch set. And if the node branches to be optimized exist in the initial node branch set, returning to the step of sequentially extracting the node branches to be optimized in the initial node branch set. And if the node branches to be optimized do not exist in the initial node branch set, taking the loop to be optimized as an optimized loop. And judging whether a loop to be optimized exists in the loop sequence. And if the loop sequence has the loop to be optimized, returning to the step of sequentially extracting the loop to be optimized in the loop sequence. And if the loop sequence does not have a loop to be optimized, completing the circuit wiring optimization of the circuit topological graph.
Compared with the background art, the method comprises the following steps: the method comprises the steps of sorting all loops in a circuit topological graph according to a circuit length to obtain a loop sequence, optimizing all loops to be optimized in the loop sequence in sequence, optimizing branches forming the loops to be optimized in sequence, splitting the loops to be optimized in the splitting process, splitting the loops to be optimized by utilizing element nodes in the loops to be optimized to obtain an original node branch set, optimizing all loops in the loop according to the circuit length of the loops to be optimized and the circuit length of all the nodes in the original node branch set by utilizing a pre-constructed circuit distribution formula, initializing the circuit length of each section of the node branch in the original node branch set to obtain an initial node branch set, obtaining the approximate length of each section of node branch, then utilizing a mode of adjusting the circuit length of the node branch to be optimized, obtaining a dynamic optimization loop, detecting the total impedance of the circuit topological graph in real time, obtaining the minimum impedance value of the circuit topological graph, iterating the loops to be optimized according to the node length of the node branch in the original node branch set, and finally optimizing all the loops to be optimized according to the node sequence. Therefore, the circuit wiring optimization method and device based on the circuit performance equalization can solve the problems of general circuit performance and larger circuit impedance existing in the current circuit wiring mode.
Drawings
Fig. 1 is a flow chart of a circuit wiring optimization method based on circuit performance equalization according to an embodiment of the present invention.
Fig. 2 is a functional block diagram of a circuit layout optimizing apparatus based on circuit performance equalization according to an embodiment of the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The embodiment of the application provides a circuit wiring optimization method based on circuit performance equalization. The execution subject of the circuit wiring optimization method based on circuit performance equalization includes, but is not limited to, at least one of a server, a terminal, and the like, which can be configured to execute the method provided by the embodiment of the application. In other words, the circuit wiring optimization method based on the circuit performance equalization may be performed by software or hardware installed in a terminal device or a server device. The service end includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, and the like.
Example 1:
referring to fig. 1, a flow chart of a circuit layout optimization method based on circuit performance equalization according to an embodiment of the present invention is shown. In this embodiment, the circuit wiring optimization method based on circuit performance equalization includes: s1, acquiring a circuit topological graph, and sequencing all loops in the circuit topological graph according to the length of a circuit to obtain a loop sequence.
The circuit topology diagram refers to a circuit structure diagram of circuits such as an integrated circuit, and a set of branches and nodes reflects the connection relation and properties of the circuits. Each loop refers to a circuit capable of forming a closed circuit in the circuit topology diagram.
In the embodiment of the invention, the circuit length of each loop in the circuit topological graph is fixed, and the circuit structure is optimized by only changing the positions of components in the loop.
In the embodiment of the present invention, the sequencing each loop in the circuit topology according to the circuit length to obtain a loop sequence includes: loop start points are identified in the circuit topology map.
And searching a loop termination point along a single circuit at the loop start point.
And taking a circuit between the loop starting point and the loop ending potential as a loop to obtain a loop set.
And sequencing the loops in the loop set according to the sequence from the large circuit length to the small circuit length of the loops to obtain a loop sequence.
In detail, the loop start point refers to a position in the loop where a circuit signal is initiated.
S2, sequentially extracting loops to be optimized from the loop sequence, and splitting the loops to be optimized by using element nodes in the loops to be optimized to obtain an original node branch set.
It is understood that the element node refers to various kinds of elements, such as: resistor, capacitor, power supply, diode, etc. Because the circuit impedance is different among different components, the impedance of each node branch in the original node branch set is different, and therefore the node branches need to be separated independently for calculation and analysis.
In the embodiment of the present invention, the splitting the loop to be optimized by using the element nodes in the loop to be optimized to obtain the original node branch set includes: and taking the element nodes in the loop to be optimized as loop dividing points.
And carrying out line segmentation on the loop to be optimized according to the loop segmentation points to obtain a segmented branch set.
And sequencing the segmented branch sets according to the signal transmission sequence in the loop to be optimized to obtain the original node branch set.
S3, initializing the circuit length of each section of node branch in the original node branch set according to the circuit length of the loop to be optimized and the impedance of each node branch in the original node branch set by utilizing a pre-constructed circuit distribution formula, and obtaining an initial node branch set.
In detail, the circuit allocation formula is as follows:
wherein l mi Representing the circuit length L of the ith node branch in the mth loop to be optimized m The circuit length of the mth loop to be optimized is represented, m represents the serial number of the loop to be optimized in the loop sequence, i represents the serial number of the node branch in the loop to be optimized, j represents the number of the node branch in the loop to be optimized, and r mi Representing the impedance of the ith node branch in the mth loop to be optimized.
It can be understood that, since the total circuit length of the loop to be optimized is fixed, but the circuit length of each node branch in the loop to be optimized is adjustable, the circuit length of each node branch in the original node branch set is initialized according to the principle that the circuit length should be shorter as the circuit impedance is larger.
In the embodiment of the invention, when the circuit length of each section of node branch in the original node branch set is initialized, the circuit length of each section of node branch is distributed according to the impedance size proportion of each section of node branch, and the larger the impedance of the unit circuit length is, the smaller the circuit length of the distributed node branch is, so that the whole circuit impedance is reduced.
In the embodiment of the present invention, the initializing the circuit length of each segment of node branch in the original node branch set according to the circuit length of the loop to be optimized and the impedance of each node branch in the original node branch set by using the pre-constructed circuit allocation formula to obtain an initial node branch set includes: and calculating the initialized circuit length of each section of node branch in the original node branch set according to the circuit length of the loop to be optimized and the impedance of each node branch in the original node branch set by utilizing a pre-constructed circuit distribution formula.
And identifying the initial point position of the loop to be optimized, and extracting the termination point position of each section of node branch in the loop to be optimized according to the initial point position and the initialization circuit length of each section of node branch.
And cutting the loop to be optimized according to the termination points of the node branches of each section to obtain an initial node branch set.
It can be explained that, after the initial point of the loop to be optimized and the length of the initializing circuit of each section of node branch are determined, the first section of initializing node branch is obtained after the initial point is first extended to the length of the initializing circuit of the first section of node branch. And then starting to extend the termination point of the first section of initialization node branch to the length of the initialization circuit of the second section of node branch to obtain a second section of initialization node branch, and the like until the division of the initialization node branch is completed.
In the embodiment of the present invention, the extracting, according to the starting point location and the initializing circuit length of each segment node branch, the ending point location of each segment node branch in the loop to be optimized includes: and sequentially extracting the initialized circuit length of each section of node branch in the original node branch set to obtain a circuit length positioning sequence.
And determining termination points of each section of node branch in the loop to be optimized according to the circuit length positioning sequence.
And S4, sequentially extracting node branches to be optimized in the initial node branch set, and adjusting the circuit length of the node branches to be optimized to obtain a dynamic optimization loop.
The dynamic optimization loop is a loop generated by dynamically moving a certain node in the loop within the range of the front node and the rear node. The total impedance value of the dynamic optimization loop is always changed, so that the loop at the moment is the optimal loop when the total impedance value is minimum in the changing process.
In the embodiment of the present invention, the adjusting the circuit length of the node branch to be optimized to obtain a dynamic optimization loop includes: and identifying the termination point positions of the node branches to be optimized, and taking the termination point positions of the node branches to be optimized as optimized dynamic point positions.
And carrying out bidirectional movement along the loop to be optimized from the optimized dynamic point location to obtain a dynamic optimized loop.
It can be explained that at the beginning of the optimization, the node at which the second (subsequent) element of the first node branch to be optimized is located should be moved. For example: when the line and node distribution of the dynamic optimization loop is as follows: when the optimization is started, the capacitor (node) is firstly moved between the line starting point and the resistor (node), and then the capacitor (node) is the optimized dynamic point.
In the embodiment of the present invention, the bidirectional movement is performed along the loop to be optimized from the optimized dynamic point location to obtain a dynamic optimized loop, which includes: and acquiring a front element distance threshold value and a rear element distance threshold value of the element at the optimized dynamic point position and the front element and the rear element in the loop to be optimized.
And moving forwards from the optimized dynamic point position to obtain the dynamic distance of the front element of the element at the optimized dynamic point position.
And judging whether the dynamic distance of the front element is larger than a front element distance threshold value.
And if the front element dynamic distance is larger than a front element distance threshold value, keeping the optimized dynamic point position moving forwards.
And if the front element dynamic distance is not greater than the front element distance threshold, stopping forward movement of the optimized dynamic point.
And moving backwards from the optimized dynamic point position to obtain the dynamic distance of the rear element of the element at the optimized dynamic point position.
And judging whether the dynamic distance of the rear element is larger than the distance threshold value of the rear element.
And if the rear element dynamic distance is larger than the rear element distance threshold value, keeping the optimized dynamic point to move backwards.
And if the dynamic distance of the rear element is not greater than the distance threshold of the rear element, stopping the forward movement of the optimized dynamic point location to obtain the dynamic optimized loop.
It can be explained that the front element distance threshold refers to the nearest allowable distance between the element at the optimized dynamic point and the front element, and the rear element distance threshold refers to the nearest allowable distance between the element at the optimized dynamic point and the rear element, and due to the size and circuit performance of different elements, there should be a shortest distance between the different elements, and when the shortest distance is smaller, it means that two elements cannot form a complete loop.
In the embodiment of the present invention, when the line and node distribution of the dynamic optimization loop is: when the optimized dynamic point is the resistor (node), the resistor (node) can be moved towards the capacitor, when the resistor (node) is moved to the distance threshold value of the front element (capacitor), the resistor (node) is required to be moved towards the rear element (diode), and when the distance from the diode is equal to the distance threshold value of the rear element, the resistor (node) is stopped moving. A complete dynamic optimization loop is obtained at this time.
And S5, obtaining the circuit length of the node branch to be optimized when the circuit topological graph is at the minimum impedance value, and obtaining an optimized branch.
In the embodiment of the present invention, the obtaining the circuit length of the node branch to be optimized when the circuit topology diagram is at the minimum impedance value, to obtain an optimized branch, includes: and calculating the real-time impedance value of the circuit topological graph by using a pre-constructed impedance value calculation formula to obtain an impedance value set.
And extracting the circuit length of the node branch to be optimized corresponding to the minimum impedance value from the impedance value set.
And taking the circuit length of the node branch to be optimized corresponding to the minimum impedance value as the circuit length of the node branch to be optimized to obtain the optimized branch.
In detail, the impedance value calculation formula is as follows:
r t ＝r dq +r dh
wherein r is t Representing the impedance value of the circuit topology at the time t, r dq Representing the total impedance value, r, of the circuit topology diagram before the optimal dynamic point location at time t dh And representing the total impedance value of the circuit topology diagram positioned behind the optimized dynamic point at the time t.
S6, judging whether node branches to be optimized exist in the initial node branch set.
In the embodiment of the invention, after the node branches to be optimized are optimized, each node branch to be optimized in the initial node branch set is required to be optimized through cyclic iteration until the node branches to be optimized do not exist in the initial node branch set, which means that loop optimization corresponding to the initial node branch set is completed.
And if the node branches to be optimized exist in the initial node branch set, returning to the step of sequentially extracting the node branches to be optimized in the initial node branch set.
And if the node branches to be optimized do not exist in the initial node branch set, executing S7, and taking the loop to be optimized as an optimized loop.
S8, judging whether a loop to be optimized exists in the loop sequence.
In the embodiment of the invention, the loop optimization method in the loop sequence is similar to the optimization method of the node branch to be optimized, and all loops in the loop sequence are required to be optimized in a cyclic iteration mode until no loop to be optimized exists in the loop sequence, and the optimization of the circuit structure of the circuit topology graph is completed.
And if the loop sequence has the loop to be optimized, returning to the step of sequentially extracting the loop to be optimized in the loop sequence.
It can be understood that when the optimization of one loop to be optimized is completed, there may be already an optimized branch in the next loop to be optimized (the loop to be optimized and the next loop to be optimized share the optimized branch), and this does not need to be optimized, but only needs to optimize other node branches to be optimized in the next loop to be optimized sequentially.
And if the loop sequence does not have a loop to be optimized, executing S9 to finish the circuit wiring optimization of the circuit topological graph.
The beneficial effects are that: compared with the background art, the method comprises the following steps: the method comprises the steps of sorting all loops in a circuit topological graph according to a circuit length to obtain a loop sequence, optimizing all loops to be optimized in the loop sequence in sequence, optimizing branches forming the loops to be optimized in sequence, splitting the loops to be optimized in the splitting process, splitting the loops to be optimized by utilizing element nodes in the loops to be optimized to obtain an original node branch set, optimizing all loops in the loop according to the circuit length of the loops to be optimized and the circuit length of all the nodes in the original node branch set by utilizing a pre-constructed circuit distribution formula, initializing the circuit length of each section of the node branch in the original node branch set to obtain an initial node branch set, obtaining the approximate length of each section of node branch, then utilizing a mode of adjusting the circuit length of the node branch to be optimized, obtaining a dynamic optimization loop, detecting the total impedance of the circuit topological graph in real time, obtaining the minimum impedance value of the circuit topological graph, iterating the loops to be optimized according to the node length of the node branch in the original node branch set, and finally optimizing all the loops to be optimized according to the node sequence. Therefore, the circuit wiring optimization method and device based on the circuit performance equalization can solve the problems of general circuit performance and larger circuit impedance existing in the current circuit wiring mode.
Example 2:
fig. 2 is a functional block diagram of a circuit layout optimizing apparatus based on circuit performance equalization according to an embodiment of the present invention.
The circuit wiring optimization device 100 based on the circuit performance equalization of the present invention can be installed in an electronic apparatus. Depending on the implementation function, the circuit routing optimization apparatus 100 based on circuit performance equalization may include a loop ordering module 101, a loop splitting module to be optimized 102, a circuit length initializing module 103, a dynamic optimization loop obtaining module 104, and a loop iterative optimization module 105. The module of the invention, which may also be referred to as a unit, refers to a series of computer program segments, which are stored in the memory of the electronic device, capable of being executed by the processor of the electronic device and of performing a fixed function.
The circuit ordering module 101 is configured to obtain a circuit topology map, and order each circuit in the circuit topology map according to a circuit length to obtain a circuit sequence.
The circuit splitting module 102 to be optimized is configured to sequentially extract the circuits to be optimized from the circuit sequence, and split the circuits to be optimized by using element nodes in the circuits to be optimized to obtain an original node branch set.
The circuit length initializing module 103 is configured to initialize the circuit lengths of the node branches of each segment in the original node branch set according to the circuit lengths of the loop to be optimized and the impedance of each node branch in the original node branch set by using a pre-constructed circuit allocation formula, so as to obtain an initial node branch set, where the circuit allocation formula is as follows:
wherein l mi Representing the circuit length L of the ith node branch in the mth loop to be optimized m The circuit length of the mth loop to be optimized is represented, m represents the serial number of the loop to be optimized in the loop sequence, i represents the serial number of the node branch in the loop to be optimized, j represents the number of the node branch in the loop to be optimized, and r mi Representing the impedance of the ith node branch in the mth loop to be optimized.
The dynamic optimization loop obtaining module 104 is configured to sequentially extract node branches to be optimized in the initial node branch set, and adjust a circuit length of the node branches to be optimized to obtain a dynamic optimization loop.
The loop iteration optimization module 105 is configured to obtain a circuit length of the node branch to be optimized when the circuit topology diagram is at a minimum impedance value, so as to obtain an optimized branch. Judging whether node branches to be optimized exist in the initial node branch set. And if the node branches to be optimized exist in the initial node branch set, returning to the step of sequentially extracting the node branches to be optimized in the initial node branch set. And if the node branches to be optimized do not exist in the initial node branch set, taking the loop to be optimized as an optimized loop. And judging whether a loop to be optimized exists in the loop sequence. And if the loop sequence has the loop to be optimized, returning to the step of sequentially extracting the loop to be optimized in the loop sequence. And if the loop sequence does not have a loop to be optimized, completing the circuit wiring optimization of the circuit topological graph.
In detail, the modules in the circuit wiring optimization device 100 based on circuit performance equalization in the embodiment of the present invention use the same technical means as the circuit wiring optimization method based on circuit performance equalization described in fig. 1 and can produce the same technical effects, which are not described here again.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be other manners of division when actually implemented.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units can be realized in a form of hardware or a form of hardware and a form of software functional modules.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.
Finally, it should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention.
Claims (8)
1. A circuit routing optimization method based on circuit performance equalization, the method comprising:
obtaining a circuit topological graph, and sequencing all loops in the circuit topological graph according to the length of a circuit to obtain a loop sequence;
sequentially extracting loops to be optimized from the loop sequence, and splitting the loops to be optimized by using element nodes in the loops to be optimized to obtain an original node branch set;
initializing the circuit length of each section of node branch in the original node branch set according to the circuit length of the loop to be optimized and the impedance of each node branch in the original node branch set by using a pre-constructed circuit allocation formula to obtain an initial node branch set, wherein the circuit allocation formula is as follows:
Wherein l mi Representing the circuit length L of the ith node branch in the mth loop to be optimized m The circuit length of the mth loop to be optimized is represented, m represents the serial number of the loop to be optimized in the loop sequence, i represents the serial number of the node branch in the loop to be optimized, j represents the number of the node branch in the loop to be optimized, and r mi Representing the impedance of an ith node branch in an mth loop to be optimized;
sequentially extracting node branches to be optimized from the initial node branch set, and adjusting the circuit length of the node branches to be optimized to obtain a dynamic optimization loop;
the adjusting the circuit length of the node branch to be optimized to obtain a dynamic optimization loop comprises the following steps:
identifying the termination point positions of the node branches to be optimized, and taking the termination point positions of the node branches to be optimized as optimized dynamic point positions;
performing bidirectional movement along the loop to be optimized from the optimized dynamic point location to obtain a dynamic optimized loop;
the bidirectional movement is carried out along the loop to be optimized from the optimized dynamic point position to obtain a dynamic optimized loop, which comprises the following steps:
acquiring a front element distance threshold value and a rear element distance threshold value of the element at the optimized dynamic point position and the front element and the rear element in the loop to be optimized;
Forward moving from the optimized dynamic point position to obtain the dynamic distance of the front element of the element at the optimized dynamic point position;
judging whether the dynamic distance of the front element is larger than a front element distance threshold value or not;
if the front element dynamic distance is greater than a front element distance threshold, keeping the optimized dynamic point position moving forward;
if the dynamic distance of the front element is not greater than the threshold value of the distance of the front element, stopping the forward movement of the optimized dynamic point;
moving backwards from the optimized dynamic point position to obtain the dynamic distance of the rear element of the element at the optimized dynamic point position;
judging whether the dynamic distance of the rear element is larger than the distance threshold of the rear element;
if the rear element dynamic distance is greater than a rear element distance threshold, keeping the optimized dynamic point moving backwards;
if the dynamic distance of the rear element is not greater than the distance threshold of the rear element, stopping the forward movement of the optimized dynamic point location to obtain the dynamic optimized loop;
obtaining the circuit length of the node branch to be optimized when the circuit topological graph is at the minimum impedance value, and obtaining an optimized branch;
judging whether node branches to be optimized exist in the initial node branch set or not;
If the node branches to be optimized exist in the initial node branch set, returning to the step of sequentially extracting the node branches to be optimized in the initial node branch set;
if the node branches to be optimized do not exist in the initial node branch set, the loop to be optimized is used as an optimized loop;
judging whether a loop to be optimized exists in the loop sequence;
if the loop sequence has the loop to be optimized, returning to the step of sequentially extracting the loop to be optimized in the loop sequence;
and if the loop sequence does not have a loop to be optimized, completing the circuit wiring optimization of the circuit topological graph.
2. The circuit routing optimization method based on circuit performance equalization according to claim 1, wherein said splitting the circuit to be optimized by using element nodes in the circuit to be optimized to obtain an original node branch set comprises:
taking element nodes in the loop to be optimized as loop dividing points;
carrying out line segmentation on the loop to be optimized according to the loop segmentation points to obtain a segmented branch set;
and sequencing the segmented branch sets according to the signal transmission sequence in the loop to be optimized to obtain the original node branch set.
3. The circuit layout optimization method based on circuit performance equalization according to claim 1, wherein the ordering each loop in the circuit topology according to the circuit length to obtain a loop sequence comprises:
identifying a loop starting point in the circuit topology diagram;
searching a loop termination point along a single circuit at the loop start point;
taking a circuit between the loop starting point and the loop ending potential as a loop to obtain a loop set;
and sequencing the loops in the loop set according to the sequence from the large circuit length to the small circuit length of the loops to obtain a loop sequence.
4. The circuit layout optimization method based on circuit performance equalization according to claim 2, wherein initializing the circuit length of each segment of the node branches in the original node branch set to obtain an initial node branch set according to the circuit length of the circuit to be optimized and the impedance of each node branch in the original node branch set by using a pre-constructed circuit allocation formula comprises:
calculating the initialized circuit length of each section of node branch in the original node branch set according to the circuit length of the loop to be optimized and the impedance of each node branch in the original node branch set by utilizing a pre-constructed circuit distribution formula;
Identifying the initial point position of the loop to be optimized, and extracting the termination point position of each section of node branch in the loop to be optimized according to the initial point position and the initialization circuit length of each section of node branch;
and cutting the loop to be optimized according to the termination points of the node branches of each section to obtain an initial node branch set.
5. The circuit layout optimization method based on the circuit performance equalization according to claim 4, wherein the extracting termination points of each segment node branch in the loop to be optimized according to the start points and the initialized circuit length of each segment node branch comprises:
sequentially extracting the initialized circuit length of each section of node branch in the original node branch set to obtain a circuit length positioning sequence;
and determining termination points of each section of node branch in the loop to be optimized according to the circuit length positioning sequence.
6. The circuit layout optimization method based on circuit performance equalization according to claim 1, wherein the obtaining the circuit length of the node branch to be optimized when the circuit topology is at the minimum impedance value, to obtain an optimized branch, comprises:
Calculating the real-time impedance value of the circuit topological graph by using a pre-constructed impedance value calculation formula to obtain an impedance value set;
extracting the circuit length of the node branch to be optimized corresponding to the minimum impedance value in the impedance value set;
and taking the circuit length of the node branch to be optimized corresponding to the minimum impedance value as the circuit length of the node branch to be optimized to obtain the optimized branch.
7. The circuit wiring optimization method based on circuit performance equalization according to claim 6, wherein the impedance value calculation formula is as follows:
r t =r dq +r dh
wherein r is t Representing the impedance value of the circuit topology at the time t, r dq Representing the total impedance value, r, of the circuit topology diagram before the optimal dynamic point location at time t dh And representing the total impedance value of the circuit topology diagram positioned behind the optimized dynamic point at the time t.
8. A circuit routing optimization apparatus based on circuit performance equalization, the apparatus comprising:
the circuit sequencing module is used for acquiring a circuit topological graph, sequencing each circuit in the circuit topological graph according to the circuit length, and obtaining a circuit sequence;
the circuit splitting module to be optimized is used for sequentially extracting the circuit to be optimized from the circuit sequence, and splitting the circuit to be optimized by utilizing element nodes in the circuit to be optimized to obtain an original node branch set;
The circuit length initializing module is used for initializing the circuit length of each section of node branch in the original node branch set according to the circuit length of the loop to be optimized and the impedance of each node branch in the original node branch set by utilizing a pre-constructed circuit allocation formula to obtain an initial node branch set, wherein the circuit allocation formula is as follows:
wherein l mi Representing the circuit length L of the ith node branch in the mth loop to be optimized m The circuit length of the mth loop to be optimized is represented, m represents the serial number of the loop to be optimized in the loop sequence, i represents the serial number of the node branch in the loop to be optimized, j represents the number of the node branch in the loop to be optimized, and r mi Representing the impedance of an ith node branch in an mth loop to be optimized;
the dynamic optimization loop acquisition module is used for sequentially extracting node branches to be optimized in the initial node branch set, and adjusting the circuit length of the node branches to be optimized to obtain a dynamic optimization loop; the adjusting the circuit length of the node branch to be optimized to obtain a dynamic optimization loop comprises the following steps: identifying the termination point positions of the node branches to be optimized, and taking the termination point positions of the node branches to be optimized as optimized dynamic point positions; performing bidirectional movement along the loop to be optimized from the optimized dynamic point location to obtain a dynamic optimized loop; the bidirectional movement is carried out along the loop to be optimized from the optimized dynamic point position to obtain a dynamic optimized loop, which comprises the following steps: acquiring a front element distance threshold value and a rear element distance threshold value of the element at the optimized dynamic point position and the front element and the rear element in the loop to be optimized; forward moving from the optimized dynamic point position to obtain the dynamic distance of the front element of the element at the optimized dynamic point position; judging whether the dynamic distance of the front element is larger than a front element distance threshold value or not; if the front element dynamic distance is greater than a front element distance threshold, keeping the optimized dynamic point position moving forward; if the dynamic distance of the front element is not greater than the threshold value of the distance of the front element, stopping the forward movement of the optimized dynamic point; moving backwards from the optimized dynamic point position to obtain the dynamic distance of the rear element of the element at the optimized dynamic point position; judging whether the dynamic distance of the rear element is larger than the distance threshold of the rear element; if the rear element dynamic distance is greater than a rear element distance threshold, keeping the optimized dynamic point moving backwards; if the dynamic distance of the rear element is not greater than the distance threshold of the rear element, stopping the forward movement of the optimized dynamic point location to obtain the dynamic optimized loop;
The loop iteration optimization module is used for obtaining the circuit length of the node branch to be optimized when the circuit topological graph is at the minimum impedance value, so as to obtain an optimized branch; judging whether node branches to be optimized exist in the initial node branch set or not; if the node branches to be optimized exist in the initial node branch set, returning to the step of sequentially extracting the node branches to be optimized in the initial node branch set; if the node branches to be optimized do not exist in the initial node branch set, the loop to be optimized is used as an optimized loop; judging whether a loop to be optimized exists in the loop sequence; if the loop sequence has the loop to be optimized, returning to the step of sequentially extracting the loop to be optimized in the loop sequence; and if the loop sequence does not have a loop to be optimized, completing the circuit wiring optimization of the circuit topological graph.
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