CN116027176A - Test structure, test structure layout and test method of semiconductor device - Google Patents

Abstract

The invention provides a test structure, a test structure layout and a test method of a semiconductor device. In the test structure, the third sub-metal lines on the surface of the shared metal plug in the same row or column along the X direction and/or the Y direction are connected in series, then, the tail ends of the first sub-metal lines in the same row or column after being connected in series are connected in series to form a first test chain (assumed to be M2 of an odd row or an odd column), then, by using the same method, the fourth sub-metal lines (corresponding to the first test chain, namely M2 of an even row or an even column) which are spaced from the third sub-metal lines in the same row or the Y direction are connected in series to form a second test chain, and then, by testing whether a current exists between the first test chain and the second test chain, namely the second metal lines of an odd row and the second metal lines of an even row, whether the shared metal plug is shorted with the metal layer M1 on the surface of the adjacent normal metal plug can be determined.

Description

Test structure, test structure layout and test method of semiconductor device

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a test structure of a semiconductor device, a test structure layout, and a test method thereof.

Background

In the conventional chip design, in order to reduce the size of the SRAM device, for example, the F90SRAM device, there is a case that the source or drain of one MOS transistor and the gate of another MOS transistor share a metal plug CT (simply referred to as a shared metal plug), and because the length of the shared metal plug is longer than that of the normal metal plug, the shared metal plug is shorted with the metal layer M1 on the surface of the adjacent normal metal plug, which often causes the problem of failure of the flash memory device.

Therefore, to avoid the problem of the failure of the flash memory device, how to find the size of the metal layer M1 (or what layer of metal lines) and the metal plug is an urgent problem in this field.

Disclosure of Invention

The invention aims to provide a test structure, a test structure layout and a test method of a semiconductor device, which are used for determining the optimal size by testing a test structure capable of setting shared metal plugs and metal wires with different sizes, and rapidly finding out the failure problem of the semiconductor device through the test structure.

In order to solve the above technical problems, the present invention provides a test structure of a semiconductor device, the test structure comprising:

a semiconductor substrate on which a device isolation structure is formed;

the sharing metal plugs are positioned on the device isolation structure, and each sharing metal plug is used for electrically connecting a source electrode or a drain electrode of one MOS tube with a grid electrode of the other MOS tube in the equivalent SRAM device;

the first layer metal wire comprises a plurality of first sub-metal wires and a plurality of second sub-metal wires, wherein one first sub-metal wire covers the surface of one shared metal plug and is electrically connected with the shared metal plug, and the plurality of second sub-metal wires are respectively positioned between two adjacent first sub-metal wires, namely are arranged at intervals with the plurality of first sub-metal wires;

the second layer of metal wires comprises a plurality of third sub-metal wires and a plurality of fourth sub-metal wires, wherein one third sub-metal wire covers the surface of one first sub-metal wire, one fourth sub-metal wire covers the surface of one second sub-metal wire, the third sub-metal wires in the same row or column along the X direction or the Y direction are connected in series to form a first test chain, and the fourth sub-metal wires in the same row or column along the X direction or the Y direction are connected in series to form a second test chain.

Further, the test structure may further include a plurality of through holes, where the plurality of through holes are specifically located in an inter-metal dielectric between the first layer metal line and the second layer metal line, so as to electrically connect corresponding sub-metal lines between the first layer metal line and the second layer metal line, respectively.

Further, the test structure may further include a first test pad electrically connected to the first test chain and a second test pad electrically connected to the second test chain.

In a second aspect, based on the same inventive concept as the test structure of the semiconductor device, the present invention further provides a test structure layout for forming the test structure of the semiconductor device, and specifically, the test structure layout provided by the present invention may include:

the first contact hole test layout can comprise a plurality of shared metal plug test patterns used for electrically connecting a source electrode or a drain electrode of one MOS tube and a grid electrode of the other MOS tube in the equivalent SRAM device;

the first metal test layout can comprise a plurality of first metal patterns and a plurality of second metal patterns which are arranged at intervals, the plurality of first metal patterns are respectively covered on the plurality of shared metal plug test patterns, and the projections of the plurality of first metal patterns and the plurality of shared metal plug test patterns are respectively overlapped in a part or all along the direction perpendicular to the test structure layout;

the second contact hole test layout can comprise a plurality of second contact hole patterns, and the second contact hole patterns respectively correspond to the first metal patterns and the second metal patterns;

the second metal test layout may include a first test chain pattern and a second test chain pattern, the first test chain pattern may include a plurality of first sub-test chain patterns extending in an X direction or a Y direction and each having a straight shape, and each of the first sub-test chain patterns may include a plurality of third metal patterns covering a plurality of the second contact hole patterns in a same row or a same column in the X direction or the Y direction, the second test chain pattern may include a plurality of second sub-test chain patterns extending in the X direction or the Y direction and each having a straight shape, and each of the second sub-test chain patterns includes a plurality of fourth metal patterns covering a plurality of the second contact hole patterns in a same row or a same column in the X direction or the Y direction.

Further, the third metal patterns and the fourth metal patterns are arranged at intervals, and one third metal pattern or one fourth metal pattern covers one second contact hole pattern.

Furthermore, the test structure layout may further include an isolation structure test layout, and the isolation structure test layout may specifically include a shallow trench isolation structure pattern, where the shallow trench isolation structure pattern is located below a plurality of the shared metal plug test patterns.

Further, the test structure layout may further include a pad test layout, where the pad test layout may include a first pad pattern and a second pad pattern, where the first pad pattern is located on the first test chain pattern, and the second pad pattern is located on the second test chain pattern.

The third aspect of the present invention provides a method for forming a test structure of a semiconductor device by using the test structure layout provided by the present invention, which specifically includes the following steps:

providing a semiconductor substrate;

providing an isolation structure test layout, and forming a device isolation structure on the semiconductor substrate through the isolation structure test layout;

providing a first contact hole test layout, and forming a plurality of shared metal plugs on the device isolation structure through the first contact hole test layout;

providing a first metal test layout, and forming a first layer metal wire structure through the first metal test layout, wherein the first layer metal wire structure comprises a plurality of first sub-metal wires and a plurality of second sub-metal wires, one first sub-metal wire covers the surface of one shared metal plug and is electrically connected with the shared metal plug, and the plurality of second sub-metal wires are respectively positioned between two adjacent first sub-metal wires, namely are arranged at intervals with the plurality of first sub-metal wires;

providing a second contact hole test layout, and forming a plurality of through holes through the second contact hole test layout, wherein the through holes are respectively correspondingly covered on the first sub-metal wires and the second sub-metal wires;

providing a second metal test layout, and forming a second-layer metal wire structure through the second metal test layout, wherein the second-layer metal wire structure comprises a plurality of third sub-metal wires and a plurality of fourth sub-metal wires, one third sub-metal wire covers the surface of one first sub-metal wire, and one fourth sub-metal wire covers the surface of one second sub-metal wire.

In a fourth aspect, the present invention further provides a testing method for testing the testing structure of the semiconductor device, based on the same inventive concept as the testing structure of the semiconductor device, which specifically includes the following steps:

providing a test structure of the semiconductor device as described above;

and respectively applying voltages to the first test pad and the second test pad, and measuring the current between the first test chain and the second test chain.

In a fifth aspect, based on the same inventive concept as the test structure of the semiconductor device, the present invention further provides a method for detecting a defect of the semiconductor device corresponding to the test structure of the semiconductor device, which specifically includes the following steps:

providing a test structure of the semiconductor device as described above;

and respectively applying voltages to the first test bonding pad and the second test bonding pad, and determining whether the test structure is short-circuited with a shared metal plug and a second sub-metal wire adjacent to a first sub-metal wire electrically connected with the shared metal plug or not through the measured current between the first test chain and the second test chain.

Further, the step of determining whether the test structure has a shared metal plug shorted to a second sub-metal line adjacent to the first sub-metal line to which it is electrically connected may include:

and judging whether the measured current between the first test chain and the second test chain is greater than zero, if not, determining that the test structure is short-circuited with a shared metal plug and a second sub-metal wire adjacent to the first sub-metal wire electrically connected with the shared metal plug.

The sixth aspect is based on the same inventive concept, and the invention further provides an electronic device, which specifically comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are in communication with each other through the communication bus;

a memory for storing a computer program;

and the processor is used for realizing the testing steps of the testing method or the defect detection method steps of the semiconductor device when executing the program stored in the memory.

In a seventh aspect, based on the same inventive concept, the present invention further provides a computer-readable storage medium having stored therein a computer program which, when executed by a processor, implements the test steps of the test method described above, or the defect detection method steps of the semiconductor device.

Compared with the prior art, the technical scheme of the invention has at least one of the following beneficial effects:

the invention provides a novel test structure of a semiconductor device, wherein a third sub-metal wire formed on the surface of a shared metal plug in the same row or column along the X direction and/or the Y direction is connected in series, then, the tail ends of the connected third sub-metal wires in a plurality of rows or columns are connected in series to form a first test chain (assumed to be M2 of an odd row or an odd column), then, a fourth sub-metal wire which is spaced from the third sub-metal wire in the same row or the same column along the X direction or the Y direction (which can also be understood as M2 for electrically connecting a normal shared metal plug) is connected in series (relative to the first test chain, namely, M2 of an even row or an even column) to form a second test chain, and then, by testing whether a current exists between the first test chain and the second test chain, namely, the second layer metal wire of the odd row and the second layer metal wire of the even row, whether the shared metal plug is shorted with the metal layer M1 on the surface of the adjacent normal metal plug can be determined by the same method.

Furthermore, since the test structure provided by the invention can determine whether the shared metal plug is short-circuited with the metal layer M1 on the surface of the adjacent normal metal plug, the optimal size of the shared metal plug and the first layer metal wire can be determined by changing the sizes of the shared metal plug and the first layer metal wire in the test structure provided by the invention, and the optimal size of the shared metal plug and the first layer metal wire can be determined by testing the test structure, so that the performance of the SRAM device can be monitored in real time, and the yield of the semiconductor device can be further ensured.

Drawings

Fig. 1 is a schematic structural diagram of a part of a test layout in a test structure layout including a test structure of a semiconductor device according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of a complete test structure layout of all components of a test structure layout including a test structure of a semiconductor device according to an embodiment of the present invention.

Fig. 3 is a flow chart of a method for manufacturing a test structure of a semiconductor device according to an embodiment of the present invention.

Detailed Description

As described in the background art, in the conventional flash memory device, for example, in the F90SRAM device, in order to reduce the device size, there is a case that the source or drain of one MOS transistor and the gate of the other MOS transistor in the memory cell share a metal plug CT (simply referred to as a shared metal plug), and because the shared metal plug has a longer length than the normal metal plug, the shared metal plug is shorted with the metal layer M1 on the surface of the adjacent normal metal plug, which often causes the problem of failure of the flash memory device. Therefore, to avoid the problem of the failure of the flash memory device, how to find the size of the metal layer M1 (or what layer of metal lines) and the metal plug is an urgent problem in this field.

In view of this problem, the present inventors firstly propose a test structure of a special structure in which third sub-metal wires formed on the surface of a shared metal plug in the same row or column in the X-direction and/or Y-direction are connected in series, then, after connecting the ends of the series-connected rows or columns of third sub-metal wires in series as a first test chain (assuming to be M2 of an odd row or an odd column), then, by the same method, fourth sub-metal wires in the same row or column in the X-direction or Y-direction are connected in series (also understood to be M2 for electrically connecting a normal shared metal plug in series (with respect to the first test chain, M2 of an even row or an even column) to form a second test chain; then, by utilizing the first test chain and the second test chain in the unique test structure in the structure to apply voltage, whether current exists between the first test chain and the second test chain, namely, the second layer metal wires in the odd-numbered rows and the second layer metal wires in the even-numbered rows, whether the shared metal plug is short-circuited with the metal layer M1 on the surface of the adjacent normal metal plug can be determined, so that the defect detection of the semiconductor device by utilizing the test structure provided by the invention is realized.

In addition, by changing the sizes of the shared metal plug and the first layer metal wire in the test structure, and then in the test mode of the test structure, the optimal sizes of the shared metal plug and the first layer metal wire can be determined, the performance of the SRAM device can be monitored in real time, and the purpose of ensuring the yield of the semiconductor device is achieved.

Therefore, the invention aims to provide a test structure, a test structure layout and a test method of a semiconductor device, so that the test structure which can be provided with shared metal plugs and metal wires with different sizes is tested, the optimal size is determined, and the failure problem of the semiconductor device is rapidly found through the test structure.

The test structure, the test structure layout and the test method of the semiconductor device provided by the invention are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than as described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.

As used in this application and in the claims, the terms "a," "an," "the," and/or "the" are not specific to the singular, but may include the plural, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus. In describing embodiments of the present invention in detail, the cross-sectional view of the device structure is not partially exaggerated to a general scale for convenience of explanation, and the schematic drawings are only examples and should not limit the scope of the present invention herein. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.

The test structure layout provided by the invention is first described below. Referring to fig. 1 to 3, fig. 1 is a schematic structural diagram of a part of a test layout in a test structure layout including a test structure of a semiconductor device according to an embodiment of the present invention; fig. 2 is a schematic structural diagram of a complete test structure layout of all components of a test structure layout including a test structure of a semiconductor device according to an embodiment of the present invention.

As shown in fig. 1 to 2, the test structure layout provided by the present invention may specifically include:

a first contact hole test layout, which comprises a plurality of shared metal plug test patterns CT1 used for electrically connecting a source electrode or a drain electrode of one MOS tube with a grid electrode of the other MOS tube in the equivalent SRAM device;

the first metal test layout M1 comprises a plurality of first metal patterns and a plurality of second metal patterns which are arranged at intervals, the plurality of first metal patterns are respectively covered on the plurality of shared metal plug test patterns CT1, and projections of the plurality of first metal patterns and the plurality of shared metal plug test patterns CT1 are respectively overlapped in a part or all corresponding manner along the direction perpendicular to the test structure layout;

the second contact hole testing layout comprises a plurality of second contact hole patterns CT2, and the second contact hole patterns CT2 respectively correspond to the first metal patterns and the second metal patterns;

the second metal test layout comprises a first test chain pattern S1 and a second test chain pattern S2, the first test chain pattern S1 comprises a plurality of first sub-test chain patterns S11 which extend along the X direction or the Y direction and are all in a straight shape, each first sub-test chain pattern S11 comprises a plurality of third metal patterns which cover a plurality of second contact hole patterns CT2 in the same row or the same column along the X direction or the Y direction, the second test chain pattern S2 comprises a plurality of second sub-test chain patterns S22 which extend along the X direction or the Y direction and are all in a straight shape, and each second sub-test chain pattern S22 comprises a plurality of fourth metal patterns which cover a plurality of second contact hole patterns CT2 in the same row or the same column along the X direction or the Y direction.

It should be noted that, in the embodiment of the present invention, since the test pattern of the second contact hole pattern CT2 located on the test pattern of the first metal test layout M1 is located under the patterns of the first test chain pattern S1 and the second test chain pattern S2, in the exemplary fig. 2 provided by the present invention, the test pattern of the second contact hole pattern CT2 located under the patterns of the first test chain pattern S1 and the second test chain pattern S2 cannot be seen, so that, in order to identify the test pattern of the second contact hole pattern CT2, the test pattern of the second contact hole pattern CT2 is illustrated in the other places in fig. 2 where the test pattern of the second contact hole pattern CT2 is formed, but the test pattern of the second contact hole pattern CT2 located under the patterns of the first test chain pattern S1 and the second test chain pattern S2 is not identified.

The third metal patterns and the fourth metal patterns are different second-layer metal wires respectively covered on the first metal patterns and the second metal patterns in the second-layer metal wire structure in the test structure layout provided by the invention, so that the third metal patterns and the fourth metal patterns are arranged at intervals, and one third metal pattern or one fourth metal pattern is covered on one second contact hole pattern.

Furthermore, the test structure layout provided by the invention further comprises an isolation structure test layout, wherein the isolation structure test layout comprises shallow trench isolation structure patterns STI, and the shallow trench isolation structure patterns are positioned below a plurality of shared metal plug test patterns CT 1.

Furthermore, the test structure layout provided by the invention may further include a pad test layout (not shown), where the pad test layout includes a first pad pattern (not shown) and a second pad pattern (not shown), the first pad pattern is located on the first test chain pattern S1, and the second pad pattern is located on the second test chain pattern S2.

Specifically, the odd-numbered rows and the even-numbered rows of the second metal test layout in the test structure may be distinguished along the X direction as shown in fig. 2 to form the first test chain pattern S1 and the second test chain pattern S2, or the odd-numbered columns and the even-numbered columns of the second metal test layout in the test structure may be distinguished along the Y direction to form the first test chain pattern and the second test chain pattern (i.e., the layout of the test structure shown in fig. 2 is rotated by 90 degrees). The difference between the first test chain pattern S1 and the second test chain pattern S2 is that one is a second layer metal wire connected to the first metal pattern electrically connected to the shared metal plug test pattern CT1, the other is a second layer metal wire connected to a first layer metal wire electrically connected to a non-shared metal plug test pattern (a common metal plug in the SRAM device, which may also be referred to as a common metal plug) electrically connected to the source or the drain of the MOS transistor, and which is specifically the first test chain pattern and which is specifically the second test chain pattern.

Based on the test structure layout, the invention also provides a preparation method of the test structure of the semiconductor device, and particularly as shown in fig. 3, the preparation method of the test structure of the semiconductor device, provided by the invention, comprises the following steps:

in step S301, a semiconductor substrate is provided.

Step S302, providing an isolation structure test layout, and forming a device isolation structure on the semiconductor substrate through the isolation structure test layout;

step S303, providing a first contact hole test layout, and forming a plurality of shared metal plugs on the device isolation structure through the first contact hole test layout;

step S304, providing a first metal test layout, and forming a first-layer metal wire structure through the first metal test layout, wherein the first-layer metal wire structure comprises a plurality of first sub-metal wires and a plurality of second sub-metal wires, one first sub-metal wire covers the surface of one shared metal plug and is electrically connected with the shared metal plug, and the plurality of second sub-metal wires are respectively positioned between two adjacent first sub-metal wires, namely are arranged at intervals with the plurality of first sub-metal wires;

step S305, providing a second contact hole test layout, and forming a plurality of through holes through the second contact hole test layout, wherein the through holes are respectively correspondingly covered on the first sub-metal wires and the second sub-metal wires;

step S306, providing a second metal test layout, and forming a second-layer metal wire structure through the second metal test layout, wherein the second-layer metal wire structure comprises a plurality of third sub-metal wires and a plurality of fourth sub-metal wires, one third sub-metal wire covers the surface of one first sub-metal wire, and one fourth sub-metal wire covers the surface of one second sub-metal wire.

In this embodiment, a semiconductor substrate may be provided first, then, a device isolation structure for isolating a device unit may be formed on the semiconductor substrate by using processes such as etching, deposition, etc., and, by way of example, the device isolation structure in the test structure provided by the present invention may be a shallow trench isolation structure STI, then, the shallow trench isolation structure STI is used as a bottom, and then, each test layout is formed layer by layer on the surface of the shallow trench isolation structure STI in sequence, that is, a specific sequence is that a first contact hole test layout is formed first, and then, a first metal test layout, a second contact hole test layout, and a second metal test layout are formed.

Based on the test structure layout shown in fig. 2 and the manufacturing method shown in fig. 3, the invention also provides a test structure of a semiconductor device formed by using the test structure layout and the manufacturing method, which specifically comprises the following steps:

a semiconductor substrate, on which a device isolation structure STI is formed;

the sharing metal plugs CT are positioned on the device isolation structures STI, and each sharing metal plug CT is used for electrically connecting a source electrode or a drain electrode of one MOS tube with a grid electrode of the other MOS tube in the equivalent SRAM device;

the first layer metal wire comprises a plurality of first sub-metal wires and a plurality of second sub-metal wires, wherein one first sub-metal wire covers the surface of one shared metal plug CT1 and is electrically connected with the shared metal plug CT, and a plurality of second sub-metal wires M1b are respectively positioned between two adjacent first sub-metal wires, namely are arranged at intervals with the plurality of first sub-metal wires;

the second layer of metal wires comprises a plurality of third sub-metal wires and a plurality of fourth sub-metal wires, wherein one third sub-metal wire covers the surface of one first sub-metal wire, one fourth sub-metal wire covers the surface of one second sub-metal wire, the third sub-metal wires in the same row or column along the X direction or the Y direction are connected in series to form a first test chain S1, and the fourth sub-metal wires in the same row or column along the X direction or the Y direction are connected in series to form a second test chain S2.

Further, the test structure provided by the present invention may further include a first test pad (not shown) electrically connected to the first test chain and a second test pad (not shown) electrically connected to the second test chain.

Obviously, in the test structure provided by the invention, the third sub-metal lines formed on the surface of the shared metal plug in the same row or column along the X direction and/or the Y direction are connected in series, then the tail ends of the first sub-metal lines in the connected rows or columns are connected in series to form a first test chain (assumed to be M2 of an odd row or an odd column), then the fourth sub-metal lines formed on the surface of the non-shared metal plug in the same row or the same column along the X direction or the Y direction are connected in series (M2 of an even row or an even column relative to the first test chain) by the same method, so as to form a second test chain, and then whether the shared metal plug is shorted with the metal layer M1 on the surface of the adjacent normal metal plug can be determined by testing whether current exists between the first test chain and the second test chain, namely, the second metal lines of the odd row and the second metal lines of the even row.

Wherein the semiconductor substrate may be any suitable substrate known in the art, for example, at least one of the following mentioned materials: silicon, germanium, silicon carbide, silicon germanium carbide, indium arsenide, gallium arsenide, indium phosphide, or other III/V compound semiconductors, and the like.

Based on the same inventive concept, the invention also provides a test method based on the test structure, which specifically comprises the following steps:

providing a test structure of the semiconductor device as described above;

and respectively applying voltages to the first test pad and the second test pad, and measuring the current between the first test chain and the second test chain.

Based on the test structure, the invention also provides a defect detection method of the semiconductor device based on the test structure, which comprises the following steps:

providing a test structure of the semiconductor device as described above;

and respectively applying voltages to the first test bonding pad and the second test bonding pad, and determining whether the test structure is short-circuited with a shared metal plug and a second sub-metal wire adjacent to a first sub-metal wire electrically connected with the shared metal plug or not through the measured current between the first test chain and the second test chain.

Further, the step of determining whether the test structure has a shared metal plug shorted to a second sub-metal line adjacent to a first sub-metal line to which it is electrically connected, comprises:

and judging whether the measured current between the first test chain and the second test chain is greater than zero, if not, determining that the test structure is short-circuited with a shared metal plug and a second sub-metal wire adjacent to the first sub-metal wire electrically connected with the shared metal plug.

In summary, the present invention provides a novel test structure of a semiconductor device, in which a third sub-metal line formed on a surface of a shared metal plug in the same row or column along the X direction and/or the Y direction is connected in series, then, an end of a first sub-metal line of a plurality of rows or columns after being connected in series is connected in series as a first test chain (assuming to be M2 of an odd row or an odd column), then, by using the same method, a fourth sub-metal line formed on a surface of an unshared metal plug in the same row or the same column along the X direction or the Y direction is connected in series (M2 of an even row or an even column relative to the first test chain) to form a second test chain, and then, by testing whether a current exists between the first test chain and the second test chain, that is, the second metal line of the odd row and the second metal line of the even row, it can be determined whether the shared metal plug is shorted with the metal layer M1 on the surface of an adjacent normal metal plug thereof.

Furthermore, since the test structure provided by the invention can determine whether the shared metal plug is short-circuited with the metal layer M1 on the surface of the adjacent normal metal plug, the optimal size of the shared metal plug and the first layer metal wire can be determined by changing the sizes of the shared metal plug and the first layer metal wire in the test structure provided by the invention, and the optimal size of the shared metal plug and the first layer metal wire can be determined by testing the test structure, so that the performance of the SRAM device can be monitored in real time, and the yield of the semiconductor device can be further ensured.

It should be noted that in the embodiment of the present invention, an electronic device is further provided, which includes a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus, and the memory is used to store a computer program; and the processor is used for realizing the testing method provided by the embodiment of the invention or the defect detection method of the semiconductor device when executing the program stored in the memory.

In addition, the test method implemented by the processor executing the program stored in the memory, or other implementation manners of the defect detection method of the semiconductor device, are the same as those mentioned in the foregoing method embodiment, and will not be repeated here.

In yet another embodiment of the present invention, a computer readable storage medium is provided, where instructions are stored, which when executed on a computer, cause the computer to perform the testing method according to any one of the above embodiments, or the defect detection method of the semiconductor device.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium, or a semiconductor medium (e.g., solid state disk), etc.

It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

All that is required is that the similar parts are mutually referred to, and each embodiment is mainly explained for the differences from the other embodiments. In particular, for apparatus, electronic devices, and computer-readable storage medium embodiments, the description is relatively simple, as it is substantially similar to method embodiments, with reference to portions of the description of method embodiments being relevant.

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims (11)

1. A test structure of a semiconductor device, comprising:

a semiconductor substrate on which a device isolation structure is formed;

the sharing metal plugs are positioned on the device isolation structure, and each sharing metal plug is used for electrically connecting a source electrode or a drain electrode of one MOS tube with a grid electrode of the other MOS tube in the equivalent SRAM device;

the first layer metal wire comprises a plurality of first sub-metal wires and a plurality of second sub-metal wires, wherein one first sub-metal wire covers the surface of one shared metal plug and is electrically connected with the shared metal plug, and the plurality of second sub-metal wires are respectively positioned between two adjacent first sub-metal wires, namely are arranged at intervals with the plurality of first sub-metal wires;

the second layer of metal wires comprises a plurality of third sub-metal wires and a plurality of fourth sub-metal wires, wherein one third sub-metal wire covers the surface of one first sub-metal wire, one fourth sub-metal wire covers the surface of one second sub-metal wire, the third sub-metal wires in the same row or column along the X direction or the Y direction are connected in series to form a first test chain, and the fourth sub-metal wires in the same row or column along the X direction or the Y direction are connected in series to form a second test chain.

2. The test structure of a semiconductor device of claim 1, further comprising a plurality of vias in an inter-metal dielectric between the first layer of metal lines and the second layer of metal lines for electrically connecting corresponding sub-metal lines between the first layer of metal lines and the second layer of metal lines, respectively.

3. The test structure of a semiconductor device of claim 1, further comprising a first test pad electrically connected to the first test chain and a second test pad electrically connected to the second test chain.

4. A test structure layout, the test structure layout comprising:

the first contact hole test layout comprises a plurality of shared metal plug test patterns used for electrically connecting a source electrode or a drain electrode of one MOS tube with a grid electrode of the other MOS tube in the equivalent SRAM device;

the first metal test layout comprises a plurality of first metal patterns and a plurality of second metal patterns which are arranged at intervals, the plurality of first metal patterns are respectively covered on the plurality of shared metal plug test patterns, and projections of the plurality of first metal patterns and the plurality of shared metal plug test patterns are respectively overlapped in a part or all along the direction perpendicular to the test structure layout;

the second contact hole testing layout comprises a plurality of second contact hole patterns, and the second contact hole patterns respectively correspond to the first metal patterns and the second metal patterns;

the second metal test layout comprises a first test chain pattern and a second test chain pattern, the first test chain pattern comprises a plurality of first sub-test chain patterns which extend in the X direction or the Y direction and are all in a straight strip shape, each first sub-test chain pattern comprises a plurality of third metal patterns which cover a plurality of second contact hole patterns in the same row or the same column in the X direction or the Y direction, the second test chain pattern comprises a plurality of second sub-test chain patterns which extend in the X direction or the Y direction and are all in a straight strip shape, and each second sub-test chain pattern comprises a plurality of fourth metal patterns which cover a plurality of second contact hole patterns in the same row or the same column in the X direction or the Y direction.

5. The test structure layout according to claim 4, wherein a plurality of the third metal patterns and a plurality of the fourth metal patterns are arranged at intervals, and one of the third metal patterns and the fourth metal patterns is overlaid on one of the second contact hole patterns.

6. The test structure layout of claim 4, further comprising an isolation structure test layout, the isolation structure test layout comprising shallow trench isolation structure patterns, and the shallow trench isolation structure patterns being located under a plurality of the shared metal plug test patterns.

7. The test structure layout of claim 4, further comprising a pad test layout, the pad test layout comprising a first pad pattern and a second pad pattern, the first pad pattern being located on the first test chain pattern and the second pad pattern being located on the second test chain pattern.

8. A method for manufacturing a test structure, characterized in that the method for manufacturing a test structure uses the test structure layout according to any one of claims 4 to 7, the method comprising the steps of:

providing a semiconductor substrate;

providing an isolation structure test layout, and forming a device isolation structure on the semiconductor substrate through the isolation structure test layout;

providing a first contact hole test layout, and forming a plurality of shared metal plugs on the device isolation structure through the first contact hole test layout;

providing a first metal test layout, and forming a first layer metal wire structure through the first metal test layout, wherein the first layer metal wire structure comprises a plurality of first sub-metal wires and a plurality of second sub-metal wires, one first sub-metal wire covers the surface of one shared metal plug and is electrically connected with the shared metal plug, and the plurality of second sub-metal wires are respectively positioned between two adjacent first sub-metal wires, namely are arranged at intervals with the plurality of first sub-metal wires;

providing a second contact hole test layout, and forming a plurality of through holes through the second contact hole test layout, wherein the through holes are respectively correspondingly covered on the first sub-metal wires and the second sub-metal wires;

providing a second metal test layout, and forming a second-layer metal wire structure through the second metal test layout, wherein the second-layer metal wire structure comprises a plurality of third sub-metal wires and a plurality of fourth sub-metal wires, one third sub-metal wire covers the surface of one first sub-metal wire, and one fourth sub-metal wire covers the surface of one second sub-metal wire.

9. A method of testing comprising the steps of:

providing a test structure of a semiconductor device according to any of claims 1-3;

and respectively applying voltages to the first test pad and the second test pad, and measuring the current between the first test chain and the second test chain.

10. A defect detection method of a semiconductor device, comprising the steps of:

providing a test structure of a semiconductor device according to any of claims 1-3;

and respectively applying voltages to the first test bonding pad and the second test bonding pad, and determining whether the test structure is short-circuited with a shared metal plug and a second sub-metal wire adjacent to a first sub-metal wire electrically connected with the shared metal plug or not through the measured current between the first test chain and the second test chain.

11. The method of defect detection of a semiconductor device of claim 10, wherein the step of determining whether the test structure has a shared metal plug shorted to a second sub-metal line adjacent to a first sub-metal line to which it is electrically connected, comprises:

and judging whether the measured current between the first test chain and the second test chain is greater than zero, if not, determining that the test structure is short-circuited with a shared metal plug and a second sub-metal wire adjacent to the first sub-metal wire electrically connected with the shared metal plug.

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