CN116016398B - Multi-port access processing method, device, electronic equipment and storage medium - Google Patents
Multi-port access processing method, device, electronic equipment and storage medium Download PDFInfo
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Abstract
The embodiment of the invention provides a multi-port access processing method, a multi-port access processing device, electronic equipment and a storage medium. Each scheduler receives N access requests sent by all ports respectively; each scheduler respectively matches all the access requests with the target access requests to obtain N matching results; when at least two matching results are the same, arbitrating the same two matching results, and authorizing the corresponding at least two schedulers for the same port to access the corresponding storage areas; and the schedulers with different matching results authorize the corresponding ports to access the corresponding storage areas. Therefore, when a plurality of ports access the same storage area, the scheduler grants the right of accessing the corresponding storage area to the same port in an arbitration mode, so that the number of the schedulers is reduced, the physical hardware overhead is optimized, and the complexity of hardware layout and wiring is reduced.
Description
Technical Field
The present invention relates to the field of network storage, and in particular, to a method and apparatus for processing multi-port access, an electronic device, and a storage medium.
Background
In a high-density network chip, it is often necessary to write multi-channel data into a memory for caching, and read out the cached data through a certain scheduling mechanism. In general, the types of physical memory can be classified into two basic types, 1 read or 1 write, and 1 read 1 write. Where a "1 read or 1 write" type indicates that the memory is only allowed to perform one read operation or one write operation in one clock cycle. The "1 read 1 write" type indicates that the memory allows one read operation and one write operation to be performed simultaneously in one clock cycle.
In the prior art, in order to improve the access bandwidth of the service, a multi-port parallel access memory technology is introduced. Typically, the memory, ports, and schedulers comprise a logical memory that receives access requests through the ports, the memory comprising a plurality of memory regions, each memory region being configured with a scheduler for managing a corresponding memory region. Multiple ports can concurrently access multiple memory regions of memory, increasing access bandwidth. When multiple ports access the same memory area, the scheduler arbitrates and decides one of the ports to grant, and the granted port can access the corresponding memory area. It follows that in order to reduce the multi-port concurrent access conflict, a large number of schedulers need to be configured, resulting in an increase in both physical overhead and hardware placement and routing complexity.
Disclosure of Invention
In view of the above, the present invention aims to provide a multi-port access processing method, apparatus, electronic device and storage medium, which can configure a scheduler according to ports, and when a plurality of ports access a same storage area, the scheduler grants permission to access the corresponding storage area to the same port through an arbitration mode, thereby reducing the number of schedulers, optimizing the physical hardware overhead, and reducing the complexity of hardware layout and wiring.
In order to achieve the above object, the technical scheme adopted by the embodiment of the invention is as follows:
In a first aspect, the present invention provides a multi-port access processing method applied to a network chip, where the network chip includes a memory, N ports and N schedulers, the N ports are in one-to-one correspondence with the N schedulers, and the memory is divided into X storage areas, and the method includes:
each scheduler receives N access requests sent by all the ports respectively; each of the access request applications indicating access to one of the X storage areas;
Each scheduler respectively matches all the access requests with a target access request to obtain N matching results; the target access request is sent by a port corresponding to the scheduler;
When at least two matching results are the same, arbitrating the same two matching results, and authorizing the corresponding at least two schedulers for the same port to access the corresponding storage area;
And the schedulers with different matching results authorize the corresponding ports to access the corresponding storage areas.
In an alternative embodiment, the multi-port access processing method further includes:
when all the matching results are different, the schedulers with different matching results authorize the corresponding ports, and access corresponding to the storage areas is performed.
In an alternative embodiment, each access request contains identification information of a storage area to be accessed; each scheduler respectively matches all the access requests with a target access request to obtain N matching results, and the steps comprise:
the scheduler matches all the identification information with the target identification information to obtain N matching result sequences; the target identification information is identification information of a storage area to be accessed corresponding to a port corresponding to the scheduler.
In an optional embodiment, when there are at least two matching results that are the same, arbitrating the same two matching results, and authorizing the corresponding at least two schedulers for the same port, and performing the step of accessing the corresponding storage area, where the step includes:
when at least two matching results are the same, conflict ports which are successfully matched are respectively obtained in each scheduler with the same matching results; the conflict ports are all ports which are the same as the storage area to be accessed of the corresponding ports of the scheduler;
Determining a target port in the corresponding conflict port by each scheduler according to the unique arbitration rule;
and the at least two schedulers authorize the target port and access the storage area corresponding to the target port.
In a second aspect, the present invention provides a multi-port access processing device applied to a network chip, where the device includes a memory, N ports and N schedulers, the N ports are in one-to-one correspondence with the N schedulers, the memory is divided into X storage areas, and the schedulers and the memory are communicatively connected with the ports;
The schedulers are used for each scheduler to respectively receive N access requests sent by all the ports; each of the access request applications indicating access to one of the X storage areas; each scheduler respectively matches all the access requests with a target access request to obtain N matching results; the target access request is sent by a port corresponding to the scheduler; when at least two matching results are the same, arbitrating the same two matching results, and authorizing the corresponding at least two schedulers for the same port to access the corresponding storage area; and the schedulers with different matching results authorize the corresponding ports to access the corresponding storage areas.
In an alternative embodiment, the scheduler is specifically configured to:
when all the matching results are different, the schedulers with different matching results authorize the corresponding ports, and access corresponding to the storage areas is performed.
In an alternative embodiment, each of the access requests contains identification information of the storage area to be accessed, and the scheduler is specifically configured to:
the scheduler matches all the identification information with the target identification information to obtain N matching result sequences; the target identification information is identification information of a storage area to be accessed corresponding to a port corresponding to the scheduler.
In an alternative embodiment, the scheduler is specifically configured to:
When at least two matching results are the same, conflict ports which are successfully matched are respectively obtained in each scheduler with the same matching results; the conflict ports are all ports which are the same as the storage area to be accessed of the corresponding ports of the scheduler; determining a target port in the corresponding conflict port by each scheduler according to the unique arbitration rule; and the at least two schedulers authorize the target port and access the storage area corresponding to the target port.
In a third aspect, the present invention provides an electronic device comprising a memory for storing a computer program and a processor for executing the multiport access processing method according to any of the previous embodiments when the computer program is invoked.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a multi-port access processing method as set forth in any of the preceding embodiments.
Compared with the prior art, the multi-port access processing method, the multi-port access processing device, the electronic equipment and the storage medium provided by the embodiment of the invention allow the storage, the N ports and the N schedulers to be configured before receiving the access request, the N ports are in one-to-one correspondence with the N schedulers, the storage is divided into X storage areas, and each scheduler respectively receives the N access requests sent by all the ports; each access request application indicates access to one of the X storage areas; each scheduler respectively matches all the access requests with the target access requests to obtain N matching results; the target access request is sent by a port corresponding to the scheduler; when at least two matching results are the same, arbitrating the same two matching results, and authorizing the corresponding at least two schedulers for the same port to access the corresponding storage areas; and the schedulers with different matching results authorize the corresponding ports to access the corresponding storage areas. The method is characterized in that a scheduler is arranged on the basis of the ports, the scheduler manages the authority of the corresponding ports to access the storage areas, and when a plurality of ports access the same storage area, the scheduler grants the authority of the corresponding storage area to the same port in an arbitration mode, so that the number of the schedulers is reduced, the physical hardware overhead is optimized, and the complexity of hardware layout and wiring is reduced.
In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a basic structure diagram of a logical memory configured with 4 write ports and 2 read ports.
Fig. 2 shows a basic structure diagram of a logical memory configuring a scheduler according to the number of memory areas.
Fig. 3 shows a basic structure diagram of a logical memory configuring a scheduler according to the number of ports.
Fig. 4 is a schematic flow chart of a multi-port access process according to an embodiment of the present invention.
Fig. 5 shows a schematic flow chart of a sub-step of step S102 and step S103 in fig. 4.
Fig. 6 shows a block diagram of a multiport access processing device 200 according to an embodiment of the present invention.
Fig. 7 shows a block schematic diagram of the electronic device 100 according to an embodiment of the invention.
Icon: 100-an electronic device; a 120-processor; 130-a communication module; 200-a multi-port access processing device; 201-a memory; 202-port; 203-scheduler.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
It is noted that relational terms such as "first" and "second", and the like, are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Typically, a logic memory in the network chip configures a plurality of write ports and a plurality of read ports, each port corresponding to a data transmission channel. Taking a logic memory with 4 write ports and 2 read ports as an example, the basic structure is shown in fig. 1. Write channels 0-3 may generate write requests simultaneously per clock cycle, and read channels may read out any buffered data per clock cycle.
Taking a logical memory of a type of 1 read-1 write as an example, when a plurality of channels are to write the physical memory of the logical memory at the same time, only a write request of one channel can be authorized, that is, the port corresponding to the channel obtains the authority of the write request, and data can be written into the physical memory. While other unauthorized ports can only continue to wait. It follows that the write bandwidth of an unauthorized port inevitably drops.
In order to increase the access bandwidth of each port, a multi-port concurrent access memory mode is adopted to realize the multi-port read-write request. The physical memory of the memory can be divided into a plurality of memory areas, a scheduler is arranged for each memory area, and each scheduler manages the corresponding memory area to avoid access conflict. The scheduling algorithm adopted by the scheduler can be Round Robin (RR), weighted Round Robin (Weighted Round Robin WRR) and Strict Priority (SP). When the port accesses the data of the storage area, the scheduler needs to be applied with permission, and the authorized port is allowed to access the data of the corresponding storage area.
To further simplify the illustration, consider the example of FIG. 2, which assumes that the logical memory includes memory, 2 ports, and 4 schedulers. The memory is divided into 4 memory areas, the 4 schedulers are in one-to-one correspondence with the 4 memory areas, and if only writing operation is considered, the 2 ports are corresponding to 2 writing channels. When 2 ports access different storage areas, the data can be directly accessed and written into the corresponding storage areas. When 2 ports access the same memory area, the memory area is limited to only provide one write request in the same clock cycle, that is, only one port write request can be allowed, and then an 'access conflict' occurs.
When the 'access conflict' occurs, the dispatcher corresponding to the storage area arbitrates, one of the ports is authorized according to the arbitration result, and the authorized port performs the write request. It follows that in order to reduce the probability of "access conflicts", a large number of schedulers are typically required to manage the memory area, which results in increased physical overhead and increased hardware placement and routing complexity.
Based on the above, the embodiment of the invention provides a multi-port access processing method, a device, an electronic device and a storage medium.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
The multi-port access processing method and device provided by the embodiment of the invention can be applied to a network chip, wherein the network chip comprises a memory, N ports and N schedulers, the N ports are in one-to-one correspondence with the N schedulers, and the memory is divided into X memory areas.
Specifically, the scheme sets schedulers according to the number of ports, and each scheduler manages a corresponding port. Taking fig. 3 as an example, assuming that the number of write ports is 2, and the memory is divided into 4 storage spaces, only 2 schedulers are required to be set, and each scheduler can receive write requests of 2 ports, and each port corresponds to one write channel.
The multi-port access processing method provided by the embodiment of the invention is described below based on the fact that the network chip comprises a memory, a port and a scheduler. Referring to fig. 4, fig. 4 is a schematic flow chart of a multi-port access process according to an embodiment of the invention. The method comprises the following steps:
In step S101, each scheduler receives N access requests sent by all ports.
Wherein each access request application indicates access to one of the X storage areas.
In the embodiment of the invention, the ports are in one-to-one correspondence with the schedulers, and the schedulers are used for managing the corresponding ports. In order to avoid concurrent access of physical memory of the memory caused by multi-port 'access conflict', data of the memory are finally inconsistent, each scheduler receives N access requests sent by all ports respectively, and each scheduler processes all the received access requests.
Step S102, each scheduler respectively matches all access requests with the target access request to obtain N matching results.
Wherein the target access request is sent by a port corresponding to the scheduler.
In the embodiment of the invention, each scheduler matches all received access requests with the target access request, wherein all the access requests comprise the target access request, and the target access request is sent by a port managed by the scheduler. After each scheduler matches all access requests with the target access request, corresponding matching results are obtained, and then N schedulers obtain N matching results. The matching result of each scheduler is used for recording the conflict situations of other ports and the target port to access the storage area.
Step S103, when at least two matching results are the same, arbitrating the same two matching results, and authorizing the corresponding at least two schedulers for the same port to access the corresponding storage areas.
In the embodiment of the invention, when the matching results of at least two schedulers are the same, the storage areas accessed by the ports corresponding to the schedulers with the same matching results are shown to be in conflict, one target port can be selected in an arbitration mode, and at least two schedulers with the same matching results are authorized by the same target port. The authorized destination port is allowed access to the corresponding storage area.
Step S104, the schedulers with different matching results authorize the corresponding ports to access the corresponding storage areas.
In the embodiment of the invention, when the matching results are different, it is indicated that the access requests of the ports corresponding to the scheduler do not have access conflict, and no other ports and the corresponding ports access the same storage area in the access requests of all ports received by the scheduler. The scheduler directly grants the corresponding port, and the granted port can access the corresponding storage area.
In summary, the multi-port access processing method provided by the embodiment of the invention is applied to a network chip, the network chip comprises a memory, N ports and N schedulers, the N ports are in one-to-one correspondence with the N schedulers, the memory is divided into X storage areas, and each scheduler receives N access requests sent by all the ports respectively; each access request application indicates access to one of the X storage areas; each scheduler respectively matches all the access requests with the target access requests to obtain N matching results; the target access request is sent by a port corresponding to the scheduler; when at least two matching results are the same, arbitrating the same two matching results, and authorizing the corresponding at least two schedulers for the same port to access the corresponding storage areas; and the schedulers with different matching results authorize the corresponding ports to access the corresponding storage areas. The method is characterized in that a scheduler is arranged on the basis of the ports, the scheduler manages the authority of the corresponding ports to access the storage areas, and when a plurality of ports access the same storage area, the scheduler grants the authority of the corresponding storage area to the same port in an arbitration mode, so that the number of the schedulers is reduced, the physical hardware overhead is optimized, and the complexity of hardware layout and wiring is reduced.
Optionally, in practical application, when multiple ports access the storage areas concurrently, there is a case that the storage areas accessed by each port are different, and there is no "access conflict" between the ports. The multi-port access processing method further comprises the following steps:
When all the matching results are different, the schedulers with different matching results authorize the corresponding ports, and access to the corresponding storage areas is performed.
In the embodiment of the invention, each scheduler matches all the received access requests of all the ports with the access requests sent by the corresponding ports to obtain the matching result of each scheduler, and when the matching results of all the schedulers are different, each scheduler does not receive the same access request as the storage area to be accessed by the corresponding port, that is, no access conflict exists among the ports. Each scheduler grants the corresponding port, which is allowed to access the corresponding storage area to be accessed.
Optionally, in practical application, when multiple ports access the memory concurrently, in order to avoid "access conflict", the memory is divided into multiple storage areas, and the identification information may be used to distinguish between the storage areas. Each access request contains identification information of the storage area to be accessed, and referring to fig. 5, the substeps of step S102 may include:
in step S1021, the scheduler matches all the identification information with the target identification information to obtain N matching result sequences.
The target identification information is identification information of a storage area to be accessed corresponding to a port corresponding to the scheduler.
In the embodiment of the application, the identification information of the storage areas is uniformly addressed, and the identification information can be numbered or named, so that the application is not limited. When the ports access the storage areas, the identification information of the storage areas to be accessed needs to be carried when the access request is sent to the scheduler, so that the scheduler can conveniently judge whether the access conflict exists between the ports. And the dispatcher matches all the identification information carried in all the received access requests with the target identification information to obtain a matching result sequence. The N schedulers will get N matching result sequences. The target identification information is identification information of a storage area to be accessed, which is carried in an access request sent by a corresponding port managed by the scheduler.
Optionally, in practical application, according to the received access requests sent by all ports, the schedulers perform matching of the access requests, so as to obtain a matching result of each scheduler. When the same matching result appears, the corresponding port is indicated to have 'access conflict', and the scheduler selects one target port through arbitration and grants the target port. On the basis of fig. 4, referring to fig. 5, the substeps of step S103 may include:
step S1031, when at least two matching results are the same, a conflict port successfully matched is obtained in each scheduler with the same matching result.
The conflict ports are all ports which are the same as the storage area to be accessed by the corresponding ports of the scheduler.
In the embodiment of the invention, when a plurality of identical matching results exist, the fact that the ports have access conflict is described. Each scheduler with the same matching result respectively acquires a conflict port, and all ports which access the same storage area with the corresponding ports of the schedulers are the conflict ports, wherein the conflict ports comprise the corresponding ports of the memories.
Step S1032, each scheduler determines a target port in the corresponding conflict port according to the unique arbitration rule;
In the embodiment of the invention, when the 'access conflict' occurs, in order to enable the dispatcher to select the same port from the conflicting ports for authorization, a unified arbitration rule is set in the system. Each scheduler can select the same port from the conflict ports as a target port according to the unique arbitration rule.
Step S1033, at least two schedulers authorize the target port and access the storage area corresponding to the target port.
In the embodiment of the invention, as the unique blanking rule is used for carrying out conflict port arbitration, a plurality of schedulers select the same target port. And each scheduler grants the destination port. Although the target port is authorized by a plurality of schedulers, the target port is authorized to access the storage area to be accessed, so that the access of the target port can ensure the data consistency of the storage area to be accessed.
In order to more clearly illustrate the multi-port access processing method provided by the embodiment of the application, the two conditions of access non-conflict and access conflict when the multi-port access is performed concurrently are combined for illustration.
As a specific embodiment, a case where multiple ports concurrently access are not conflicting is illustrated. It is assumed that a logic memory is composed of 4 ports, 4 schedulers and a memory to provide data access service to the outside, the memory is divided into 4 memory areas, and the memory areas are identified by using numbers 0 to 3. The memory may be a Random Access Memory (RAM). Assume that the memory regions to be accessed by ports 0-3 are 0, 1,2, and 3, respectively. The ports are in one-to-one correspondence with schedulers, each scheduler is used for managing the corresponding port, and memories 0-3 respectively manage ports 0-3. The access requests sent by the corresponding ports to the schedulers are called target access requests, each scheduler can receive the access requests sent by all the ports, and each access request contains identification information of a storage area to be accessed. The correspondence among the ports, the scheduler, the target identification information, all the identification information, and the matching result is shown in table 1. The target identification information is a storage area number corresponding to a port corresponding to the scheduler, and all the identification information is a storage area number to be accessed contained in all access requests sent by all ports received by the caller.
TABLE 1
| Port (port) | Scheduler | Target identification information | All identification information | Matching results |
| Port 0 | Scheduler 0 | 0 | 0，1，2，3 | {1,0,0,0} |
| Port 1 | Scheduler 1 | 1 | 0，1，2，3 | {0,1,0,0} |
| Port 2 | Scheduler 2 | 2 | 0，1，2，3 | {0,0,1,0} |
| Port 3 | Scheduler 3 | 3 | 0，1，2，3 | {0,0,0,1} |
It can be seen that the schedulers match all the received access requests with the target access requests, and according to the matching result sequence, each scheduler does not receive other access requests carrying the same storage area number as the target access request, that is, the storage areas accessed by all the ports are different. According to the matching result, each scheduler grants the corresponding port, specifically, scheduler 0 grants access right of storage area 0 to port 0; scheduler 1 grants access to storage area 1 for port 1; the scheduler 2 grants access rights to the storage area 2 for the port 2; the scheduler 3 grants access rights to the storage area 3 for port 3.
As yet another embodiment, a case of a multi-port concurrent access conflict is illustrated. It is assumed that a logic memory is composed of 4 ports, 4 schedulers and a memory to provide data access service to the outside, the memory is divided into 4 memory areas, and the memory areas are identified by using numbers 0 to 3. Assume that the memory regions to be accessed by ports 0-3 are 0,1, 2, and 1, respectively. The ports are in one-to-one correspondence with schedulers, each scheduler is used for managing the corresponding port, and memories 0-3 respectively manage ports 0-3. The correspondence between the port, scheduler, target identification information, all identification information, and matching result is shown in table 2.
TABLE 2
| Port (port) | Scheduler | Target identification information | All identification information | Matching results |
| Port 0 | Scheduler 0 | 0 | 0，1，2，1 | {1,0,0,0} |
| Port 1 | Scheduler 1 | 1 | 0，1，2，1 | {0,1,0,1} |
| Port 2 | Scheduler 2 | 2 | 0，1，2，1 | {0,0,1,0} |
| Port 3 | Scheduler 3 | 1 | 0，1，2，1 | {0,1,0,1} |
It can be seen that the scheduler matches all the received access requests with the target access request, and according to the matching result sequence, it can be known that schedule 0 and schedule 2 do not receive other access requests carrying the same storage area number as the target access request, that is, no access conflict occurs between port 0 and port 2 managed by schedule 0 and schedule 2, the scheduler 0 grants access right to the storage area 0 to the port 0, and the scheduler 2 grants access right to the storage area 2 to the port 2. While both schedulers 1 and 3 receive other access requests carrying the same storage area number as the target access request. From the matching result sequence {0,1,0,1} it is known that an access conflict occurs between port 1 and port 3, both of which access the memory area 1. The scheduler 1 and the scheduler 3 respectively acquire the unique arbitration rules in the system, and respectively determine the target ports according to the arbitration rules, and since the arbitration rules are unique, the target ports determined by the scheduler 1 and the scheduler 3 are identical, for example, an RR scheduling algorithm is adopted, the arbitration rules are that the collision ports are traversed from the starting address 0, and the first collision port traversed is selected as the target port. Under such arbitration rules, both scheduler 1 and scheduler 3 eventually select port 1 as the target port and grant access to memory region 1 for port 1, while port 3 does not have access to memory region 1.
It should be noted that, the technical means for resolving the multi-port concurrent access conflict is that all schedulers use the unique arbitration rule in the system, so that the scheduler corresponding to the port with the access conflict can authorize the same port when the access conflict occurs, thereby avoiding that a plurality of ports simultaneously operate the physical memory of the memory and finally causing inconsistent data. The invention is not limited as to how the arbitration rules are specified.
Specifically, all schedulers use unique arbitration rules, and each scheduler does not use a separate arbitration rule. For example, the schedulers adopt an RR/WRR scheduling algorithm, all schedulers use the same RR starting address A, the last arbitration result is not used as the starting address, the RR starting address can be randomly one of 0 to N-1 or can be generated in an increment mode of 0 to N-1, so that the schedulers are ensured to use the same scheduling state, the schedulers are prevented from maintaining the scheduling state respectively, concurrent access of storage areas is avoided, and finally data inconsistency is caused.
Further, when an access conflict occurs, the arbitration rule is not unique, which can cause the access conflict of the storage area, and finally, the data of the storage is possibly inconsistent. For example, in table 2, the scheduler 1 and the scheduler 3 use RR scheduling algorithm and use different start addresses, and if the start address used by the scheduler 1 is 0, the target port determined by the arbitration of the scheduler 1 is port 1. If the starting address used by the scheduler 3 is 2, the target port determined by the arbitration of the scheduler 3 is port 3. At this time, both port 1 and port 3 are granted access rights to the storage area 1, and eventually conflicting accesses to the storage area 1 by port 1 and port 3 occur.
Based on the same inventive concept, the embodiment of the invention also provides a multi-port access processing device, which can execute the steps of the method in the example to achieve the corresponding technical effects. Referring to fig. 6, fig. 6 is a block diagram of a multi-port access processing device 200 according to an embodiment of the invention. The multi-port access processing device 200 is applied to a network chip, the multi-port access processing device 200 comprises a memory 201, N ports 202 and N schedulers 203, the N ports 202 are in one-to-one correspondence with the N schedulers 203, the memory 201 is divided into X storage areas, and the schedulers 203 and the memory 201 are in communication connection with the ports 202;
The schedulers 203 are used for each scheduler to respectively receive the N access requests sent by all the ports; each access request application indicates access to one of the X storage areas; each scheduler respectively matches all the access requests with the target access requests to obtain N matching results; the target access request is sent by a port corresponding to the scheduler; when at least two matching results are the same, arbitrating the same two matching results, and authorizing the corresponding at least two schedulers for the same port to access the corresponding storage areas; and the schedulers with different matching results authorize the corresponding ports to access the corresponding storage areas.
Optionally, the scheduler 203 is specifically configured to, when all the matching results are different, grant the corresponding port to the scheduler with the different matching result, and access the corresponding storage area.
Optionally, each access request includes identification information of a storage area to be accessed, and the scheduler 203 matches all the identification information with target identification information to obtain N matching result sequences; the target identification information is identification information of a storage area to be accessed corresponding to a port corresponding to the scheduler.
Optionally, the scheduler 203 is specifically configured to, when there are at least two matching results that are the same, obtain a conflict port that is successfully matched in each scheduler that is the same in the matching results; the conflict ports are all ports which are the same as the storage area to be accessed of the corresponding port of the scheduler; each scheduler determines a target port in the corresponding conflict port according to the unique arbitration rule; and authorizing the target port by at least two schedulers, and accessing the storage area corresponding to the target port.
Referring to fig. 7, a block diagram of an electronic device 100 according to an embodiment of the invention is shown. The electronic device 100 may be a network chip, a network router, a network switch, or the like. The electronic device 100 includes a memory 201, a processor 120, and a communication module 130. The memory 201, the processor 120, and the communication module 130 are electrically connected directly or indirectly to each other to realize data transmission or interaction. For example, the components may be electrically connected to each other via one or more communication buses or signal lines.
Wherein the memory 201 is used for storing programs or other data in addition to the aforementioned write request data. The Memory 201 may be, but is not limited to, random access Memory (Random Access Memory, RAM), read Only Memory (ROM), programmable Read Only Memory (Programmable Read-Only Memory, PROM), erasable Read Only Memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable Read Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.
The processor 120 is used to read/write data or programs stored in the memory 201 and perform corresponding functions. For example, the multiport access processing method disclosed in the above embodiments may be implemented when a computer program stored in the memory 201 is executed by the processor 120.
The communication module 130 is used for establishing a communication connection between the electronic device 100 and other communication terminals through a network, and for transceiving data through the network.
It should be understood that the structure shown in fig. 7 is merely a schematic diagram of the structure of the electronic device 100, and that the electronic device 100 may also include more or fewer components than those shown in fig. 7, or have a different configuration than that shown in fig. 7. The components shown in fig. 7 may be implemented in hardware, software, or a combination thereof. The memories 201 in fig. 6 and 7 may be the same memory or different memories.
Embodiments of the present invention also provide a computer readable storage medium having stored thereon a computer program which, when executed by the processor 120, implements the multi-port access processing method disclosed in the above embodiments.
In summary, the multi-port access processing method, apparatus, network device and storage medium provided in the embodiments of the present invention allow a memory, N ports and N schedulers to be configured before receiving an access request, where the N ports are in one-to-one correspondence with the N schedulers, and the memory is divided into X storage areas, and each scheduler receives N access requests sent by all the ports respectively; each access request application indicates access to one of the X storage areas; each scheduler respectively matches all the access requests with the target access requests to obtain N matching results; the target access request is sent by a port corresponding to the scheduler; when at least two matching results are the same, arbitrating the same two matching results, and authorizing the corresponding at least two schedulers for the same port to access the corresponding storage areas; and the schedulers with different matching results authorize the corresponding ports to access the corresponding storage areas. The method is characterized in that a scheduler is arranged on the basis of the ports, the scheduler manages the authority of the corresponding ports to access the storage areas, and when a plurality of ports access the same storage area, the scheduler grants the authority of the corresponding storage area to the same port in an arbitration mode, so that the number of the schedulers is reduced, the physical hardware overhead is optimized, and the complexity of hardware layout and wiring is reduced.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present invention may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A multi-port access processing method, applied to a network chip, the network chip including a memory, N ports and N schedulers, the N ports being in one-to-one correspondence with the N schedulers, the memory being divided into X storage areas, the method comprising:
each scheduler receives N access requests sent by all the ports respectively; each of the access request applications indicating access to one of the X storage areas;
Each scheduler respectively matches all the access requests with a target access request to obtain N matching results; the target access request is sent by a port corresponding to the scheduler;
When at least two matching results are the same, arbitrating the same two matching results, and authorizing the corresponding at least two schedulers for the same port to access the corresponding storage area;
And the schedulers with different matching results authorize the corresponding ports to access the corresponding storage areas.
2. The multi-port access processing method of claim 1, further comprising:
when all the matching results are different, the schedulers with different matching results authorize the corresponding ports, and access corresponding to the storage areas is performed.
3. The multi-port access processing method of claim 1 wherein each of the access requests contains identification information of a memory region to be accessed; each scheduler respectively matches all the access requests with a target access request to obtain N matching results, and the steps comprise:
the scheduler matches all the identification information with the target identification information to obtain N matching result sequences; the target identification information is identification information of a storage area to be accessed corresponding to a port corresponding to the scheduler.
4. The multi-port access processing method of claim 1, wherein when there are at least two matching results that are the same, arbitrating the same two matching results, and the corresponding at least two schedulers grant the same port, and the step of accessing the corresponding storage area includes:
when at least two matching results are the same, conflict ports which are successfully matched are respectively obtained in each scheduler with the same matching results; the conflict ports are all ports which are the same as the storage area to be accessed of the corresponding ports of the scheduler;
Determining a target port in the corresponding conflict port by each scheduler according to the unique arbitration rule;
and the at least two schedulers authorize the target port and access the storage area corresponding to the target port.
5. A multi-port access processing device, characterized in that it is applied to a network chip, said device comprises a memory, N ports and N schedulers, N said ports are in one-to-one correspondence with N said schedulers, said memory is divided into X storage areas, said schedulers and said memory are in communication connection with said ports;
The schedulers are used for each scheduler to respectively receive N access requests sent by all the ports; each of the access request applications indicating access to one of the X storage areas; each scheduler respectively matches all the access requests with a target access request to obtain N matching results; the target access request is sent by a port corresponding to the scheduler; when at least two matching results are the same, arbitrating the same two matching results, and authorizing the corresponding at least two schedulers for the same port to access the corresponding storage area; and the schedulers with different matching results authorize the corresponding ports to access the corresponding storage areas.
6. The multi-port access processing device of claim 5, wherein the scheduler is specifically configured to:
when all the matching results are different, the schedulers with different matching results authorize the corresponding ports, and access corresponding to the storage areas is performed.
7. The multi-port access processing device of claim 5 wherein each of said access requests contains identification information of a memory region to be accessed, said scheduler being specifically configured to:
the scheduler matches all the identification information with the target identification information to obtain N matching result sequences; the target identification information is identification information of a storage area to be accessed corresponding to a port corresponding to the scheduler.
8. The multi-port access processing device of claim 5, wherein the scheduler is specifically configured to:
When at least two matching results are the same, conflict ports which are successfully matched are respectively obtained in each scheduler with the same matching results; the conflict ports are all ports which are the same as the storage area to be accessed of the corresponding ports of the scheduler; determining a target port in the corresponding conflict port by each scheduler according to the unique arbitration rule; and the at least two schedulers authorize the target port and access the storage area corresponding to the target port.
9. An electronic device comprising a memory and a processor, the memory further configured to store a computer program, the processor configured to perform the multiport access processing method of any of claims 1-4 when the computer program is invoked.
10. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the multi-port access processing method according to any of claims 1-4.
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| CN113609221A (en) * | 2021-07-27 | 2021-11-05 | 卓尔智联(武汉)研究院有限公司 | Data storage method, data access device and storage medium |
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| US20040083326A1 (en) * | 2002-10-29 | 2004-04-29 | Yuanlong Wang | Switch scheduling algorithm |
| US8549234B2 (en) * | 2011-10-14 | 2013-10-01 | Renesas Mobile Corporation | Memory controller and methods |
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| CN101013407A (en) * | 2007-02-05 | 2007-08-08 | 北京中星微电子有限公司 | System and method for implementing memory mediation of supporting multi-bus multi-type memory device |
| CN113609221A (en) * | 2021-07-27 | 2021-11-05 | 卓尔智联(武汉)研究院有限公司 | Data storage method, data access device and storage medium |
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