CN116015333A - Radio frequency front-end chip, serial communication method, device and storage medium - Google Patents
Radio frequency front-end chip, serial communication method, device and storage medium Download PDFInfo
- Publication number
- CN116015333A CN116015333A CN202211720199.6A CN202211720199A CN116015333A CN 116015333 A CN116015333 A CN 116015333A CN 202211720199 A CN202211720199 A CN 202211720199A CN 116015333 A CN116015333 A CN 116015333A
- Authority
- CN
- China
- Prior art keywords
- radio frequency
- data
- module
- function module
- system clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000004891 communication Methods 0.000 title claims abstract description 21
- 230000006870 function Effects 0.000 claims description 165
- 230000005540 biological transmission Effects 0.000 claims description 22
- 238000005070 sampling Methods 0.000 claims description 17
- 230000001360 synchronised effect Effects 0.000 claims description 15
- 238000004590 computer program Methods 0.000 claims description 4
- 230000004044 response Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 12
- 239000013078 crystal Substances 0.000 description 7
- 238000002955 isolation Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Transceivers (AREA)
Abstract
The application discloses a radio frequency front end chip, a serial communication method, equipment and a storage medium, wherein the radio frequency front end chip at least comprises a radio frequency control module and a radio frequency function module, the radio frequency control module is connected with the radio frequency function module through signal lines, the number of the signal lines is smaller than the number of register bits of data to be transmitted, the signal lines comprise a start clock line and a data line, and the radio frequency control module is used for acquiring baseband data from a baseband chip by taking a system clock as a reference and splitting the baseband data; the radio frequency control module is also used for acquiring a system clock signal and transmitting the system clock signal to the radio frequency function module so as to synchronize the clock of the radio frequency function module with the system clock; the radio frequency control module is further configured to send the split baseband data to the radio frequency function module in real time.
Description
Technical Field
The embodiment of the application relates to the field of radio frequency, and relates to, but is not limited to, a radio frequency front end chip, a serial communication method, equipment and a storage medium.
Background
The application of 5G (fifth generation mobile communication technology) is becoming more and more widespread, and 5G-enabled communication devices are also becoming more and more. However, the requirement of 5G communication is higher than before, a larger channel bandwidth is required, and the communication delay is lower, and meanwhile, the requirement on the complexity of 5G equipment is higher. This also makes the rf front-end chip have to possess higher performance to meet the requirements of 5G communication. In the mobile phone radio frequency front end chip, the mobile phone radio frequency front end chip communicates with the baseband main control chip through a radio frequency front end interface (RF Front End Interface, RFFE), namely a mobile industry processor interface (Mobile Industry Processor Interface, MIPI) special for the radio frequency front end chip. If the module on each die (die) inside the radio frequency front end chip uses an independent RFFE interface to communicate with the baseband main control chip, the complexity of the chip is not reduced, and the cost is increased.
Existing schemes are roughly divided into two, the first scheme using parallel general purpose input output (General purpose input output, GPIO) and the second scheme using a serial interface scheme.
The first solution has the disadvantage: when more data needs to be transferred, the required signal lines will also increase correspondingly, which will result in an increase in the complexity and cost of the chip.
The second solution has the disadvantage: after the RFFE data sampling decoding module finishes processing the received data, the received data is sent to the serial data sending module, and the more register data are required to be transmitted, the larger the generated time delay is, the easier the system time sequence problem is introduced; the clock generation module is required to generate a new clock to complete the data transmission function, which increases the complexity of the design of the radio frequency function and the control module and also leads to an increase in cost.
Disclosure of Invention
In view of this, embodiments of the present application provide a radio frequency front end chip, a serial communication method, a device, and a storage medium.
The technical scheme of the embodiment of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a radio frequency front-end chip, where the radio frequency front-end chip at least includes a radio frequency control module and a radio frequency function module, where the radio frequency control module and the radio frequency function module are connected by a signal line, where the number of signal lines is smaller than the number of register bits of data to be transmitted, where the signal line includes a start clock line and a data line,
the radio frequency control module is used for acquiring baseband data from a baseband chip by taking a system clock as a reference and splitting the baseband data;
The radio frequency control module is also used for acquiring a system clock signal and transmitting the system clock signal to the radio frequency function module so as to synchronize the clock of the radio frequency function module with the system clock;
the radio frequency control module is further configured to send the split baseband data to the radio frequency function module in real time.
In a second aspect, an embodiment of the present application provides a serial communication method, applied to a radio frequency front end chip, where the radio frequency front end chip at least includes a radio frequency control module and a radio frequency function module, where the radio frequency control module and the radio frequency function module are connected by a signal line, the number of the signal lines is smaller than the number of register bits of data to be transmitted, and the signal line includes a start clock line and a data line, and the method includes:
the radio frequency control module takes a system clock as a reference to acquire baseband data from a baseband chip and splits the baseband data;
the radio frequency control module acquires a system clock signal and sends the system clock signal to the radio frequency function module so as to synchronize the clock of the radio frequency function module with the system clock;
and the radio frequency control module sends the split baseband data to the radio frequency function module in real time.
In a third aspect, an embodiment of the present application provides an electronic device, including a memory and a processor, where the memory stores a computer program executable on the processor, and where the processor implements the method described above when executing the program.
In a fourth aspect, embodiments of the present application provide a storage medium storing executable instructions for implementing the above method when executed by a processor.
In this embodiment of the present application, a radio frequency front end chip includes at least a radio frequency control module and a radio frequency function module, where the radio frequency control module and the radio frequency function module are connected by a signal line, the number of the signal lines is smaller than the number of register bits of data to be transmitted, the signal line includes a start clock line and a data line, and the radio frequency control module is configured to acquire baseband data from a baseband chip with a system clock as a reference, and split the baseband data; the radio frequency control module is also used for acquiring a system clock signal and transmitting the system clock signal to the radio frequency function module so as to synchronize the clock of the radio frequency function module with the system clock; the radio frequency control module is further configured to send the split baseband data to the radio frequency function module in real time. Therefore, the data can be updated to the radio frequency functional module only by fewer signal wires without additional internal crystal oscillator, the complexity in the chip is reduced, the cost of the radio frequency front-end chip is reduced, and the radio frequency front-end chip has the characteristics of ultra-low time delay and high instantaneity.
Drawings
Fig. 1 is a schematic structural diagram of a radio frequency front end chip according to an embodiment of the present application;
fig. 2A is a schematic structural diagram of a radio frequency front end chip according to an embodiment of the present application;
fig. 2B is a schematic structural diagram of a rf front-end chip according to an embodiment of the present disclosure;
fig. 2C is a timing chart of an Agipi interface provided in an embodiment of the present application;
fig. 3 is a schematic structural diagram of a radio frequency front end chip according to an embodiment of the present application;
fig. 4 is a schematic implementation flow chart of a serial communication method according to an embodiment of the present application;
fig. 5 is a schematic diagram of a composition structure of a serial communication device according to an embodiment of the present application;
fig. 6 is a schematic diagram of a hardware entity of an electronic device according to an embodiment of the present application.
Detailed Description
For the purposes, technical solutions and advantages of the embodiments of the present application to be more apparent, the specific technical solutions of the embodiments of the present application will be further described in detail below with reference to the accompanying drawings in the embodiments of the present application. The following examples are illustrative of the present application, but are not intended to limit the scope of the present application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
In the following description, the terms "first", "second", "third" and the like are merely used to distinguish similar objects and do not represent a specific ordering of the objects, it being understood that the "first", "second", "third" may be interchanged with a specific order or sequence, as permitted, to enable embodiments of the application described herein to be practiced otherwise than as illustrated or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application.
Fig. 1 is a schematic structural diagram of a radio frequency front end chip according to an embodiment of the present application, as shown in fig. 1, where the radio frequency front end chip includes a radio frequency control module 10 and a radio frequency function module 11, where the radio frequency module is connected to a baseband chip through a first interface, and the radio frequency control module is connected to the radio frequency function module through a second interface.
In one embodiment, the second interface is a Agipi (Agile general internal peripheral interface) interface. The first interface is an RFFE interface. In other embodiments, the two interfaces may be other types of interfaces.
The clock pin 101 of the radio frequency control module 10 is connected with the system clock pin 201 of the baseband chip 20; the data pin 102 of the radio frequency control module 10 is connected with the baseband data pin 202 of the baseband chip 20;
the clock pin 103 of the radio frequency control module 10 is connected with the radio frequency clock pin 111 of the radio frequency function module; the instruction pin 104 of the radio frequency control module is connected with the radio frequency instruction pin 112 of the radio frequency function module; the data pin 105 of the radio frequency control module is connected with the radio frequency data pin 113 of the radio frequency function module;
the radio frequency control module 10 splits each baseband data acquired sequentially from the baseband chip with the system clock as a reference into a radio frequency instruction and radio frequency data, wherein the radio frequency instruction comprises register information; identifying each register information one by one to determine whether the register information is matched with the radio frequency function module; under the condition that the register information is determined to be matched with the radio frequency function module, namely, the data required by the radio frequency function module is identified, the radio frequency instruction and the radio frequency data are determined to be target radio frequency instruction and target radio frequency data;
When the radio frequency control module 10 obtains the baseband chip data, the baseband data is split into radio frequency instructions and radio frequency data. In the transmission process, it is not necessary to wait for the radio frequency control module 10 to process all the baseband data and then transmit them together, but each time the radio frequency control module 10 recognizes one baseband data, one baseband data is transmitted to the radio frequency function module 11 under the condition that the baseband data is determined to be the baseband data of the corresponding radio frequency function module 11. Therefore, the clock is not required to be added, and the application system can carry the clock.
Here, the radio frequency command includes register information, and the radio frequency control module 10 may identify the register information and determine that the baseband data is the baseband data corresponding to the radio frequency function module 11.
In the implementation process, the radio frequency control module 10 transmits a baseband data to the radio frequency function module 11, and may transmit the baseband data through cmd_agi and data_ agi, and the clock signal clk_ agi is kept synchronous with the system clock. The radio frequency control module 10 generates a valid clk agi clock signal derived from the acquired SCLK clock signal using the RFFE interface, where the timing relationship is synchronized.
Because the rf functional module 11 in the rf front-end chip does not need all the baseband data sent by the baseband chip 20, the rf control module 10 identifies the split rf command, and transmits the baseband data needed by the rf functional module 11, and the baseband data not needed by the rf functional module 11 does not need to be transmitted, thereby reducing the data transmission amount.
The radio frequency control module 10 sends the system clock, the target radio frequency command and the target radio frequency data to the radio frequency function module.
In the implementation process, after the baseband data is processed by the rf control module 10, the baseband data including the relevant register information is carried by the command signal (rf command) cmd_ agi and the data signal (rf data) data_ agi, and is sent to the rf functional module 11.
In this embodiment of the present application, the radio frequency control module splits each baseband data sequentially acquired from a baseband chip with a system clock as a reference into a radio frequency instruction and radio frequency data, where the radio frequency instruction includes register information; identifying each register information one by one to determine whether the register information is matched with the radio frequency function module; and under the condition that the register information is matched with the radio frequency function module, determining the radio frequency instruction and the radio frequency data as target radio frequency instruction and target radio frequency data. The data can be updated to the radio frequency functional module only by fewer signal wires without additional internal crystal oscillator, so that the complexity of the inside of the chip is reduced, the cost of the radio frequency front-end chip is reduced, and the radio frequency front-end chip has the characteristics of ultra-low time delay and high real-time performance. And data required by the radio frequency function module are transmitted, and the data not required by the radio frequency function module are not required to be transmitted, so that the data transmission quantity is reduced. Reducing unnecessary data transmission can reduce signal interference to the radio frequency function sub-module, thereby improving isolation of data transmission.
As shown in fig. 1, the radio frequency front end chip provided in the embodiment of the present application at least includes a radio frequency control module 10 and a radio frequency function module 11, where the radio frequency control module 10 and the radio frequency function module 11 are connected by signal lines, the number of the signal lines is smaller than the number of register bits of data to be transmitted, the signal lines include a start clock line and a data line,
here, the number of signal lines may be an integer smaller than the number of register bits of data to be transmitted and larger than 3. In the implementation process, the number of the data lines can be expanded based on actual requirements.
The radio frequency control module is used for acquiring baseband data from a baseband chip by taking a system clock as a reference and splitting the baseband data;
as shown in fig. 1, the radio frequency control module may acquire baseband data SDATA from the baseband chip 20 with reference to the system clock SCLK. And splitting the baseband data.
In some embodiments, the split baseband data comprises: the radio frequency instruction and the radio frequency data are respectively sent to the radio frequency function module through two data lines.
As shown in fig. 1, the baseband data may be split into an instruction signal (radio frequency instruction) cmd_ agi and a data signal (radio frequency data) data_ agi.
The radio frequency control module is also used for acquiring a system clock signal and transmitting the system clock signal to the radio frequency function module so as to synchronize the clock of the radio frequency function module with the system clock;
in the implementation process, as shown in fig. 1, the radio frequency control module 10 may send a system clock signal to the radio frequency function module 11, so that the clock of the radio frequency function module 11 may be synchronized with the system clock.
The radio frequency control module is further configured to send the split baseband data to the radio frequency function module in real time.
In the implementation process, the radio frequency control module 10 shown in fig. 1 splits baseband data into a command signal (radio frequency command) cmd_ agi and a data signal (radio frequency data) data_ agi in real time.
In some embodiments, the split baseband data comprises: a radio frequency instruction and a radio frequency data,
the radio frequency instruction is sent to the radio frequency function module through one data line;
in the implementation process, as shown in fig. 1, the radio frequency command and the radio frequency data may be sent to the radio frequency function module 11 through two different data lines, respectively.
And the radio frequency data are sent to the radio frequency function module through at least two data lines.
In some embodiments, the number of the data lines may be extended according to the actual situation, so that the radio frequency data with a larger data amount may be sent to the radio frequency function module through the extended data lines.
In some embodiments, the radio frequency function module decodes the radio frequency instruction and the radio frequency data based on the radio frequency clock signal to obtain a register address and register data;
the radio frequency function module configures the register data to a register corresponding to the register address.
In this embodiment of the present application, a radio frequency front end chip includes at least a radio frequency control module and a radio frequency function module, where the radio frequency control module and the radio frequency function module are connected by a signal line, the number of the signal lines is smaller than the number of register bits of data to be transmitted, the signal line includes a start clock line and a data line, and the radio frequency control module is configured to acquire baseband data from a baseband chip with a system clock as a reference, and split the baseband data; the radio frequency control module is also used for acquiring a system clock signal and transmitting the system clock signal to the radio frequency function module so as to synchronize the clock of the radio frequency function module with the system clock; the radio frequency control module is further configured to send the split baseband data to the radio frequency function module in real time. Therefore, the data can be updated to the radio frequency functional module only by fewer signal wires without additional internal crystal oscillator, the complexity in the chip is reduced, the cost of the radio frequency front-end chip is reduced, and the radio frequency front-end chip has the characteristics of ultra-low time delay and high instantaneity.
Fig. 2A is a schematic structural diagram of a radio frequency front end chip according to an embodiment of the present application, as shown in fig. 2A, the radio frequency control module 10 includes a sampling decoding submodule 106 and a data transmitting submodule 107,
the clock pin 101 of the sampling decoding submodule 106 is connected with the system clock pin 201 of the baseband chip 20, and the data pin 102 of the sampling decoding submodule 106 is connected with the baseband data pin 202 of the baseband chip 20;
the clock pin 1061 of the sampling decoding submodule 106 is connected with the clock pin 1071 of the data transmitting submodule 107; the data pin 1062 of the sampling decoding submodule 106 is connected with the data pin 1072 of the data transmitting submodule 107; an enable signal pin 1063 of the sampling decoding submodule 106 is connected with an enable signal pin 1073 of the data transmitting submodule 107;
the clock pin 103 of the data transmitting sub-module 107 is connected with the radio frequency clock pin 111 of the radio frequency functional module 11; the instruction pin 104 of the data sending sub-module 107 is connected with the radio frequency instruction pin 112 of the radio frequency function module 11; the data pin 105 of the data transmitting sub-module 107 is connected with the radio frequency data pin 113 of the radio frequency function module 11;
The radio frequency control module sends the system clock, the target radio frequency instruction and the target radio frequency data to the radio frequency function module, and the radio frequency control module comprises:
the sampling decoding submodule 106 controls the data transmitting submodule 107 to transmit the system clock, the target radio frequency instruction and the target radio frequency data to the radio frequency functional module 11 through control enable signals.
Fig. 2B is a schematic structural diagram of a rf front-end chip according to an embodiment of the present application, as shown in fig. 2B, the rf function module 11 includes an Agipi data receiving sub-module 114 and an rf function sub-module 115,
in the implementation process, the Agipi data receiving sub-module 114 receives the system clock, the target rf command and the target rf data sent by the data sending sub-module 107.
The rf functional submodule 115 may be any rf element such as an rf power amplifier, an rf low noise amplifier, an rf switch, a filter, or a duplexer.
In the implementation process, the Agipi data receiving sub-module 114 uses the reg_out signal to set a register corresponding to the rf function sub-module 115.
Fig. 2C is a timing chart of an Agipi interface according to an embodiment of the present application, as shown in fig. 2C, the timing chart includes a clock signal SCLK, a data signal SDATA, an ENABLE signal ENABLE, and a radio frequency clock signal clk_agipi, wherein,
In case the sampling decode sub-module 106 detects that there is baseband data to be transferred to the radio frequency function module, the ENABLE signal ENABLE is valid, the Agipi transmitting sub-module (data transmitting sub-module 107) generates a valid clk_ agi clock signal, which is derived from the SCLK clock signal of the RFFE interface, where the time-sequential relationship is synchronous, i.e. the generation source of the clock signal clk_agipi of the Agipi interface (interface between the data transmitting sub-module 107 and the radio frequency function module) is the clock signal SCLK of the RFFE interface.
As shown in fig. 2C, the rf functional module may complete decoding and storing of the baseband data before the falling edge of the last clock cycle of the clock signal clk_ agi. Namely, after the last bit of the baseband data of the RFFE interface is transmitted, the data of the radio frequency function module can be updated and stored after the delay of half clock period. This obviously greatly reduces the delay and improves the real-time performance of the system.
The Agipi interface uses three signal lines (cmd_agi, data_ agi and clk_ agi) to realize the transmission of baseband data, and no extra crystal oscillator is added to generate a clock for data transmission, so that the complexity in the chip is reduced, and meanwhile, certain cost is reduced.
In this embodiment of the present application, the sampling decoding submodule controls the data sending submodule to send the system clock, the target radio frequency instruction and the target radio frequency data to the radio frequency functional module through a control enable signal. Therefore, the three signal wires can be used for realizing the transmission of baseband data under the control of the enabling signals, the data transmission quantity is reduced, no extra crystal oscillator is added to generate a clock for data transmission, the complexity in a chip is reduced, and meanwhile, certain cost is reduced.
In some embodiments, as shown in fig. 2A, the radio frequency control module includes a sample decode sub-module 106 and a data transmit sub-module 107, wherein,
the radio frequency control module is further configured to acquire a system clock signal, and send the system clock signal to the radio frequency function module, so that a clock of the radio frequency function module is synchronized with the system clock, and includes:
the sampling decoding submodule 106 is configured to identify the baseband data, and send an enable signal to the data sending submodule when identifying the data required by the radio frequency functional module;
in the implementation process, since all the rf function modules of the rf front-end chip do not need all the baseband chip information (baseband data), the sampling decoding submodule 106 can identify the split baseband data, and when it is identified that the data needed by the rf function module exists, an enable signal is sent to the data sending submodule 107.
The data transmitting sub-module 107 is configured to transmit the system clock signal to the rf functional module in response to the enable signal.
In the implementation process, as shown in fig. 2A, the sampling decoding submodule 106 controls the data sending submodule 107 to send the system clock to the radio frequency functional module 11 through the control enable signal.
In the embodiment of the application, the sampling decoding submodule identifies the baseband data, and when the data required by the radio frequency function module is identified, an enabling signal is sent to the data sending submodule; and the data transmission sub-module is used for responding to the enabling signal and transmitting the system clock signal to the radio frequency functional module. Therefore, only when the baseband data is determined to be the data required by the radio frequency function module, the transmission of the baseband data is realized under the control of the enabling signal, the data transmission quantity is reduced, the unnecessary data transmission is reduced, and the signal interference to the radio frequency function sub-module can be reduced, so that the isolation degree of the data transmission is improved.
In some embodiments, the data transmitting sub-module is configured to transmit the system clock signal to the radio frequency functional module in response to the enable signal, and includes:
The data transmitting sub-module is further used for responding to the enabling signal and generating a radio frequency clock signal synchronous with the system clock signal;
the data transmitting sub-module is further configured to transmit the radio frequency clock signal to the radio frequency functional module.
In this embodiment of the present application, the data transmitting sub-module responds to the enable signal and generates a radio frequency clock signal synchronized with the system clock signal; and sending the radio frequency clock signal to the radio frequency function module. Therefore, no extra crystal oscillator is added to generate a clock for data transmission, so that the complexity in the chip is reduced, and meanwhile, certain cost is also reduced.
Fig. 3 is a schematic structural diagram of a rf front-end chip according to an embodiment of the present application, and as shown in fig. 3, the rf front-end chip includes an rf control module 10 and a plurality of rf functional modules 11,
the clock pin of the radio frequency control module 10 is connected with the radio frequency clock pin of each radio frequency function module 11; the instruction pins of the radio frequency control module 10 are connected with the radio frequency instruction pins of each radio frequency function module 11; the data pins of the radio frequency control module 10 are connected with the radio frequency data pins of each radio frequency function module 11;
In the case that the radio frequency control module 10 determines that the register information matches any one of the radio frequency function modules 11, determining the radio frequency instruction and the radio frequency data as a target radio frequency instruction and target radio frequency data;
the rf control module 10 transmits the system clock, the target rf command and the target rf data to each of the rf function modules 11.
As shown in fig. 3, the Agipi interface may also support a case where a plurality of rf function modules 10 located on different die are mounted on the same set of buses. At this time, the radio frequency control module 10 identifies all baseband data required by each radio frequency functional module 10, specifically, which baseband data each radio frequency functional module applies, and after each radio frequency functional module receives all the identified baseband data, the radio frequency functional module automatically discriminates, so that each radio frequency functional module obtains the baseband data corresponding to itself, and the configuration of the corresponding register is completed.
In the embodiment of the application, the radio frequency front-end chip comprises a radio frequency control module and a plurality of radio frequency function modules, wherein a clock pin of the radio frequency control module is connected with a radio frequency clock pin of each radio frequency function module; the instruction pin of the radio frequency control module is connected with the radio frequency instruction pin of each radio frequency function module; the data pin of the radio frequency control module is connected with the radio frequency data pin of each radio frequency function module; under the condition that the radio frequency control module determines that the register information is matched with any radio frequency function module, determining the radio frequency instruction and the radio frequency data as a target radio frequency instruction and target radio frequency data; the radio frequency control module sends the system clock, the target radio frequency instruction and the target radio frequency data to each radio frequency function module. Therefore, a plurality of radio frequency function modules can be mounted on the same group of buses, and each radio frequency function module can acquire corresponding baseband data.
In some embodiments, the radio frequency front end chip comprises one of the radio frequency control modules and a plurality of the radio frequency function modules,
the radio frequency control module is configured to acquire a system clock signal and send the system clock signal to the radio frequency function module, so that a clock of the radio frequency function module is synchronized with the system clock, and includes:
the radio frequency control module is used for acquiring a system clock signal and sending the system clock signal to each radio frequency function module so as to synchronize the clock of each radio frequency function module with the system clock.
The radio frequency control module is further configured to send the split baseband data to the radio frequency function module in real time, and includes:
the radio frequency control module is further configured to send the split baseband data to each radio frequency function module in real time.
In the implementation process, as shown in fig. 3, the Agipi interface may also support a case that a plurality of radio frequency function modules 10 located on different die are mounted on the same group of buses. The radio frequency control module 10 identifies all the baseband data required by each radio frequency function module 10, specifically which baseband data each radio frequency function module applies.
In some embodiments, after each radio frequency function module receives all the identified baseband data, the radio frequency function modules automatically screen the baseband data so that each radio frequency function module obtains the baseband data corresponding to the radio frequency function module and completes the configuration of the corresponding register.
In some embodiments, after identifying all the baseband data required by each rf functional module 10, and specifically what baseband data each rf functional module applies, the rf control module 10 may send the baseband data required by each rf functional module 10 to the corresponding rf functional module, so that each rf functional module only obtains the baseband data corresponding to itself, and completes configuration of the corresponding register.
The embodiment of the application provides a serial communication method, which is applied to a radio frequency front end chip, wherein the radio frequency front end chip at least comprises a radio frequency control module and a radio frequency function module, the radio frequency control module is connected with the radio frequency function module through signal lines, the number of the signal lines is smaller than the number of register bits of data to be transmitted, and the signal lines comprise a start clock line and a data line, as shown in fig. 4, the method comprises the following steps:
step S410, the radio frequency control module takes a system clock as a reference to acquire baseband data from a baseband chip, and splits the baseband data;
In some embodiments, the split baseband data comprises: the radio frequency instruction and the radio frequency data are respectively sent to the radio frequency function module through two data lines.
In some embodiments, the split baseband data comprises: a radio frequency instruction and a radio frequency data,
the radio frequency instruction is sent to the radio frequency function module through one data line;
and the radio frequency data are sent to the radio frequency function module through at least two data lines.
Step S420, the radio frequency control module acquires a system clock signal and sends the system clock signal to the radio frequency function module so as to synchronize the clock of the radio frequency function module with the system clock;
step S430, the radio frequency control module sends the split baseband data to the radio frequency function module in real time.
In the embodiment of the application, the radio frequency control module acquires baseband data from a baseband chip by taking a system clock as a reference, and splits the baseband data; the radio frequency control module acquires a system clock signal and sends the system clock signal to the radio frequency function module so as to synchronize the clock of the radio frequency function module with the system clock; and the radio frequency control module sends the split baseband data to the radio frequency function module in real time. The data can be updated to the radio frequency function module only by fewer signal wires without additional internal crystal oscillator, and the device has the characteristic of ultra-low time delay. And data required by the radio frequency function module are transmitted, and the data not required by the radio frequency function module are not required to be transmitted, so that the data transmission quantity is reduced. Reducing unnecessary data transmission can reduce signal interference to the radio frequency function sub-module, thereby improving isolation thereof.
In some embodiments, the serial port communication method further comprises the steps of:
step S450, the radio frequency function module decodes the radio frequency instruction and the radio frequency data based on the radio frequency clock signal to obtain a register address and register data;
step S460, the radio frequency function module configures the register data to a register corresponding to the register address.
In the embodiment of the application, the radio frequency function module decodes the radio frequency instruction and the radio frequency data based on the radio frequency clock signal to obtain a register address and register data; the radio frequency function module configures the register data to a register corresponding to the register address. In this way, the configuration of the corresponding register of the radio frequency function module can be achieved by using the acquired baseband signal.
In some embodiments, the radio frequency front end chip includes a radio frequency control module and a plurality of radio frequency function modules,
the step S420 "the rf control module obtains the system clock signal and sends the system clock signal to the rf functional module, so that the clock of the rf functional module is synchronized with the system clock" may be implemented by the following steps:
The radio frequency control module acquires a system clock signal and sends the system clock signal to each radio frequency function module so as to synchronize the clock of each radio frequency function module with the system clock.
The step S430 "the radio frequency control module sends the split baseband data to the radio frequency function module in real time" may be implemented by the following processes:
and the radio frequency control module sends the split baseband data to each radio frequency function module in real time.
In this embodiment of the present application, a radio frequency control module obtains a system clock signal, and sends the system clock signal to each radio frequency function module, so that a clock of each radio frequency function module is synchronized with a system clock; and the radio frequency control module sends the split baseband data to each radio frequency function module in real time. Therefore, a plurality of radio frequency function modules can be mounted on the same group of buses, and each radio frequency function module can acquire corresponding baseband data.
Based on the foregoing embodiments, the embodiments of the present application provide a serial communication device, where the device includes each module, each module includes each sub-module, and the module may be implemented by a processor in an electronic device; of course, the method can also be realized by a specific logic circuit; in practice, the processor may be a central processing unit (Central Processing Unit, CPU), microprocessor (Microprocessor Unit, MPU), digital signal processor (Digital Signal Process, DSP) or field programmable gate array (Field Programmable Gate Array, FPGA), etc.
Fig. 5 is a schematic diagram of a composition structure of a serial communication device according to an embodiment of the present application, as shown in fig. 5, the device 500 includes:
the radio frequency control module 510 is configured to acquire baseband data from a baseband chip with reference to a system clock, and split the baseband data;
the radio frequency control module 510 is further configured to acquire a system clock signal, and send the system clock signal to the radio frequency functional module, so that a clock of the radio frequency functional module is synchronized with a system clock;
the radio frequency control module 510 is further configured to send the split baseband data to the radio frequency function module 520 in real time.
In some implementations, the radio frequency control module 510 includes a sampling decoding submodule and a data sending submodule, where the sampling decoding submodule is configured to identify the baseband data, and send an enable signal to the data sending submodule when identifying the data required by the radio frequency functional module. The data transmitting sub-module is used for responding to the enabling signal and transmitting the system clock signal to the radio frequency functional module.
In some embodiments, the data transmission sub-module is further configured to respond to the enable signal and generate a radio frequency clock signal synchronized with the system clock signal;
The data transmitting sub-module is further configured to transmit the radio frequency clock signal to the radio frequency function module 520.
The description of the apparatus embodiments above is similar to that of the method embodiments above, with similar advantageous effects as the method embodiments. For technical details not disclosed in the device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.
It should be noted that, in the embodiment of the present application, if the method is implemented in the form of a software functional module, and sold or used as a separate product, the method may also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied essentially or in a part contributing to the related art in the form of a software product stored in a storage medium, including several instructions for causing an electronic device (which may be a mobile phone, a tablet computer, a notebook computer, a desktop computer, etc.) to perform all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.
Accordingly, embodiments of the present application provide a storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the serial communication method provided in the above embodiments.
Correspondingly, an electronic device is provided in the embodiment of the present application, fig. 6 is a schematic diagram of a hardware entity of the electronic device provided in the embodiment of the present application, and as shown in fig. 6, the hardware entity of the device 600 includes: comprising a memory 601 and a processor 602, said memory 601 storing a computer program executable on the processor 602, said processor 602 implementing the steps in the serial communication method provided in the above embodiments when said program is executed.
The memory 601 is configured to store instructions and applications executable by the processor 602, and may also cache data (e.g., image data, audio data, voice communication data, and video communication data) to be processed or processed by the processor 602 and the modules in the electronic device 600, which may be implemented by a FLASH memory (FLASH) or a random access memory (Random Access Memory, RAM).
It should be noted here that: the description of the storage medium and apparatus embodiments above is similar to that of the method embodiments described above, with similar benefits as the method embodiments. For technical details not disclosed in the embodiments of the storage medium and the apparatus of the present application, please refer to the description of the method embodiments of the present application for understanding.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present application, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present application. The foregoing embodiment numbers of the present application are merely for describing, and do not represent advantages or disadvantages of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units; can be located in one place or distributed to a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, where the program, when executed, performs steps including the above method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read Only Memory (ROM), a magnetic disk or an optical disk, or the like, which can store program codes.
Alternatively, the integrated units described above may be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied essentially or in a part contributing to the related art in the form of a software product stored in a storage medium, including several instructions for causing an electronic device (which may be a mobile phone, a tablet computer, a notebook computer, a desktop computer, etc.) to perform all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a removable storage device, a ROM, a magnetic disk, or an optical disk.
The methods disclosed in the several method embodiments provided in the present application may be arbitrarily combined without collision to obtain a new method embodiment.
The features disclosed in the several product embodiments provided in the present application may be combined arbitrarily without conflict to obtain new product embodiments.
The features disclosed in the several method or apparatus embodiments provided in the present application may be arbitrarily combined without conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely an embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (12)
1. The radio frequency front end chip is characterized by at least comprising a radio frequency control module and a radio frequency function module, wherein the radio frequency control module and the radio frequency function module are connected through signal lines, the number of the signal lines is smaller than the number of register bits of data to be transmitted, the signal lines comprise a start clock line and a data line,
The radio frequency control module is used for acquiring baseband data from a baseband chip by taking a system clock as a reference and splitting the baseband data;
the radio frequency control module is also used for acquiring a system clock signal and transmitting the system clock signal to the radio frequency function module so as to synchronize the clock of the radio frequency function module with the system clock;
the radio frequency control module is further configured to send the split baseband data to the radio frequency function module in real time.
2. The radio frequency front-end chip of claim 1, wherein the split baseband data comprises: the radio frequency instruction and the radio frequency data are respectively sent to the radio frequency function module through two data lines.
3. The radio frequency front-end chip of claim 1, wherein the split baseband data comprises: a radio frequency instruction and a radio frequency data,
the radio frequency instruction is sent to the radio frequency function module through one data line;
and the radio frequency data are sent to the radio frequency function module through at least two data lines.
4. The radio frequency front end chip of claim 1, wherein the radio frequency control module comprises a sample decoding sub-module and a data transmission sub-module,
The radio frequency control module is further configured to acquire a system clock signal, and send the system clock signal to the radio frequency function module, so that a clock of the radio frequency function module is synchronized with the system clock, and includes:
the sampling decoding submodule is used for identifying the baseband data, and sending an enabling signal to the data sending submodule when the data required by the radio frequency functional module is identified;
the data transmitting sub-module is used for responding to the enabling signal and transmitting the system clock signal to the radio frequency functional module.
5. The radio frequency front end chip of claim 4, wherein the data transmission sub-module for transmitting the system clock signal to the radio frequency functional module in response to the enable signal comprises:
the data transmitting sub-module is further used for responding to the enabling signal and generating a radio frequency clock signal synchronous with the system clock signal;
the data transmitting sub-module is further configured to transmit the radio frequency clock signal to the radio frequency functional module.
6. The RF front-end chip of claim 1, wherein the RF front-end chip comprises one of the RF control modules and a plurality of the RF function modules,
The radio frequency control module is configured to acquire a system clock signal and send the system clock signal to the radio frequency function module, so that a clock of the radio frequency function module is synchronized with the system clock, and includes:
the radio frequency control module is used for acquiring a system clock signal and sending the system clock signal to each radio frequency function module so as to synchronize the clock of each radio frequency function module with the system clock;
the radio frequency control module is further configured to send the split baseband data to the radio frequency function module in real time, and includes:
the radio frequency control module is further configured to send the split baseband data to each radio frequency function module in real time.
7. The serial communication method is applied to a radio frequency front end chip, and is characterized in that the radio frequency front end chip at least comprises a radio frequency control module and a radio frequency function module, the radio frequency control module and the radio frequency function module are connected through signal lines, the number of the signal lines is smaller than the number of register bits of data to be transmitted, the signal lines comprise a start clock line and a data line, and the method comprises the following steps:
the radio frequency control module takes a system clock as a reference to acquire baseband data from a baseband chip and splits the baseband data;
The radio frequency control module acquires a system clock signal and sends the system clock signal to the radio frequency function module so as to synchronize the clock of the radio frequency function module with the system clock;
and the radio frequency control module sends the split baseband data to the radio frequency function module in real time.
8. The method of claim 7, wherein the split baseband data comprises: the radio frequency instruction and the radio frequency data are respectively sent to the radio frequency function module through two data lines.
9. The method of claim 7, wherein the split baseband data comprises: a radio frequency instruction and a radio frequency data,
the radio frequency instruction is sent to the radio frequency function module through one data line;
and the radio frequency data are sent to the radio frequency function module through at least two data lines.
10. The method of claim 7, wherein said RF front-end chip includes one of said RF control modules and a plurality of said RF function modules,
the radio frequency control module obtains a system clock signal and sends the system clock signal to the radio frequency function module so as to synchronize the clock of the radio frequency function module with the system clock, and the radio frequency control module comprises:
The radio frequency control module acquires a system clock signal and sends the system clock signal to each radio frequency function module so as to synchronize the clock of each radio frequency function module with the system clock;
the radio frequency control module sends the split baseband data to the radio frequency function module in real time, and the radio frequency control module comprises:
and the radio frequency control module sends the split baseband data to each radio frequency function module in real time.
11. An electronic device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that the processor implements the steps of the method of any of claims 7 to 10 when the program is executed.
12. A storage medium having stored thereon executable instructions for causing a processor to perform the steps of the method of any one of claims 7 to 10.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211720199.6A CN116015333B (en) | 2022-12-30 | 2022-12-30 | Radio frequency front-end chip, serial communication method, device and storage medium |
| PCT/CN2023/124361 WO2024139536A1 (en) | 2022-12-30 | 2023-10-12 | Radio frequency front-end chip, serial communication method, device and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211720199.6A CN116015333B (en) | 2022-12-30 | 2022-12-30 | Radio frequency front-end chip, serial communication method, device and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116015333A true CN116015333A (en) | 2023-04-25 |
| CN116015333B CN116015333B (en) | 2024-04-16 |
Family
ID=86036855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211720199.6A Active CN116015333B (en) | 2022-12-30 | 2022-12-30 | Radio frequency front-end chip, serial communication method, device and storage medium |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN116015333B (en) |
| WO (1) | WO2024139536A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024139536A1 (en) * | 2022-12-30 | 2024-07-04 | 广州慧智微电子股份有限公司 | Radio frequency front-end chip, serial communication method, device and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109032980A (en) * | 2018-06-30 | 2018-12-18 | 唯捷创芯(天津)电子技术股份有限公司 | Serial communication apparatus and serial communication method |
| CN109902056A (en) * | 2019-01-31 | 2019-06-18 | 郑州云海信息技术有限公司 | A kind of method, apparatus of serial transmission, equipment and computer readable storage medium |
| CN112988634A (en) * | 2019-12-02 | 2021-06-18 | 深圳市中兴微电子技术有限公司 | Multi-antenna channel device and configuration method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102045156B (en) * | 2010-11-18 | 2014-12-10 | 和芯星通科技(北京)有限公司 | Method and device for multi-module synchronous processing of digital signals |
| US11357005B2 (en) * | 2019-10-09 | 2022-06-07 | Cisco Technology, Inc. | Integration of a Wi-Fi access point with a cellular radio unit |
| CN114936112B (en) * | 2022-07-22 | 2022-10-11 | 深圳市国芯物联科技有限公司 | Control method of passive ultrahigh frequency electronic tag chip digital baseband processor |
| CN116015333B (en) * | 2022-12-30 | 2024-04-16 | 广州慧智微电子股份有限公司 | Radio frequency front-end chip, serial communication method, device and storage medium |
-
2022
- 2022-12-30 CN CN202211720199.6A patent/CN116015333B/en active Active
-
2023
- 2023-10-12 WO PCT/CN2023/124361 patent/WO2024139536A1/en unknown
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109032980A (en) * | 2018-06-30 | 2018-12-18 | 唯捷创芯(天津)电子技术股份有限公司 | Serial communication apparatus and serial communication method |
| CN109902056A (en) * | 2019-01-31 | 2019-06-18 | 郑州云海信息技术有限公司 | A kind of method, apparatus of serial transmission, equipment and computer readable storage medium |
| CN112988634A (en) * | 2019-12-02 | 2021-06-18 | 深圳市中兴微电子技术有限公司 | Multi-antenna channel device and configuration method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024139536A1 (en) * | 2022-12-30 | 2024-07-04 | 广州慧智微电子股份有限公司 | Radio frequency front-end chip, serial communication method, device and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024139536A1 (en) | 2024-07-04 |
| CN116015333B (en) | 2024-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12067767B2 (en) | Buses for pattern-recognition processors | |
| US20190306905A1 (en) | Bluetooth connection method, device and smart terminal | |
| CN111651384B (en) | Register reading and writing method, chip, subsystem, register set and terminal | |
| US9430434B2 (en) | System and method for conserving memory power using dynamic memory I/O resizing | |
| KR20180075507A (en) | Radio frequency front end devices having a high data rate mode | |
| US11334134B2 (en) | Integrated circuit | |
| US11119960B2 (en) | Adapter to concatenate connectors | |
| CN116015333B (en) | Radio frequency front-end chip, serial communication method, device and storage medium | |
| US10423551B2 (en) | Ultra-short RFFE datagrams for latency sensitive radio frequency front-end | |
| JP2021519009A (en) | Transmission method, device, and storage medium for synchronous signal blocks | |
| EP3403377A1 (en) | Signaling protocols for radio frequency front-end control interface (rffe) buses | |
| US8171186B1 (en) | On-chip interconnect fabric | |
| US20190346876A1 (en) | Sharing a serial bus interface among devices having different operating speeds | |
| US9990317B2 (en) | Full-mask partial-bit-field (FM-PBF) technique for latency sensitive masked-write | |
| US20090138673A1 (en) | Internal memory mapped external memory interface | |
| CN110726924B (en) | Chip operation method and device | |
| CN116933723A (en) | Multi-core processor verification system | |
| CN112416843A (en) | Backboard communication equipment, control method thereof and storage medium | |
| CN111782989A (en) | Fast application association method and related device | |
| US20240259457A1 (en) | Multimedia data transmission apparatus and method | |
| US8006012B2 (en) | Data storage system | |
| CN117389923A (en) | SD memory card transmission delay tuning method and device, readable storage medium and terminal | |
| CN118554967A (en) | Radio frequency device and control signal transmission method | |
| CN115457998A (en) | MIPI RFFE interface address expansion circuit, method and related equipment | |
| CN104679697A (en) | File reading method and device, optical drive driver board and optical drive equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |