CN116013991A - Micro-nano multiport ion gate dielectric synaptic transistor and preparation method thereof - Google Patents
Micro-nano multiport ion gate dielectric synaptic transistor and preparation method thereof Download PDFInfo
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- CN116013991A CN116013991A CN202211674014.2A CN202211674014A CN116013991A CN 116013991 A CN116013991 A CN 116013991A CN 202211674014 A CN202211674014 A CN 202211674014A CN 116013991 A CN116013991 A CN 116013991A
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Abstract
The invention relates to the technical field of transistors, in particular to a micro-nano multiport ion gate dielectric synaptic transistor and a preparation method thereof, wherein the micro-nano multiport ion gate dielectric synaptic transistor comprises an indium tin oxide conducting layer, an amorphous indium gallium zinc oxide metal oxide channel layer and an ion gate dielectric gel layer, and the transistor adopts a coplanar structure design; the main gates G1, G2, G3 and G4 of the synaptic transistors are multiport signal input ends and are used for simulating a presynaptic membrane of a biological synapse; the conductance between the source and drain is used to simulate the synaptic weight of a biological synapse; the side grating modulation end is used for simulating the modulation function of the biological downlink channel on the nervous system. The invention designs a novel micro-nano multiport ion gate dielectric synaptic transistor device aiming at the problems of insufficient calculation force and the like in the emerging fields of nerve artificial limbs, brain-computer interfaces, nerve robots and the like, and is mainly used for realizing the real-time processing of multimode mimicry nerve signals in microelectronics so as to improve the overall output transmission, calculation and storage capacity.
Description
Technical Field
The invention relates to the technical field of transistors, in particular to a micro-nano multiport ion gate dielectric synaptic transistor and a preparation method thereof.
Background
Compared with the traditional intelligent system using the von Neumann structure, the human body perception nervous system has stronger data parallel processing capability, has the perception information processing function of integrating storage and operation, and has the advantages of fault tolerance, energy conservation, robustness, event driving and the like when dealing with real-time big data information flow, and has recently been widely focused in academia. The integrated electronic device of the mimicry sensing nerve with similar functions is prepared by referring to and simulating the working mode of the biological nervous system, and is applied to future intelligent equipment, so that timely and efficient sensing and processing of environmental information in the real world can be realized, and the traditional electronic equipment can be effectively prevented from falling into the von neumann bottleneck. Therefore, the comprehensive research on the bionic nervous system is developed and the combination of the bionic nervous system and intelligent electronic equipment is explored, and the bionic nervous system has great research and potential industrialization significance on the development of the fields of next-generation nerve prostheses, human-computer interfaces, humanoid robots and the like.
Synapses are structures of interconnections between neurons that play an important role in a biological sensing system, and adjustable synaptic weights are the basis for achieving biological sensing signal processing. In recent years, scientists have focused on developing biomimetic neural systems based on synaptic devices. Various electronic devices are used for constructing artificial synapses, memristors with two-terminal structures and synaptic transistors with multi-terminal structures are two main types of synaptic devices, and the synaptic transistors can realize parallel learning and are easier to realize advanced synaptic functions. The ion migration process of the electric double-layer synaptic transistor is very similar to that of biological synapse, and these advantages make them ideal data processing nodes for developing bionic sensing system, so that the development of nerve morphology device of this type is receiving great attention.
Disclosure of Invention
Aiming at the defects of the existing algorithm, the invention designs a novel micro-nano multiport ion gate dielectric synaptic transistor device aiming at the problems of insufficient calculation power and the like in the emerging fields of nerve artificial limb, brain-computer interface, nerve robot and the like, and is mainly used for realizing the real-time processing of multimode mimicry nerve signals in microelectronics so as to improve the overall output transmission, calculation and storage capacity.
The technical scheme adopted by the invention is as follows: a micro-nano multiport ion gate dielectric synaptic transistor comprising: the transistor adopts a coplanar structure design; the main gates G1, G2, G3 and G4 of the synaptic transistors are multiport signal input ends and are used for simulating a presynaptic membrane of a biological synapse; the conductance between the source and drain is used to simulate the synaptic weight of a biological synapse; the side grating modulation end is used for simulating the modulation function of the biological downlink channel on the nervous system.
The preparation method of the micro-nano multiport ion gate dielectric synaptic transistor comprises the following steps:
firstly, performing patterning deposition of IGZO on a silicon oxide wafer by means of a metal mask plate in a magnetron sputtering mode to form a channel layer of a synaptic transistor;
further, the parameters of the magnetron sputtering mode are set to be 100W power for sputtering under argon atmosphere for the first time, and the working pressure of the cavity is 0.5Pa.
Secondly, forming an electrode layer on the semi-finished product in the first step by means of patterning and depositing ITO (indium tin oxide) by a metal mask plate in a magnetron sputtering mode;
further, setting the working pressure of the cavity to 0.8Pa in the argon atmosphere again through the parameters of the magnetron sputtering mode;
step three, annealing treatment is carried out, so that better ohmic contact is realized for the two layers of materials;
further, the annealing temperature is set to 300 ℃ for 3 hours;
step four, adopting the dispensing function of the microelectronic ink-jet printer to directly print a gate medium on the semi-finished product after the step three in a patterning way;
further, specific materials of the inkjet are: an organic mixture of ionic liquid, photoinitiator hoppa and polymer PEGDA.
And step five, irradiating the semi-finished product prepared in the step four in an ultraviolet curing box, and crosslinking the polymer top gate dielectric under ultraviolet irradiation to obtain the novel synaptic transistor.
The invention has the beneficial effects that:
1. the synaptic transistor is based on the double-layer effect of ionic gel, and has the characteristics of ultra-large gate capacitance of mu F/cm < -2 > level, high carrier density and low power consumption compared with the traditional transistor;
2. the response test of various single/multi-pulse excitation signals is realized, and the simulation of various nerve synaptic behaviors, such as the functions of postsynaptic excitation current, bipulse facilitation, post-rigidity enhancement and the like, are realized;
3. the channel layer of the synaptic transistor can respond to optical stimulus and electric stimulus and can be applied to different application scenes;
4. the structure that the gate dielectric covers the top of the device can isolate the environmental interference so as to greatly enhance the stability and the service life of the synaptic transistor;
5. the preparation process of the synaptic transistor can realize the preparation of wafer-level large-scale transistors and is compatible with the traditional transistor preparation process.
Drawings
FIG. 1 is an internal block diagram (top view) of a synaptic transistor of the present invention;
FIG. 2 is an internal block diagram (side view) of a synaptic transistor of the present invention;
fig. 3 is a schematic representation of the electric double layer effect of the present invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings and examples, which are simplified schematic illustrations showing only the basic structure of the invention and thus showing only those constructions that are relevant to the invention.
As shown in fig. 1 and 2, a micro-nano multiport ion gate dielectric synaptic transistor comprises: a conductive layer of Indium Tin Oxide (ITO), an amorphous indium gallium zinc oxide (a-IGZO) metal oxide channel layer and an ion gate dielectric gel layer, and the whole transistor adopts a coplanar structure design; wherein the main gate (G1, G2, G3, G4) of the synaptic transistor is a multi-port signal input of the transistor for simulating a pre-synaptic membrane of a biological synapse; the conductance between the source (S) and the drain (D) is used to simulate the synaptic weight of a biological synapse; the side grating modulation end (Gm) is used for simulating the modulation function of the biological downlink channel on the nervous system.
Compared with the laminated structure of the traditional transistor device, the novel coplanar multi-grid input structure of the invention has the advantages that all electrodes of the transistor device and a channel layer are in the same horizontal plane, and signal input integration and modulation are facilitated by means of a lateral ion coupling mechanism of an ionic medium; in addition, each electrode and the channel layer are on the same horizontal plane, so that the process complexity of the packaging stage is greatly simplified in terms of the process.
The ion gate dielectric synaptic transistor is mainly based on the double-layer effect generated by the ion gel gate dielectric and can realize the advancing ultra-low working voltage (lower than 1V) and the nerve morphology calculation function; as shown in FIG. 3, a specific process of generating the electric double layer effect is depicted, and under the drive of an external electric field, anions and cations contained in the ion gate dielectric layer can rapidly and gradually migrate to the interface, and finally form a compact electric double layer with a spacing of only nm level at the interface of a channel/electrolyte and a gate/dielectric, and generate mu F/cm -2 And the ultra-large gate capacitance of the level, thereby reducing the power consumption of the whole device.
When the device is used, the ports G1, G2, G3 and G4 can be selected to be single or multiple, and forward mimicry nerve voltage pulse sequences can be applied independently or simultaneously, and the comprehensive treatment and analysis of the data stream can be carried out by means of the side gate coupling characteristic of the solid ion gate medium; under the influence of a forward voltage pulse, cations in the ion gate medium migrate to a channel, exciting postsynaptic current (EPSC) is induced in the channel, when the voltage pulse is withdrawn, the induced ions move reversely and return to an initial state, at the moment, the channel current still acts on incompletely reset ions, and the EPSC signal slowly drops.
In addition, in the use process, positive or negative constant voltage electric signals can be applied to the Gm port at the same time, so that the enhancement or inhibition adjustment of the output characteristics of the whole device can be performed; for example, under the action of positive voltage, more carriers are induced in the channel, so that the output signal of the device is improved, and negative voltage plays a role in reverse.
Under the action of a plurality of voltage pulses, positive ions and negative ions at the gate dielectric/channel interface and the gate/gate dielectric gradually drift back to the equilibrium state after the excitatory current generated by the first pulse. If the next voltage pulse arrives in the process, part of ions which do not return are overlapped with the quantity of the ions excited at the time, more carriers are induced in the channel, so that the exciting postsynaptic current triggered at the time is stronger, and the phenomena of double pulse facilitation and the like are generated.
When a plurality of signal input ends are used for inputting the nerve pulse sequence, nonlinear superposition effect can be generated, and the finally obtained data output value is far greater than the linear value obtained by independently applying signals to each signal input end, so that the ion gate medium synaptic transistor is more suitable for carrying out nerve morphology calculation.
The preparation method of the micro-nano multiport ion gate dielectric synaptic transistor comprises the following steps:
firstly, performing patterning deposition of IGZO on a silicon oxide wafer by means of a metal mask plate in a magnetron sputtering mode to form a channel layer of a synaptic transistor;
the magnetron sputtering parameters are set to be 100W power and 0.5Pa cavity working pressure in argon atmosphere;
secondly, forming an electrode layer on the semi-finished product in the first step by means of patterning and depositing ITO (indium tin oxide) by a metal mask plate in a magnetron sputtering mode;
the magnetron sputtering parameters are set to be 0.8Pa of cavity working pressure under the argon atmosphere;
step three, annealing treatment is carried out, so that better ohmic contact is realized for the two layers of materials;
the temperature is set to 300 ℃ for 3 hours;
step four, adopting the dispensing function of the microelectronic ink-jet printer to directly print a gate medium on the semi-finished product after the step three in a patterning way;
the specific materials of the ink adopted in the step are as follows: an organic mixture of ionic liquid [ EMIM ] [ TFSI ] (1-methyl-3-methylimidazolium bis (tri-fluoro-sulfonyl) imide), photo-initiator hopp (2-hydroxy-2-methyl-prophioquinone), and polymer PEGDA (polyethylene glycol diacrylate).
And step five, irradiating the semi-finished product prepared in the step four in an ultraviolet curing box, and crosslinking the polymer top gate dielectric under ultraviolet irradiation to obtain the novel synaptic transistor.
With the above-described preferred embodiments according to the present invention as an illustration, the above-described descriptions can be used by persons skilled in the relevant art to make various changes and modifications without departing from the scope of the technical idea of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.
Claims (6)
1. A micro-nano multiport ion gate dielectric synaptic transistor comprising: the transistor adopts a coplanar structure design; the main gates G1, G2, G3 and G4 of the synaptic transistors are multiport signal input ends and are used for simulating a presynaptic membrane of a biological synapse; the conductance between the source and drain is used to simulate the synaptic weight of a biological synapse; the side grating modulation end is used for simulating the modulation function of the biological downlink channel on the nervous system.
2. The method for preparing the micro-nano multiport ion gate dielectric synaptic transistor according to claim 1, comprising the steps of:
firstly, performing patterning deposition of IGZO on a silicon oxide wafer by means of a metal mask plate in a magnetron sputtering mode to form a channel layer of a synaptic transistor;
secondly, forming an electrode layer on the semi-finished product in the first step by means of patterning and depositing ITO (indium tin oxide) by a metal mask plate in a magnetron sputtering mode;
step three, annealing treatment is carried out, so that better ohmic contact is realized for the two layers of materials;
step four, adopting the dispensing function of the microelectronic ink-jet printer to directly print a gate medium on the semi-finished product after the step three in a patterning way;
and step five, irradiating the semi-finished product prepared in the step four in an ultraviolet curing box, and crosslinking the polymer top gate dielectric under ultraviolet irradiation to obtain the novel synaptic transistor.
3. The method for preparing the micro-nano multiport ion gate dielectric synaptic transistor according to claim 1, wherein the parameter of the magnetron sputtering mode is set to be 100W power for sputtering under argon atmosphere for the first time, and the working pressure of the cavity is 0.5Pa.
4. The method for preparing the micro-nano multiport ion gate dielectric synaptic transistor according to claim 1, wherein the method is characterized in that: and setting the working pressure of the cavity to 0.8Pa in the argon atmosphere by the parameters of the magnetron sputtering mode.
5. The method for preparing the micro-nano multiport ion gate dielectric synaptic transistor according to claim 1, wherein the method is characterized in that: the temperature of the annealing was set at 300 degrees celsius for 3 hours.
6. The method for preparing the micro-nano multiport ion gate dielectric synaptic transistor according to claim 1, wherein the method is characterized in that: the specific materials of the inkjet are: an organic mixture of ionic liquid, photoinitiator hoppa and polymer PEGDA.
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