CN117042552A

CN117042552A - Electrolyte grid-controlled transistor array, high-precision integration method thereof, quasi-solid electrolyte with high ion conductivity and application thereof

Info

Publication number: CN117042552A
Application number: CN202311041153.6A
Authority: CN
Inventors: 李俊; 雷宇星; 张志林
Original assignee: University of Shanghai for Science and Technology
Current assignee: University of Shanghai for Science and Technology
Priority date: 2023-08-17
Filing date: 2023-08-17
Publication date: 2023-11-10

Abstract

The invention belongs to the technical field of electronic devices, and particularly relates to an electrolyte grid-control transistor array, a high-precision integration method thereof, a quasi-solid electrolyte with high ion conductivity and application thereof. The electrolyte gate control synaptic transistor array prepared by the integration method is different from the traditional transistor with the top gate structure or the bottom gate structure, the grid electrode of the electrolyte gate control synaptic transistor array is not in the vertical area of the transistor channel, the process steps are simplified while the array wiring is convenient, and the grid electrode medium of the transistor is arranged at the top and can be prepared finally, so that the large-array and high-precision preparation of the composite functional structure can be realized before the grid electrode medium is arranged, the incompatibility between the photoetching process and the liquid or quasi-solid electrolyte gate medium is avoided, and the integration method is simplified. Meanwhile, an extra isolation layer is introduced between the grid electrode and the source electrode and the drain electrode in the device structure, so that the grid electrode and the source electrode and the drain electrode are isolated, and crosstalk between the two layers of electrodes is avoided.

Description

Electrolyte grid-controlled transistor array, high-precision integration method thereof, quasi-solid electrolyte with high ion conductivity and application thereof

Technical Field

The invention belongs to the technical field of electronic devices, and particularly relates to an electrolyte grid-control transistor array, a high-precision integration method thereof, a quasi-solid electrolyte with high ion conductivity and application thereof.

Background

Inspired by the high parallelism, low energy consumption and integration of human brain, researchers try to imitate human brain to perform brain-like calculation. Synapses in the human brain are the fundamental unit of information transfer and processing, and thus simulating synapses with electronics is the basis for achieving brain-like calculations. Among the electronic devices currently proposed for simulating synapses, the electrolytic gate-controlled transistor synapse device is capable of simulating synapses while processing a plurality of signals, combining learning and memory functions, and at the same time is capable of realizing a neural network based on capacitive coupling. In contrast to conventional thin film transistors, the electrolyte gated transistor has an electrolyte material as the gate dielectric. Under the action of gate voltage, movable ions or protons in the electrolyte can directionally migrate, so that a compact double electric layer is generated at the interface of the active layer and the gate dielectric layer, and the double electric layer can enable the device to work under extremely low driving voltage and is also a reason that the electrolyte gate control transistor can simulate the synaptic function.

Currently, many studies are expanding around improving the performance of single-electrolyte-gated transistor synapse devices, but there are few schemes for integrating multiple-electrolyte-gated transistor synapse devices. The gate dielectric quasi-solid electrolyte material is difficult to be compatible with the current photoetching technology, and most of the existing integration schemes are small-array and low-precision schemes, and large-array and high-precision integration schemes are to be developed.

Disclosure of Invention

The invention aims to provide an electrolyte grid-controlled transistor array, a high-precision integration method thereof and a quasi-solid electrolyte with high ion conductivity and application thereof.

In order to achieve the above object, the present invention provides the following technical solutions:

the invention provides a high-precision integration method of an electrolyte grid-controlled transistor array, which comprises the following steps:

preparing a source electrode and a drain electrode on the surface of a substrate; a channel position is arranged between the source electrode and the drain electrode of the substrate;

performing first deposition on the source electrode, the drain electrode and the uncovered substrate surfaces of the source electrode and the drain electrode by adopting an isolation material to obtain an isolation layer;

preparing a grid electrode on the surface of the isolation layer; the gate does not overlap the channel location in a vertical direction;

etching the isolation layer to expose the substrate where the channel position is located and pins of the source electrode and the drain electrode;

carrying out second deposition on the surface of the substrate where the channel position is located by adopting a channel material to obtain a channel; the substrate, the source electrode, the drain electrode, the channel, the isolation layer and the grid electrode form a composite functional structure;

coating a grid medium on the surface of the composite functional structure to obtain the electrolyte grid-controlled transistor array; the gate dielectric is a liquid or quasi-solid electrolyte.

Preferably, the source and drain electrode composition includes one or more of aluminum, gold, silver, copper, platinum, molybdenum, indium tin oxide, and fluorine doped tin oxide;

the grid electrode comprises one or more of aluminum, gold, silver, copper, platinum, molybdenum, palladium, indium tin oxide and fluorine doped tin oxide;

the thicknesses of the source electrode, the drain electrode and the grid electrode are independently 50-500 nm, and the pattern line width is independently 0.5-50 mu m.

Preferably, the components of the substrate and the isolation layer independently comprise borophosphosilicate glass, silicon dioxide or silicon nitride;

the thickness of the isolation layer is 0.1-1 mu m.

Preferably, the channel material comprises tin oxide, indium zinc oxide, indium gallium zinc oxide, amorphous indium gallium zinc oxide or molybdenum disulfide;

the second post-deposition further comprises annealing; the annealing temperature is 200-800 ℃;

the thickness of the channel is 0.5-500 nm.

Preferably, the etching is lithography;

the first deposition and the second deposition independently comprise physical vapor deposition, chemical vapor deposition, or plasma enhanced chemical vapor deposition.

Preferably, the preparation raw materials of the quasi-solid electrolyte comprise organic polymers, metal salts, metal organic frame materials and solvents.

The invention also provides an electrolyte grid-controlled transistor array prepared by the high-precision integration method.

The invention also provides a quasi-solid electrolyte with high ionic conductivity, and the preparation raw materials comprise an organic polymer, metal salt, a metal organic framework material and a solvent;

the molar ratio of the organic polymer to the metal salt is 6-16:1;

the mass ratio of the metal organic framework material to the organic polymer is 1% -10%.

Preferably, the organic polymer comprises one or more of polyethylene oxide, polyvinylpyrrolidone and polyacrylonitrile;

the metal salt comprises one or more of lithium perchlorate, sodium perchlorate, lithium hexafluorophosphate, sodium hexafluorophosphate, lithium difluorosulfonimide, sodium difluorosulfonimide, lithium bistrifluoromethylsulfonimide and sodium bistrifluoromethylsulfonimide;

the metal organic framework material comprises a zeolite-imidazole framework material and/or a channel framework material.

The invention also provides application of the quasi-solid electrolyte in an electronic device.

The invention provides a high-precision integration method of an electrolyte grid-controlled transistor array, which comprises the following steps: preparing a source electrode and a drain electrode on the surface of a substrate; a channel position is arranged between the source electrode and the drain electrode of the substrate; performing first deposition on the source electrode, the drain electrode and the uncovered substrate surfaces of the source electrode and the drain electrode by adopting an isolation material to obtain an isolation layer; preparing a grid electrode on the surface of the isolation layer; the gate does not overlap the channel location in a vertical direction; etching the isolation layer to expose the substrate where the channel position is located and pins of the source electrode and the drain electrode; carrying out second deposition on the surface of the substrate where the channel position is located by adopting a channel material to obtain a channel; the substrate, the source electrode, the drain electrode, the channel, the isolation layer and the grid electrode form a composite functional structure; coating a grid medium on the surface of the composite functional structure to obtain the electrolyte grid-controlled transistor array; the gate dielectric is a liquid or quasi-solid electrolyte. The electrolyte gate control synaptic transistor array prepared by the integration method is different from the traditional transistor with the top gate structure or the bottom gate structure, the grid electrode of the electrolyte gate control synaptic transistor array is not in the vertical area of the transistor channel, the process steps are simplified while the array wiring is convenient, and the grid electrode medium of the transistor is arranged at the top and can be prepared finally, so that the large-array and high-precision preparation of the composite functional structure can be realized before the grid electrode medium is arranged, the incompatibility between the photoetching process and the liquid quasi-solid electrolyte grid medium is avoided, and the integration method is simplified. Meanwhile, an extra isolation layer is introduced between the grid electrode and the source electrode and the drain electrode in the device structure, so that the grid electrode and the source electrode and the drain electrode are isolated, and crosstalk between the two layers of electrodes is avoided.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of an integration method according to the present invention, wherein (a) a grid pattern of source and drain electrodes is prepared, (b) a grid pattern of gate electrodes is prepared for covering an isolation layer, (c) a source and drain lead and a channel are exposed for etching the isolation layer, and a channel is prepared, and (d) a composite functional structure is coated for a gate dielectric;

FIG. 2 is an overall view and a partial enlarged view of a layout for processing an array of synaptic devices of an electrolyte gate controlled transistor prepared in example 1;

FIG. 3 is a photograph of an embodiment of an array of the synaptic devices of the electrolytic gate control transistor prepared in example 1 before coating with a gate dielectric and a microscope photograph;

FIG. 4 is a schematic view of a single composite functional structure prepared in example 1 and a corresponding cross-sectional view;

FIG. 5 is a graph showing the results of a single device basic synaptic performance test in an electrolyte gated transistor synaptic device prepared in example 1;

FIG. 6 is a graph showing the non-linearity (excitation process) distribution of 225 devices uniformly distributed in an array of synaptic devices of an electrolyte gate controlled transistor prepared in example 1;

FIG. 7 is a single device multiple synaptic function simulation of an array of electrolyte gate controlled transistor synaptic devices prepared in example 2;

fig. 8 is an analysis result of the ac impedance spectrum of the electrolyte prepared in example 1 and comparative example.

Detailed Description

In the present invention, all raw material components are commercially available products well known to those skilled in the art unless specified otherwise.

The invention prepares a source electrode and a drain electrode on the surface of a substrate; and a channel position is arranged between the source electrode and the drain electrode of the substrate.

In the present invention, the source and drain electrode components preferably include one or more of aluminum, gold, silver, copper, platinum, molybdenum, indium tin oxide, and fluorine doped tin oxide, more preferably one or more of aluminum, gold, silver, molybdenum, indium tin oxide, and fluorine doped tin oxide, and most preferably one or more of silver, molybdenum, and indium tin oxide; when the composition of the source and the drain is two or more of the above specific choices, the present invention is not limited in any particular way to the composition ratio of the source and the drain.

In the present invention, the thickness of the source and drain electrodes is preferably 50 to 500nm, more preferably 100 to 400nm, and most preferably 150 to 300nm; the pattern line width is preferably 0.5 to 50. Mu.m, more preferably 5 to 25. Mu.m, most preferably 10. Mu.m.

In the present invention, the composition of the substrate preferably includes borophosphosilicate glass, silicon dioxide or silicon nitride, more preferably silicon dioxide or silicon nitride, and most preferably silicon dioxide; the thickness of the substrate is not particularly limited, and the thickness of the substrate known to those skilled in the art may be used.

In the present invention, the preparation of the source electrode and the drain electrode preferably includes deposition and etching performed sequentially; the deposition includes physical vapor deposition, chemical vapor deposition or plasma enhanced chemical vapor deposition, more preferably physical vapor deposition or chemical vapor deposition, most preferably physical vapor deposition; the physical vapor deposition preferably comprises magnetron sputtering deposition or vacuum evaporation; the etching is preferably lithography; the process of deposition and etching is not particularly limited in the present invention, and the source and drain patterns meeting the above thickness conditions may be prepared by a method well known to those skilled in the art.

In the invention, the preparation of the source electrode and the drain electrode also preferably comprises the steps of cleaning and drying the substrate in sequence; the cleaning preferably comprises acetone cleaning, alcohol cleaning and deionized water cleaning which are sequentially carried out; the cleaning and drying process is not particularly limited in the present invention, and may be performed in a manner well known to those skilled in the art.

After the source electrode and the drain electrode are prepared, the isolation layer is obtained by first depositing isolation materials on the source electrode, the drain electrode and the uncovered substrate surfaces of the source electrode and the drain electrode.

In the present invention, the composition of the isolation layer preferably includes borophosphosilicate glass, silicon dioxide or silicon nitride, more preferably silicon dioxide or silicon nitride, and most preferably silicon dioxide.

In the present invention, the thickness of the separator is preferably 0.1 to 1. Mu.m, more preferably 0.15 to 0.8. Mu.m, and most preferably 0.2 to 0.6. Mu.m.

In the present invention, the first deposition preferably includes physical vapor deposition, chemical vapor deposition or plasma-enhanced chemical vapor deposition, more preferably physical vapor deposition or plasma-enhanced chemical vapor deposition, and most preferably plasma-enhanced chemical vapor deposition; the first deposition process is not particularly limited, and the isolation layer meeting the above thickness conditions may be prepared by a process well known to those skilled in the art.

After the isolating layer is obtained, a grid electrode is prepared on the surface of the isolating layer; the gate does not overlap the channel location in a vertical direction.

In the present invention, the composition of the gate electrode preferably includes one or more of aluminum, gold, silver, copper, platinum, molybdenum, palladium, indium tin oxide, and fluorine doped tin oxide, more preferably one or more of aluminum, gold, molybdenum, palladium, indium tin oxide, and fluorine doped tin oxide, and most preferably one or more of molybdenum, palladium, and indium tin oxide; when the composition of the gate electrode is two or more of the above specific choices, the composition ratio of the gate electrode is not particularly limited.

In the present invention, the thickness of the gate electrode is preferably 50 to 500nm, more preferably 100 to 400nm, and most preferably 150 to 300nm; the pattern line width is preferably 0.5 to 50. Mu.m, more preferably 5 to 25. Mu.m, most preferably 10. Mu.m.

In the present invention, the preparation of the gate electrode preferably includes deposition and etching sequentially; the deposition preferably comprises physical vapor deposition, chemical vapor deposition or plasma enhanced chemical vapor deposition, more preferably physical vapor deposition or chemical vapor deposition, most preferably physical vapor deposition; the physical vapor deposition preferably comprises magnetron sputtering deposition or vacuum evaporation, more preferably magnetron sputtering deposition; the etching is preferably lithography; the process of deposition and etching is not particularly limited in the present invention, and the gate pattern meeting the above thickness conditions may be prepared by a method well known to those skilled in the art.

After the grid electrode is prepared, the isolation layer is etched, and the substrate where the channel position is located and pins of the source electrode and the drain electrode are exposed.

In the present invention, the etching is preferably lithography; the etching process is not particularly limited, and the substrate where the channel is located and the pins of the source electrode and the drain electrode are exposed in a manner well known to those skilled in the art.

After the etching, the invention adopts the channel material to carry out second deposition on the surface of the substrate where the channel position is positioned, so as to obtain a channel; the substrate, the source electrode, the drain electrode, the channel, the isolation layer and the grid electrode form a composite functional structure.

In the present invention, the channel material preferably includes tin oxide, indium zinc oxide, indium gallium zinc oxide, amorphous indium gallium zinc oxide, or molybdenum disulfide, more preferably indium gallium zinc oxide, amorphous indium gallium zinc oxide, or molybdenum disulfide, and most preferably indium gallium zinc oxide or molybdenum disulfide.

In the present invention, the thickness of the channel is preferably 0.5 to 500nm; when the channel is tin oxide, indium zinc oxide, indium gallium zinc oxide or amorphous indium gallium zinc oxide, the thickness of the channel is preferably 50-500 nm, more preferably 100-400 nm, and most preferably 150-300 nm; when the channel is molybdenum disulfide, the thickness of the channel is preferably 0.65-65 nm, more preferably 0.65-6.5 nm, and most preferably 0.65nm; the length and width of the channels are independently preferably 0.5 to 50 μm, more preferably 5 to 25 μm, most preferably 10 to 20 μm; .

In the present invention, the second deposition preferably includes physical vapor deposition, chemical vapor deposition or plasma-enhanced chemical vapor deposition, more preferably physical vapor deposition or chemical vapor deposition, and most preferably physical vapor deposition; the physical vapor deposition preferably comprises magnetron sputtering deposition or vacuum evaporation, more preferably magnetron sputtering deposition; the process of the second deposition is not particularly limited, and the channel meeting the above thickness conditions may be prepared by a process well known to those skilled in the art.

In the present invention, the second deposition preferably further includes etching and annealing performed sequentially; the etching is preferably lithography; the invention is not limited in any way to the photolithographic process, and the channel is aligned with the source and drain electrodes and brought into good contact by processes well known to those skilled in the art; the annealing temperature is preferably 200-800 ℃, more preferably 200-600 ℃, and most preferably 200-400 ℃; the time is preferably 0.5 to 4 hours, more preferably 1 to 3 hours, most preferably 2 hours.

In the present invention, the effect of the anneal is to enhance the channel performance.

After the composite functional structure is obtained, the surface of the composite functional structure is coated with a grid medium to obtain the electrolyte grid-controlled transistor array.

In the present invention, the gate dielectric is preferably a liquid or quasi-solid electrolyte, more preferably a quasi-solid electrolyte.

In the present invention, the raw materials for preparing the quasi-solid electrolyte preferably include an organic polymer, a metal salt, a metal organic frame material, and a solvent.

In the present invention, the organic polymer preferably includes one or more of polyethylene oxide, polyvinylpyrrolidone and polyacrylonitrile, more preferably polyethylene oxide and/or polyvinylpyrrolidone; when the organic polymer is two or more of the above specific choices, the compounding ratio of the organic polymer is not particularly limited in the present invention.

In the invention, the polyethylene pyrrolidone is doped into the polyethylene oxide, so that the electrolyte leakage phenomenon after the metal organic frame material is added can be effectively inhibited.

In the present invention, the metal salt preferably includes one or more of lithium perchlorate, sodium perchlorate, lithium hexafluorophosphate, sodium hexafluorophosphate, lithium bis-fluorosulfonyl imide, sodium bis-fluorosulfonyl imide, lithium bis-trifluoromethylsulfonyl imide and sodium bis-trifluoromethylsulfonyl imide, more preferably one or more of lithium bis-fluorosulfonyl imide, sodium bis-trifluoromethylsulfonyl imide, lithium bis-trifluoromethylsulfonyl imide and sodium bis-trifluoromethylsulfonyl imide, and most preferably lithium bis-trifluoromethylsulfonyl imide and/or sodium bis-trifluoromethylsulfonyl imide; when the metal salt is two or more of the above specific choices, the proportion of the metal salt is not particularly limited in the present invention.

In the present invention, the metal organic framework material preferably comprises a zeolite-imidazole framework material and/or a channel framework material, more preferably a zeolite-imidazole framework material; the zeolite-imidazole framework material preferably comprises one or more of ZIF-8, ZIF-67 and ZIF-L, more preferably one or more of ZIF-67 and/or ZIF-L, most preferably ZIF-67; the channeled frame material preferably comprises PCN-9 and/or PCN-14, more preferably PCN-14; when the metal organic frame material is two or more of the above specific choices, the compounding ratio of the metal organic frame material is not particularly limited.

In the present invention, the solvent preferably includes acetonitrile.

In the present invention, the molar ratio of the organic polymer to the metal salt is preferably 6 to 16:1, more preferably 8 to 14:1, and most preferably 8 to 12:1;

in the present invention, the mass ratio of the metal organic framework material to the organic polymer is preferably 1% to 10%, more preferably 2% to 6%, and most preferably 3%.

In the present invention, the volume of the solvent and the mass ratio of the organic polymer are preferably 20 to 28mL/g, more preferably 22 to 26mL/g, and most preferably 24mL/g.

In the present invention, the method for preparing a quasi-solid electrolyte comprises: and mixing the organic polymer, the metal salt, the metal organic framework material and the solvent to obtain the quasi-solid electrolyte.

In the present invention, the mixing means is preferably stirring; the stirring time is preferably 6 to 24 hours, more preferably 10 to 20 hours, and most preferably 12 hours; the stirring process is not particularly limited, and may be performed in a manner well known to those skilled in the art.

In the present invention, the coating means preferably includes spin coating, drop coating or blade coating, more preferably drop coating or blade coating, and most preferably drop coating.

In the present invention, the post-coating further preferably includes standing; the process of the present invention is not particularly limited, and the gate dielectric may be uniformly stabilized by a method well known to those skilled in the art.

The electrolyte gate control synaptic transistor array prepared by the integration method is different from the traditional transistor with a top gate structure or a bottom gate structure, and the grid electrode of the electrolyte gate control synaptic transistor array is not in a vertical region of a transistor channel, so that the wiring of the array is convenient, and meanwhile, the process steps are simplified; the transistor gate dielectric is arranged at the top and can be prepared finally, so that large-array and high-precision preparation of the composite functional structure can be realized before the gate dielectric is arranged, incompatibility between a photoetching process and a liquid quasi-solid electrolyte gate dielectric is avoided, an integration method is simplified, and trial-and-error experiments on liquid and quasi-solid electrolyte materials are facilitated. In addition, an extra isolation layer is introduced between the grid electrode and the source electrode and the drain electrode in the device structure, so that the grid electrode and the source electrode and the drain electrode are isolated, and crosstalk between the two layers of electrodes is avoided. Meanwhile, the integration method provided by the invention is compatible with the existing thin film transistor preparation process.

the molar ratio of the organic polymer to the metal salt is 6-16:1;

In the present invention, the solvent preferably includes acetonitrile.

The quasi-solid electrolyte provided by the invention jumps out of the traditional method for improving the ionic conductivity of the polymer matrix mainly in the form of doping inorganic electrolyte or low-dimensional material thereof, and adopts a metal organic framework material with a super-porous structure. The organic ligand-based ion-selective polymer not only has the activity of metal ions, but also has the functional group selectivity and flexibility of organic ligands, and has a special spatial structure based on the metal ions and the organic ligands, so that the ion transmission rate can be greatly improved.

The application mode of the quasi-solid electrolyte in the electronic device is not particularly limited, and the quasi-solid electrolyte can be prepared by adopting a process well known to a person skilled in the art.

For further explanation of the present invention, the present invention provides an electrolyte gate control transistor array and its high precision integration method, a quasi-solid state electrolyte with high ion conductivity and its application, which are described in detail below with reference to the accompanying drawings and examples, but they should not be construed as limiting the scope of the present invention.

Example 1

And selecting a silica glass substrate, sequentially cleaning the silica glass substrate by using acetone, alcohol and deionized water, and then drying the silica glass substrate for later use.

A 150nm thick metal molybdenum (Mo) and a 50nm thick Indium Tin Oxide (ITO) are sequentially deposited as source and drain layers of an electrolyte gate control transistor on a glass substrate using a magnetron sputter deposition method. The source and drain grid pattern was etched using a photolithography process with a line width of 10 μm and a reserved channel position with a channel length and a channel width of 10 μm as shown in fig. 1 (a) (for clarity of illustration of the fabrication process, fig. 1 provides a reference diagram of the fabrication process for a 5×5 array, and it is not shown that only a 5×5 array was fabricated in this example).

A 300nm thick silicon dioxide isolation layer was deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD).

A 150nm thick metallic molybdenum (Mo) and a 50nm thick Indium Tin Oxide (ITO) were deposited as an electrolyte gate transistor gate layer on the spacer layer using magnetron sputter deposition. The gate grid pattern was etched using a photolithography process with a line width of 10 μm as shown in fig. 1 (b).

And processing the isolation layer by using a photoetching process to expose the substrate where the reserved channel position is located and the source drain electrode pin.

A 200nm thick Indium Gallium Zinc Oxide (IGZO) was deposited at the channel location using magnetron sputter deposition and a photolithographic process was used to align and form good contacts for the channel regions of the electrolyte gate transistor and the switching transistor and their corresponding source and drain electrodes, as shown in fig. 1 (c). And annealing the whole array at 220 ℃ for 2 hours to improve the performance of Indium Gallium Zinc Oxide (IGZO). Thus far, the fabrication of all complex functional structures except the gate dielectric has been completed for the array of electrolyte gate controlled transistor synapses. The layout for array processing is shown in fig. 2, wherein the diagram (a) is a layout overall diagram, and the diagram (b) is a layout partial enlarged diagram. The composite functional structure physical diagram is shown in fig. 3, wherein the left diagram of fig. 3 is an array physical photograph, and the right diagram of fig. 3 is an array microscope photograph. A single composite functional structure schematic and corresponding cross-sectional view is shown in fig. 4.

The solute polyethylene oxide (PEO), polyvinylpyrrolidone (PVP), lithium bis (trifluoromethylsulfonyl) imide (LiTFSI), ZIF-67 and solvent acetonitrile are used for preparing the composite electrolyte, and the following conditions are satisfied: PEO and PVP together form an organic polymer matrix, wherein the mass ratio of PVP to PEO is 50%. The molar ratio of the organic polymer matrix to LiTFSI is 8:1, the mass ratio of ZIF-67 to the organic polymer matrix is 3%, and the mass ratio of acetonitrile volume to the organic polymer matrix is 24mL/g. After stirring for 12 hours, a quasi-solid electrolyte is obtained and is dripped on the array to be uniformly distributed and used as a grid medium. Standing still and waiting for the electrolyte to stabilize, so as to obtain a coplanar grid electrode electrolyte grid control transistor synaptic device array, as shown in fig. 1 (d).

In the embodiment, 100×100 electrolyte gate control transistors are successfully integrated on 25mm×25mm TFT glass, and the feasibility of high-precision integration of the large array of the electrolyte gate control transistors by the scheme is proved.

Example 2

A 150nm thick metal silver (Ag) was deposited as an electrolyte gate transistor source drain layer on a glass substrate using vacuum evaporation. And (3) etching a source drain grid pattern by using a photoetching process, wherein the line width is 10 mu m, and the channel position is reserved, and the channel length and the channel width are respectively 20 mu m and 10 mu m.

A 300nm thick SiO2 isolation layer was deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD).

And depositing 150nm thick metal palladium (Pd) on the isolation layer by using a magnetron sputtering deposition mode as a gate layer of the electrolyte gate control transistor. Grid patterns were etched using a photolithography process with a line width of 20 μm.

150nm thick Indium Gallium Zinc Oxide (IGZO) is deposited at the channel position by using a magnetron sputtering deposition mode, and a photoetching process is used for aligning the channel regions of the electrolyte gate control transistor and the switch tube and the corresponding source electrode and drain electrode thereof and forming good contact. And annealing the whole array at 220 ℃ for 2 hours to improve the performance of Indium Gallium Zinc Oxide (IGZO). To this end, the fabrication of all complex functional structures, except the electrolyte, has been completed for an array of electrolyte-gated transistor synapses.

The solute polyethylene oxide (PEO), polyvinylpyrrolidone (PVP), sodium bis (trifluoromethylsulfonamide) (NaTFSI), ZIF-67 and solvent acetonitrile are used for preparing the composite electrolyte, and the following conditions are satisfied: the molecular weight ratio of PEO to NaTFSI was 10:1, the ZIF-67 to PEO mass ratio was 3%, the PVP to PEO mass ratio was 50%, and the acetonitrile volume to PEO mass ratio was 20mL/g. After stirring for 12 hours, the mixture was spread on an array to be uniformly distributed as a gate medium. And standing for the electrolyte to stabilize, so as to obtain the coplanar grid electrode electrolyte grid control transistor synaptic device array.

Comparative example

An electrolyte was prepared according to the preparation method provided in example 1, except that no ZIF-67 metal-organic framework material was added.

Test example 1

A single device in the array of electrolyte gated transistor synaptic devices prepared in example 1 was tested. A specific electrolyte gated transistor in the array can be selected by arbitrarily selecting a gate pin and a drain pin and applying a voltage. In the test, pulse voltages with different amplitudes, different pulse widths and different numbers are applied to the gate pins, and fixed bias voltages are applied to the drain pins, so that simulation of basic synaptic function excitation type post-synaptic current (EPSC) and double pulse facilitation (continuous two identical pulses trigger post-synaptic current, and the post-synaptic current is larger than the post-synaptic current) can be completed, and the test result is shown in FIG. 5.

In fig. 5, graph (a) is a graph of the change of the current after excited synapse with the pulse amplitude, graph (b) is a graph of the change of the current after excited synapse with the pulse width, graph (c) is a graph of the change of the current after excited synapse with the number of pulses, and graph (d) is a graph of the simulation of the double pulse facilitation function. As can be seen from fig. 5, the devices in the array of electrolyte gated transistor synaptic devices have good synaptic shaping.

225 uniformly distributed devices were selected from the array of the electrolyte gated transistor synapse devices prepared in example 1, tested for long-range shaping using a series of gate pulses, of which 60 positive pulses (excitation process) and 60 negative pulses (suppression process) were grouped together in three groups, simulating long-range shaping of the synapse, extracting their nonlinearities (including excitation process and suppression process), and cycle-to-cycle differences (waveform differences generated for characterizing the pulse sequences of each group), respectively, and the test results are shown in fig. 6.

Fig. 6 shows the distribution of nonlinearity of the excitation process, and through statistical analysis, the performance of the selected 225 devices is better and similar, and the electrolyte grid control transistor array is proved to have better performance and uniformity.

Test example 2

The single devices in the array of the synaptic devices of the electrolyte gate controlled transistor prepared in example 2 were tested so that the electrolyte gate controlled transistor mimics the synaptic function. The method comprises the steps of stimulating a single-synaptic transistor in an array by using a sequence consisting of five pulses with different frequencies, simulating a high-pass filtering function by taking the relative variation of the excited post-synaptic current as a threshold value of the high-pass filtering, and deducing the approximate range of the frequency of the applied pulse sequence and realizing the high-pass filtering function by taking the relative variation of the current as a reference standard by using a current curve graph and a current relative variation curve graph after synapses under the excitation of pulse sequences with different frequencies as shown in fig. 7 (a) and 7 (b).

After different time intervals, a pulse is respectively applied to the grid electrode and the drain electrode of the synaptic transistor (wherein the grid electrode is firstly applied, the interval time is positive, and the interval time is negative), the relative variation of post-synaptic current is used as the variation of synaptic weight so as to simulate peak time sequence dependent plasticity, a simulated fitting curve diagram of the peak time sequence dependent plasticity of the synaptic devices in the array is shown in fig. 7 (c), and the plasticity is shown to be in classical Gaussian distribution.

Using synaptic transistor plasticity, the simulated bar Pu Luofu experiment: the 1V pulse was considered as bell and the 2V pulse as feed; a postsynaptic current below 1.2 μΑ was considered to be non-salivary to the dogs and a current above 1.2 μΑ was considered to be salivary to the dogs. The simulation process and results are shown in fig. 7 (d). As can be seen from FIG. 7 (d), before training, a 1V pulse was applied, the post-synaptic current was less than 1.2 μA, a 2V pulse was applied, and the post-synaptic current exceeded 1.2 μA. The dog simulated by the synaptic transistor is shown to not form a conditional reflection. Pulses of 1V and 2V were applied simultaneously as training, and after 10 training, the post-synaptic current was still greater than 1.2 mua even with pulses of 1V alone. The dog simulated by the electrode grid control transistor synaptic device array forms conditional reflection and training is successful.

Test example 3

The electrolytes prepared in example 1 and comparative example were subjected to ac impedance spectroscopy, and the test results are shown in fig. 8. The ion conductivity can be determined by the abscissa R of the intersection point of an alternating current impedance spectrum arc and a straight line ₀ And (5) calculating to obtain the product. Satisfying the ion conductivity σ=l/(s×r) ₀ ). Wherein L and S are the thickness and area of the test device, respectively, and the thickness and area of the two samples in the test are the same.

As can be seen from fig. 8, the quasi-solid electrolyte prepared in example 1 of the present invention has significantly improved ionic conductivity compared to the electrolyte provided in the comparative example.

Although the foregoing embodiments have been described in some, but not all embodiments of the invention, other embodiments may be obtained according to the present embodiments without departing from the scope of the invention.

Claims

1. The high-precision integration method of the electrolyte grid-controlled transistor array is characterized by comprising the following steps of:

2. The high precision integration method of claim 1, wherein the source and drain components comprise one or more of aluminum, gold, silver, copper, platinum, molybdenum, indium tin oxide, and fluorine doped tin oxide;

3. The high precision integration method of claim 1, wherein the composition of the substrate and isolation layer independently comprises borophosphosilicate glass, silicon dioxide, or silicon nitride;

the thickness of the isolation layer is 0.1-1 mu m.

4. The high precision integration method of claim 1, wherein the channel material comprises tin oxide, indium zinc oxide, indium gallium zinc oxide, amorphous indium gallium zinc oxide, or molybdenum disulfide;

the thickness of the channel is 0.5-500 nm.

5. The high precision integration method according to claim 1 or 4, wherein the etching is lithography;

6. The high precision integration method of claim 1, wherein the quasi-solid electrolyte is prepared from raw materials including organic polymers, metal salts, metal organic framework materials and solvents.

7. An electrolyte gate-controlled transistor array prepared by the high-precision integration method of any one of claims 1 to 6.

8. A quasi-solid electrolyte with high ionic conductivity is characterized in that the preparation raw materials comprise organic polymers, metal salts, metal organic frame materials and solvents;

the molar ratio of the organic polymer to the metal salt is 6-16:1;

9. The quasi-solid state electrolyte of claim 8, wherein the organic polymer comprises one or more of polyethylene oxide, polyvinylpyrrolidone, and polyacrylonitrile;

10. Use of a quasi-solid electrolyte as claimed in claim 8 or 9 in an electronic device.