CN116013987A - SiC VDMOSFET power device and preparation method thereof - Google Patents
SiC VDMOSFET power device and preparation method thereof Download PDFInfo
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- CN116013987A CN116013987A CN202211557686.5A CN202211557686A CN116013987A CN 116013987 A CN116013987 A CN 116013987A CN 202211557686 A CN202211557686 A CN 202211557686A CN 116013987 A CN116013987 A CN 116013987A
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Abstract
The invention discloses a structure of a SiC VDMOSFET power device, which comprises: an N-type SiC substrate, a drain electrode positioned on the back surface and the front surface of the N-type SiC substrate, and an N-type epitaxial layer; two P well regions are formed by injection at two sides of the N-type epitaxial layer, a P+ contact region and an N+ source region are sequentially formed in each P well region, the P+ contact region is far away from the JFET region, and the N+ source region is adjacent to the P+ contact region and is close to the JFET region; the first layer of gate oxide layer is arranged on the N-type epitaxial layer and is positioned above the JFET region, the channel and part of the N+ source region, the first layer of gate oxide layer above the channel is downwards concave, a gate is formed on the first layer of gate oxide layer, and a source is formed on the P+ contact region and part of the N+ source region. The concave gate oxide layer is formed through dry etching, the gate oxide layer is thick above the JFET region and thin above the channel, the threshold voltage of the device is reduced under the condition that the electric field intensity born by the gate oxide layer is not affected, and the performance and reliability of the device are improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a SiC VDMOSFET power device and a preparation method thereof.
Background
Silicon carbide (SiC) has excellent physical and electrical characteristics as a representative of third generation semiconductor materials. Compared with silicon materials, the SiC material has the advantages of large forbidden bandwidth, high breakdown electric field, high heat conductivity, high electron saturation rate, strong radiation resistance and the like, so that a semiconductor device prepared from the SiC material can stably operate at a higher temperature and is also suitable for high-voltage and high-frequency scenes. Meanwhile, the SiC material is the only SiO which can be grown by thermal oxidation besides the Si material 2 This provides a reference process for the development of the gate oxide of the voltage-controlled device MOSFET, which makes the MOSFET widely used. For a voltage-controlled power device SiC VDMOSFET, conduction of the conduction channel is achieved by applying pressure on the gate oxide. The quality of the gate oxide layer thus determines whether the entire device can function properly.
Application publication number CN 114446785A, application publication date 2022.05.06, patent name: a preparation process for improving threshold voltage stability of a silicon carbide VDMOSFET device is characterized in that a gate oxide layer is prepared by high-temperature thermal oxidation in an oxygen environment; due to the self-properties of SiC, a large number of defects such as dangling bonds, carbon clusters, near-interface traps and the like exist in the gate oxide layer after the SiC is thermally oxidized, so that the SiC has extremely high interface state density, and the reliability of the gate oxide and the normal operation of the SiC VDMOSFET are seriously affected.
Disclosure of Invention
The present invention provides a structure of a SiC VDMOSFET power device, which aims to improve the above-mentioned problems.
The invention is realized in that a structure of a SiC VDMOSFET power device comprises:
an N-type SiC substrate 2, a drain electrode 1 and an N-type epitaxial layer 3 positioned on the back and the front of the N-type SiC substrate 2;
two P well regions 4 are formed by injection at two sides of the N-type epitaxial layer 3, a P+ contact region 5 and an N+ source region 6 are sequentially formed in each P well region 4, the P+ contact region 5 is far away from the JFET region, and the N+ source region 6 is adjacent to the P+ contact region 5 and is close to the JFET region;
the first layer of gate oxide layer 9 is arranged on the N-type epitaxial layer, is positioned above the JFET region, the channel and part of the N+ source region 6, the first layer of gate oxide layer 9 above the channel is downwards concave, the gate 10 is formed on the first layer of gate oxide layer, and the source is formed on the P+ contact region 5 and part of the N+ source region 6.
Further, the SiC VDMOSFET power device further includes:
a second gate oxide layer 8 is located between the first gate oxide layer 9 and the N-type epitaxial layer 3 and over the JFET region, channel and part of the n+ source region 6.
Further, the N-type epitaxial layer 3 having the shallow phosphorus ion implantation is thermally oxidized to form a second gate oxide layer 8.
Further, two lightly doped N-type regions 7 are formed in the P-well region 4 and are disposed adjacent to the JFET region and the n+ source region 6, respectively.
The invention is realized in such a way that a preparation method of a SiC VDMOSFET power device comprises the following steps:
s1, epitaxially growing an N-type epitaxial layer 3 on the front surface of the N-type SiC substrate 2;
s2, forming two P well regions 4 on two sides of the front surface of the N-type epitaxial layer 3 through ion implantation,
s3, performing ion implantation at the position, far away from the JEFT region, of the P well region 4 to form a P+ contact region 5, and performing ion implantation at the position, close to the JFET region, of the P well region 4 to form an N+ source region 6;
s4, forming a phosphorus ion shallow injection layer at the top of the N-type epitaxial layer 3, and activating injection ions;
s5, depositing SiO on the JFET region, the channel and part of the N+ source region 6 2 Layer, throughFormation of SiO by means of thermal oxidation 2 Oxidizing the layer, consuming the phosphorus ion shallow injection layer, and annealing in NO;
S6、SiO 2 etching the oxide layer to form a second gate oxide layer 8 for SiO 2 Dry etching is carried out on the layers to form a first layer of grid oxide layer 9 with a thick thickness above the JFET region and a thin thickness above the channel;
and S7, forming a gate 10 on the first layer of gate oxide layer 9, forming a source 11 on the P+ contact region 5 and a part of the N+ source region 6 far away from the JFET region, and forming a back drain 1 of the N-type SiC substrate 2.
Further, the formation process of the shallow phosphorus ion implantation layer on the top of the N-type epitaxial layer 3 is as follows:
deposition of SiO on the N-type epitaxial layer 2 The cushion layer is then subjected to phosphorus ion implantation, and after the implantation is finished, all SiO is removed 2 And a cushion layer, wherein a phosphorus ion shallow implantation layer is formed on the top of the N-type epitaxial layer 3.
Further, the thickness of the second layer of gate oxide layer is 20-30 nm, and the thickness of the first layer of gate oxide layer is 60-80 nm.
Further, siO 2 The etching thickness of the layer is 40-60 nm, and the etching width is slightly larger than the trench width, so that a first layer of gate oxide layer is formed.
Further, after step S3, before step S4, the method further includes: and carrying out sub-implantation on two sides of a channel between the N+ source region 6 and the JEFT region to form a lightly doped N-type region 7.
The invention forms a thin oxide layer by combining the thermal oxidation after the shallow injection pretreatment of phosphorus ions and PECVD deposition of SiO through a concave gate oxide layer and additionally adding two lightly doped N-type regions at the upper parts of two sides of a channel 2 The two modes of the layer are adopted to efficiently prepare the gate oxide layer with the target thickness, the effects of reducing the threshold voltage of the SiC VDMOSFET and the defects of the gate oxide layer are realized under the condition that the voltage endurance capability of the gate oxide layer is not influenced, the thermal electron degradation effect is prevented, and the performance and the reliability of the device are improved.
Drawings
Fig. 1 is a schematic structural diagram of a SiC VDMOSFET power device provided in an embodiment of the present invention;
fig. 2 is a flowchart of a method for manufacturing a SiC VDMOSFET power device according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a device structure after an N-type epitaxial layer is formed according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a device structure after forming a P-well region according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a device structure after forming a p+ contact region according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a device structure after forming an n+ source region according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a device structure after forming a lightly doped N-type region according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a device structure after forming a shallow phosphorus ion implantation layer according to an embodiment of the present invention;
FIG. 9 is a diagram of deposited SiO according to an embodiment of the present invention 2 Schematic device structure after layer;
FIG. 10 shows the formation of SiO after thermal oxidation in accordance with an embodiment of the present invention 2 Schematic device structure after oxide layer;
fig. 11 is a schematic diagram of a device structure after forming a second gate oxide layer according to an embodiment of the present invention;
fig. 12 is a schematic view of a device structure after forming a first gate oxide layer according to an embodiment of the present invention;
fig. 13 is a schematic view of a device structure after forming a gate according to an embodiment of the present invention;
fig. 14 is a schematic view of a device structure after forming a source electrode according to an embodiment of the present invention;
1. the semiconductor device comprises a drain electrode, a 2.N type SiC substrate, a 3.N type epitaxial layer, a 4.P well region, a 5.P + contact region, a 6.N+ source region, a 7. Lightly doped N type region, an 8. Second layer gate oxide layer, a 9. First layer gate oxide layer, a 10. Gate and a 11. Source electrode. 12. And (5) shallow implantation of phosphorus ions.
Detailed Description
The following detailed description of the embodiments of the invention, given by way of example only, is presented in the accompanying drawings to aid in a more complete, accurate, and thorough understanding of the inventive concepts and aspects of the invention by those skilled in the art.
Fig. 1 is a schematic structural diagram of a SiC VDMOSFET power device provided in an embodiment of the present invention, and for convenience of explanation, only a portion relevant to the embodiment of the present invention is shown.
The VDMOSFET is a vertical conduction double diffusion MOSFET power device, and the SiC VDMOSFET power device comprises:
a drain electrode 1 type SiC substrate 2, an N type epitaxial layer 3, a P well region 4, a P+ contact region 5, an N+ source region 6, a first layer gate oxide layer 9, a gate electrode 10 and a source electrode 11;
an N-type SiC substrate 2, wherein a drain electrode 1 and an N-type epitaxial layer 3 are respectively formed on the back surface and the front surface of the N-type SiC substrate 2; two P well regions 4 are formed on two sides in the N-type epitaxial layer 3, a P+ contact region 5 and an N+ source region 6 are sequentially formed in the P well region 4, the P+ contact region 5 is far away from the JFET region, and the N+ source region 6 is adjacent to the P+ contact region 5 and is close to the JFET region; a first gate oxide layer 9 on the N-type epitaxial layer, located above the JFET region, channel and part of the n+ source region 6; the first gate oxide layer 9 above the channel is recessed, a gate 10 is formed on the first gate oxide layer, and a source is formed on the p+ contact region 5 and a portion of the n+ source region 6.
According to the invention, the concave gate oxide layer is formed by dry etching, the gate oxide layer is thick above the JFET region and thin above the channel, and the threshold voltage of the device is reduced and the performance and reliability of the device are improved under the condition that the electric field intensity born by the gate oxide layer is not influenced.
In an embodiment of the present invention, the SiC VDMOSFET power device further includes:
a second gate oxide layer 8 is located between the first gate oxide layer 9 and the N-type epitaxial layer 3 and over the JFET region, channel and part of the n+ source region 6.
In the embodiment of the invention, two lightly doped N-type regions 7 are formed in each P well region 4 and are respectively adjacent to the JFET region and the N+ source region 6; the lightly doped N-type region is added at the upper parts of the two sides of the channel of the SiC VDMOSFET, so that the hole concentration of the channel is reduced to a certain extent, the threshold voltage of the device is reduced, and the performance of an oxide layer is improved; in addition, the existence of the lightly doped N type region can prevent the hot electron degradation effect.
Fig. 2 is a flowchart of a method for manufacturing a SiC VDMOSFET power device according to an embodiment of the present invention, where the method specifically includes the following steps:
s1, selecting an N-type SiC substrate 2 substrate, wherein the doping concentration is 1e19cm -3 ；
S2, forming an N-type epitaxial layer 3 on the front surface of the N-type SiC substrate 2 through epitaxial growth, wherein the doping concentration is 8e15cm -3 ～1.5e16 cm -3 As shown in fig. 3;
s3, forming two P well regions 4 on two sides of the N-type epitaxial layer 3 through ion implantation, wherein the implanted ions are aluminum ions, and the doping concentration is 1e17cm -3 ～1e18cm -3 The implantation depth is 0.8um to 1um as shown in fig. 4;
s4, performing ion implantation at the position, far away from the JEFT region, of the P well region 4 to form a P+ contact region 5, wherein the implanted ions are aluminum ions, and the doping concentration is 1e19cm -3 The implantation depth is 0.4-0.5 um, as shown in FIG. 5;
s5, ion implantation is carried out at the position, close to the JFET region, of the P well region 4 and close to the P+ contact region 5 to form an N+ source region 6, the implanted ions are phosphorus ions, and the doping concentration is 1e19cm -3 The implantation depth is 0.4-0.5 um, as shown in FIG. 6;
s6, depositing 50-100 nm SiO on the N-type epitaxial layer 3 2 The cushion layer is subjected to phosphorus ion implantation, and after the implantation is finished, all SiO is removed 2 A cushion layer, a phosphorus ion shallow injection layer 12 is formed on the top of the N-type epitaxial layer 3, and the doping concentration is less than 1e19cm -3 The implantation depth is 0.01-0.02 um, as shown in FIG. 8;
s7, performing high-temperature annealing, namely activating implanted ions, wherein the annealing temperature is 1300-1600 ℃ and the annealing time is 15-30 min;
s8, depositing 60-80 nm SiO on the JFET region, the channel and part of the N+ source region 6 by PECVD 2 Layers, as shown in fig. 9.
S9, forming SiO of 20-30 nm by adopting a thermal oxidation mode 2 The oxidation temperature of the oxidation layer is 1250-1350 ℃, the oxidation time is 10-30 min, and the phosphorus ions are completely consumedShallow injection layer, then annealing in NO for 1 hour, annealing temperature 1150-1350 deg.C, as shown in figure 10;
s10, performing dry etching on SiO generated by thermal oxidation 2 Etching the oxide layer to only protect SiO on the JFET region, the rear trench and part of the N+ source region 6 2 An oxide layer forming a second gate oxide layer 8 as shown in fig. 11;
s11, pair SiO 2 Dry etching the layer to remove SiO above the trench 2 The etching thickness of the layer is 40-60 nm, and the etching width is slightly larger than the length of the channel, so that a first layer of gate oxide layer 9 is formed, as shown in FIG. 12;
s12, forming a gate 10 on the first layer gate oxide layer 9 by metal sputtering, as shown in fig. 13.
S13, forming a source electrode 11 on the P+ contact region 5 and a part of the N+ source region 6 far away from the JFET region in a metal sputtering mode, and forming ohmic contact through high-temperature rapid thermal annealing, as shown in FIG. 14;
and S14, forming a drain electrode 1 on the back surface of the N-type SiC substrate 2 by adopting a metal sputtering mode, and forming ohmic contact through laser annealing, as shown in fig. 1.
The invention has two gate oxide layers, the gate oxide layer generated by thermal oxidation is thinner, and the gate oxide layer deposited by PECVD is thicker; during the pretreatment of the shallow implantation of the phosphorus ions, siO is added 2 The cushion layer can help to reduce the damage of ion implantation to the surface of the N-type epitaxial layer and is beneficial to shallower depth of the phosphorus ion implantation layer at the upper part of the N-type epitaxial layer; after the pretreatment of the shallow phosphorus ion implantation, the shallow phosphorus ion implantation layer is completely consumed in a thermal oxidation mode, and part of the implanted P element is reserved in the generated thin gate oxide layer, so that the effect of phosphorus passivation is achieved; the thin oxide layer is prepared by thermal oxidation, the thicker oxide layer is prepared by PECVD deposition on the thin oxide layer, and the two modes are combined to efficiently prepare the gate oxide with the target thickness. In addition, because of SiO 2 The existence of the cushion layer reduces the depth of the ion implantation into the epitaxial layer, and achieves the purpose of shallow implantation.
In another embodiment of the present invention, to improve the hot electron degradation effect, the method further includes, after step S3 and before step S4: sub-implantation is performed on both sides of the channel between the n+ source region 6 and the JEFT region to form a lightly doped N-type region 7, as shown in fig. 7.
While the present invention has been described by way of example, it should be apparent that the practice of the invention is not limited by the foregoing, but rather is intended to cover various insubstantial modifications of the method concepts and teachings of the invention, either as applied to other applications without modification, or as applied directly to other applications, without departing from the scope of the invention.
Claims (9)
1. A structure of a SiC VDMOSFET power device, the structure comprising:
an N-type SiC substrate (2), a drain electrode (1) and an N-type epitaxial layer (3) which are positioned on the back and the front of the N-type SiC substrate (2);
two P well regions (4) are formed by injection at two sides of the N-type epitaxial layer (3), a P+ contact region (5) and an N+ source region (6) are sequentially formed in each P well region (4), the P+ contact region (5) is far away from the JFET region, and the N+ source region (6) is adjacent to the P+ contact region (5) and is close to the JFET region;
the first layer of gate oxide layer (9) is arranged on the N-type epitaxial layer, is arranged above the JFET region, the channel and part of the N+ source region (6), the first layer of gate oxide layer (9) above the channel is concave downwards, the gate (10) is formed on the first layer of gate oxide layer, and the source is formed on the P+ contact region (5) and part of the N+ source region (6).
2. The structure of a SiC VDMOSFET power device of claim 1, wherein said SiC VDMOSFET power device further comprises:
the second layer of gate oxide (8) is positioned between the first layer of gate oxide (9) and the N-type epitaxial layer (3) and is positioned above the JFET region, the channel and part of the N+ source region (6).
3. A structure of a SiC VDMOSFET power device as claimed in claim 2, characterized in that the N-type epitaxial layer (3) in which the shallow implantation of phosphorus ions is present is thermally oxidized to form a second gate oxide layer (8).
4. A structure of a SiC VDMOSFET power device as claimed in claim 1, characterized in that two lightly doped N-type regions (7) are formed in the P-well region (4), arranged adjacent to the JFET region, the n+ source region (6), respectively.
5. A method for manufacturing a SiC VDMOSFET power device, the method comprising the steps of:
s1, epitaxially growing an N-type epitaxial layer (3) on the front surface of the N-type SiC substrate (2);
s2, forming two P well regions (4) on two sides of the front surface of the N-type epitaxial layer (3) through ion implantation;
s3, performing ion implantation at a position, far away from the JEFT region, of the P well region (4) to form a P+ contact region (5), and performing ion implantation at a position, close to the JFET region, of the P well region (4) and close to the P+ contact region (5) to form an N+ source region (6);
s4, forming a phosphorus ion shallow injection layer on the top of the N-type epitaxial layer (3), and activating injection ions;
s5, depositing SiO on the JFET region, the channel and part of the N+ source region (6) 2 A layer formed of SiO by thermal oxidation 2 Oxidizing the layer, consuming the phosphorus ion shallow injection layer, and annealing in NO;
s6, to SiO 2 Etching the oxide layer to form a second gate oxide layer (8) of SiO 2 Dry etching is carried out on the layer to form a first layer of grid oxide layer (9) with a thick thickness above the JFET region and a thin thickness above the channel;
s7, forming a grid electrode (10) on the first layer of grid electrode oxide layer (9), forming a source electrode (11) on the P+ contact region (5) and a part of N+ source region (6) far away from the JFET region, and forming a back drain electrode (1) of the N-type SiC substrate (2).
6. The method for manufacturing a SiC VDMOSFET power device according to claim 5, wherein the forming process of the shallow phosphorus ion implantation layer on top of the N-type epitaxial layer (3) is as follows:
deposition of SiO on the N-type epitaxial layer 2 The cushion layer is then subjected to phosphorus ion implantation, and after the implantation is finished, all SiO is removed 2 And a cushion layer, wherein a phosphorus ion shallow injection layer is formed on the top of the N-type epitaxial layer (3).
7. The method of manufacturing a SiC VDMOSFET power device of claim 6 wherein the second gate oxide layer has a thickness of 20-30 nm and the first gate oxide layer has a thickness of 60-80 nm.
8. The method of manufacturing a SiC VDMOSFET power device of claim 7, wherein SiO 2 The etching thickness of the layer is 40-60 nm, and the etching width is slightly larger than the trench width, so that a first layer of gate oxide layer is formed.
9. The method of manufacturing a SiC VDMOSFET power device of claim 5, further comprising, after step S3, before step S4:
and carrying out sub-implantation on two sides of a channel between the N+ source region (6) and the JEFT region to form a lightly doped N-type region (7).
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