CN116013920A - Semiconductor device, manufacturing method of semiconductor device and electronic equipment - Google Patents
Semiconductor device, manufacturing method of semiconductor device and electronic equipment Download PDFInfo
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Abstract
The invention discloses a semiconductor device, a manufacturing method of the semiconductor device and electronic equipment, wherein the semiconductor device comprises a substrate, a diode and a first insulating layer; the substrate is provided with a first surface, a first groove is formed in the first surface, and a first insulating layer is attached to the inner wall of the first groove; the diode comprises a P-type conductive layer and an N-type conductive layer, wherein the P-type conductive layer and the N-type conductive layer are both positioned in a first groove, a part of first insulating layer is positioned between the P-type conductive layer and the substrate, a part of first insulating layer is positioned between the N-type conductive layer and the substrate, the P-type conductive layer and the N-type conductive layer are connected and are laminated along a first direction, and the first direction is the thickness direction of the substrate. The invention can reduce the area of the first surface of the semiconductor device and reduce the cost of the semiconductor device on the premise that the diode has better electric conduction capacity.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor device, a method for manufacturing the semiconductor device, and an electronic apparatus.
Background
For an integrated chip of an IC (Integrated Circuit ) and a field effect transistor, a diode is one of the common devices of an IC. In addition, a zener diode is further indispensable for securing ESD (electrostatic discharge) resistance of an IC. To prevent parasitic circuits, poly-type diodes are typically used.
In order to secure the conductive capability of the diode, the PN junction width of the diode is relatively large, which leads to an increase in the area of the semiconductor device, increasing the cost of the semiconductor device. In addition, the increase in the area of the semiconductor device also results in a larger package size, and a multi-channel product cannot be realized.
Disclosure of Invention
The invention provides a semiconductor device, a manufacturing method of the semiconductor device and electronic equipment, which can reduce the area of a first surface of the semiconductor device and reduce the cost of the semiconductor device on the premise that a diode has better electric conduction capacity.
In order to solve the technical problems, the invention adopts the following technical scheme:
in a first aspect of the present invention, there is provided a semiconductor device including a substrate, a diode, and a first insulating layer; the substrate is provided with a first surface, a first groove is formed on the first surface, and the first insulating layer is attached to the inner wall of the first groove; the diode comprises a P-type conductive layer and an N-type conductive layer, wherein the P-type conductive layer and the N-type conductive layer are both positioned in the first groove, a part of the first insulating layer is positioned between the P-type conductive layer and the substrate, a part of the first insulating layer is positioned between the N-type conductive layer and the substrate, the P-type conductive layer and the N-type conductive layer are connected and are laminated along a first direction, and the first direction is the thickness direction of the substrate.
The invention has the beneficial effects that:
the P-type conductive layer and the N-type conductive layer are arranged along the thickness direction of the substrate, so that the cross-sectional area of the semiconductor device can be increased, the dimension of the P-type conductive layer and the N-type conductive layer along the length direction can be set to be smaller, the dimension of the P-type conductive layer and the N-type conductive layer along the width direction can be set to be smaller, and good conductivity can be obtained, so that the dimension of the semiconductor device occupied by the diode in the length direction and the width direction can be greatly reduced, the area occupied by the diode on the first surface of the semiconductor device can be further reduced, the area of the first surface of the semiconductor device can be further reduced, the cost of the semiconductor device can be further reduced, and meanwhile, the semiconductor device can also contribute to realizing a multichannel product.
Optionally, a second trench is further formed on the first surface, and the semiconductor device further includes a second insulating layer, a third insulating layer, and a field effect transistor, where the second insulating layer is attached to an inner wall of the second trench; the field effect transistor comprises a first conductive layer and a second conductive layer which are positioned in the second groove, part of the second insulating layer is positioned between the first conductive layer and the substrate, part of the second insulating layer is positioned between the second conductive layer and the substrate, the first conductive layer and the second conductive layer are laminated along the first direction, and the third insulating layer is positioned between the first conductive layer and the second conductive layer.
The first conductive layer and the second conductive layer in the field effect transistor are also stacked in the first direction in the same stacking direction as the P-type conductive layer and the N-type conductive layer of the diode. Since the field-effect transistor itself has a certain thickness, the sum of the dimensions of the P-type conductive layer and the N-type conductive layer in the thickness direction can also be the same as the thickness of the field-effect transistor, and therefore, the thickness of the semiconductor device does not need to be increased, and the dimensions of the diode in the length direction and the width direction can also be reduced, whereby a better conductivity of the diode can also be obtained on the basis of reducing the area of the first surface of the semiconductor device.
Optionally, the first groove and the second groove have the same size along the first direction. Since the second trench itself needs to be processed on the substrate when the semiconductor device includes a field effect transistor, the second insulating layer, the first conductive layer, the second conductive layer, and the like are formed in the second trench. Therefore, when the dimensions of the first trench and the second trench in the first direction are the same, that is, the depths of the first trench and the second trench are the same, the first trench and the second trench can be processed in the same process.
Optionally, the P-type conductive layer is closer to the first surface than the N-type conductive layer, the first conductive layer is closer to the first surface than the second conductive layer, and the N-type conductive layer and the second conductive layer have the same dimension along the first direction.
Optionally, the number of the diodes, the first trenches and the first insulating layer are all plural and the same; the first insulating layers and the diodes are located in the first grooves in a one-to-one correspondence mode, the P-type conducting layers of the diodes are connected, and the N-type conducting layers of the diodes are connected.
Optionally, the plurality of diodes are arranged along a second direction, each diode extends along a third direction, the second direction and the third direction are perpendicular to the first direction, and an included angle is formed between the second direction and the third direction.
Optionally, the semiconductor device further comprises an isolation strip, and the diode and the field effect transistor are respectively located at two sides of the isolation strip.
Optionally, the semiconductor device further includes a fourth insulating layer and a fifth insulating layer, where the fourth insulating layer covers the P-type conductive layer and is located in the first trench, and a surface of the fourth insulating layer facing away from the P-type conductive layer is flush with the first surface; the fifth insulating layer is arranged on the first surface and partially covers the fourth insulating layer.
The invention also provides electronic equipment, which comprises a circuit board and the semiconductor device of any one of the above, wherein the semiconductor device is electrically connected with the circuit board. The electronic apparatus can achieve all the effects of the above-described semiconductor device.
The invention also provides a manufacturing method of the semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate is provided with a first surface; etching the first surface to form a first groove and a second groove which are spaced; forming a first insulating layer in the first trench and forming a second insulating layer in the second trench; forming an N-type conductive layer on the first insulating layer, and forming a second conductive layer on the second insulating layer; forming a P-type conductive layer on the N-type conductive layer; and forming a third insulating layer and a first conductive layer on the second conductive layer in sequence.
The P-type conductive layer and the N-type conductive layer are arranged along the thickness direction of the substrate, so that the cross-sectional area of the semiconductor device can be increased, the dimension of the P-type conductive layer and the N-type conductive layer along the length direction can be set to be smaller, the dimension of the P-type conductive layer and the N-type conductive layer along the width direction can be set to be smaller, and good conductivity can be obtained, so that the dimension of the semiconductor device occupied by the diode in the length direction and the width direction can be greatly reduced, the area occupied by the semiconductor device on the first surface can be reduced, the area of the semiconductor device on the first surface can be reduced, the cost of the semiconductor device can be reduced, and meanwhile, contribution to realizing a multichannel product can be made.
Since the second trench itself needs to be processed on the substrate when the semiconductor device includes a field effect transistor, the second insulating layer, the first conductive layer, the second conductive layer, and the like are formed in the trench. Therefore, when the dimensions of the first trench and the second trench in the first direction are the same, that is, the depths of the first trench and the second trench are the same, the first trench and the second trench can be processed in the same process.
Drawings
The invention is further described with reference to the accompanying drawings:
fig. 1 is a structural view of a semiconductor device in the prior art;
FIG. 2 is a top view of FIG. 1;
FIG. 3 is a block diagram of a semiconductor device in one embodiment of the present application;
FIG. 4 is a top view of FIG. 3;
fig. 5 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present application.
Icon: 10-a substrate; 11-a first surface; 12-a second surface; 13-a first trench; 14-a second trench; 15-a third trench; 20-diodes; a 21-P type conductive layer; a 22-N type conductive layer; 30-an insulating layer; 41-a first insulating layer; 42-a second insulating layer; 43-a third insulating layer; 44-a fourth insulating layer; 45-a fifth insulating layer; 46-a sixth insulating layer; 50-field effect transistor; 51-a first conductive layer; 52-a second conductive layer; 60-isolating belt; 70-metal layer.
Detailed Description
For a clearer understanding of technical features, objects, and effects of the present invention, a detailed description of embodiments of the present invention will be made with reference to the accompanying drawings.
The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments, and all other embodiments obtained by those skilled in the art without making creative efforts based on the embodiments of the present invention are included in the protection scope of the present invention.
In the prior art, as shown in fig. 1, a diode 20 in a semiconductor device includes a P-type conductive layer 21 and an N-type conductive layer 22, wherein the P-type conductive layer 21 and the N-type conductive layer 22 are both disposed on an insulating layer 30 disposed on a first surface 11 of a substrate 10. To ensure the conductivity of the diode 20, as shown in fig. 2, the PN junction width of the diode 20 is relatively large, that is, the projected area of the P-type conductive layer 21 on the first surface and the projected area of the N-type conductive layer 22 on the first surface are both large, which results in a large size of the first surface of the semiconductor device, thereby resulting in a large volume and a large cost of the semiconductor device.
For convenience of description, three directions may be defined first, namely, an X direction (second direction), a Y direction (third direction) and a Z direction (first direction), and are perpendicular to each other. The X-direction indicates the longitudinal direction of the semiconductor device, the Y-direction indicates the width direction of the semiconductor device, and the Z-direction indicates the thickness direction, i.e., the height direction of the semiconductor device.
Example 1
As shown in fig. 3, an embodiment of the present invention provides a semiconductor device including a substrate 10, a diode 20, and a first insulating layer 41; the substrate 10 has a first surface 11, a first trench 13 is provided on the first surface 11, and a first insulating layer 41 is attached to an inner wall of the first trench 13; the diode 20 includes a P-type conductive layer 21 and an N-type conductive layer 22, the P-type conductive layer 21 and the N-type conductive layer 22 are both located in the first trench 13, a part of the first insulating layer 41 is located between the P-type conductive layer 21 and the substrate 10, a part of the first insulating layer 41 is located between the N-type conductive layer 22 and the substrate 10, and the P-type conductive layer 21 and the N-type conductive layer 22 are connected and laminated along the Z-direction.
The P-type conductive layer 21 and the N-type conductive layer 22 are stacked along the Z-direction of the substrate 10, so that the cross-sectional area thereof can be increased, the dimensions of the P-type conductive layer 21 and the N-type conductive layer 22 along the X-direction can be set to be smaller, the dimensions of the P-type conductive layer 21 and the N-type conductive layer 22 along the Y-direction can be set to be smaller, and better conductivity can be obtained, so that the dimensions of the semiconductor device occupied by the diode 20 in the X-direction and the Y-direction can be greatly reduced, the area occupied by the first surface 11 of the semiconductor device can be further reduced, the area of the first surface 11 of the semiconductor device can be further reduced, the cost of the semiconductor device can be further reduced, and meanwhile, the multi-channel product can be realized.
Optionally, as shown in fig. 3, the first surface 11 is further provided with a second trench 14, and the semiconductor device further includes a second insulating layer 42, a third insulating layer 43, and a field effect transistor 50, where the second insulating layer 42 is attached to an inner wall of the second trench 14; the field effect transistor 50 includes a first conductive layer 51 and a second conductive layer 52 located in the second trench 14, a portion of the second insulating layer 42 is located between the first conductive layer 51 and the substrate 10, a portion of the second insulating layer 42 is located between the second conductive layer 52 and the substrate 10, the first conductive layer 51 and the second conductive layer 52 are stacked in the Z direction, and the third insulating layer 43 is located between the first conductive layer 51 and the second conductive layer 52. Wherein, the first conductive layer 51 and the second conductive layer 52 may be gates.
Specifically, as shown in fig. 3, the number of the first conductive layers 51 and the second conductive layers 52 in the field-effect transistor 50 may be plural, the number of the third insulating layers 43 and the second insulating layers 42 may be plural, and the numbers of the first conductive layers 51, the second conductive layers 52, the second insulating layers 42, and the third insulating layers 43 are the same. A third insulating layer 43 is disposed between each first conductive layer 51 and each second conductive layer 52, a portion of each second insulating layer 42 is disposed between the first conductive layer 51 and the substrate 10, and another portion of each second insulating layer 42 is disposed between the second conductive layer 52 and the substrate 10. The plurality of first conductive layers 51 are connected, and the plurality of second conductive layers 52 are connected.
Since the first conductive layer 51 and the second conductive layer 52 in the field-effect transistor 50 are also stacked in the Z-direction, the stacking direction thereof is the same as the stacking direction of the P-type conductive layer 21 and the N-type conductive layer 22 of the diode 20. In addition, since the field effect transistor 50 itself has a certain thickness, the sum of the dimensions of the P-type conductive layer 21 and the N-type conductive layer 22 in the Z-direction can also be the same as the thickness of the field effect transistor 50, and therefore, there is no need to increase the thickness of the semiconductor device, and the dimensions of the diode 20 in the X-direction and the Y-direction can also be reduced, whereby a better conductivity of the diode 20 can also be obtained on the basis of a reduced area of the first surface 11 of the semiconductor device.
Alternatively, as shown in fig. 3, the first trench 13 and the second trench 14 have the same size in the Z direction. Since the second trench 14 itself needs to be processed on the substrate 10 when the semiconductor device includes the field effect transistor 50, the second insulating layer 42, the first conductive layer 51, the second conductive layer 52, and the like are formed in the second trench 14. Therefore, when the dimensions of the first trench 13 and the second trench 14 in the Z direction are the same, that is, the depths of the first trench 13 and the second trench 14 are the same, the first trench 13 and the second trench 14 can be processed in the same process.
Alternatively, as shown in fig. 3, the P-type conductive layer 21 is closer to the first surface 11 than the N-type conductive layer 22, the first conductive layer 51 is closer to the first surface 11 than the second conductive layer 52, and the N-type conductive layer 22 and the second conductive layer 52 have the same dimension in the Z-direction. Thus, when the N-type conductive layer 22 and the second conductive layer 52 are made of the same material, the N-type conductive layer 22 and the second conductive layer 52 can be manufactured in the same process, so that the manufacturing process of the semiconductor device is not increased as much as possible, and the manufacturing cost is saved.
Alternatively, as shown in fig. 3, the number of diodes 20, first trenches 13, and first insulating layers 41 are all plural and the same; the plurality of first insulating layers 41 and the plurality of diodes 20 are located in the plurality of first trenches 13 in one-to-one correspondence, the P-type conductive layer 21 of each diode 20 is connected, and the N-type conductive layer 22 of each diode 20 is connected. Specifically, the N-type conductive layer 22 of each diode 20 is connected by a wire or a metal device. In this way, the sum of the cross-sectional areas obtained by cutting each diode 20 in the plane determined by the X-direction and the Z-direction is larger, so that the occupied area of the diode 20 on the first surface 11 can be further reduced, and the manufacturing cost can be further saved.
Alternatively, as shown in fig. 4, a plurality of diodes 20 are arranged along the X-direction, each diode 20 extends along the Y-direction, and the X-direction and the Y-direction are perpendicular to the Z-direction, and an included angle is formed between the X-direction and the Y-direction. Specifically, the angle between the X-direction and the Y-direction may be 90 °.
The plurality of first conductive layers 51 are also arranged in the X direction and extend in the Y direction. The plurality of second conductive layers 52 are also arranged in the X-direction and extend in the Y-direction. This facilitates the fabrication of diode 20 and field effect transistor 50.
Optionally, as shown in fig. 3, the semiconductor device further includes an isolation strip 60, and the diode 20 and the field effect transistor 50 are respectively located at two sides of the isolation strip 60. Specifically, a third groove 15 is further provided on the first surface 11, and the isolation belt 60 is located in the third groove 15. The isolation tape 60 can isolate the diode 20 and the field effect transistor 50 located on both sides of the isolation tape 60, so that the reduction of the withstand voltage capability of the field effect transistor 50 side can be prevented.
Optionally, as shown in fig. 3, the semiconductor device further includes a fourth insulating layer 44 and a fifth insulating layer 45, where the fourth insulating layer 44 covers the P-type conductive layer 21 and is located in the first trench 13, and a surface of the fourth insulating layer 44 facing away from the P-type conductive layer 21 is flush with the first surface 11; the fifth insulating layer 45 is disposed on the first surface 11, and partially covers the fourth insulating layer 44. A portion of the fifth insulating layer 45 also overlies the first conductive layer 51. In this way, after the diode 20 is disposed in the first trench 13, the entire first surface 11 is as flat as possible, so as to facilitate the wiring arrangement of the integrated circuit, thereby improving the stability of circuit connection.
As shown in fig. 3, the semiconductor device further includes a sixth insulating layer 46, wherein a dimension of the sixth insulating layer 46 in the Z-direction is larger than a dimension of the fifth insulating layer 45 in the Z-direction, and the sixth insulating layer 46 covers the isolation belt 60. A portion of the fifth insulating layer 45 covering the fourth insulating layer 44 and a portion of the fifth insulating layer 45 covering the first conductive layer 51 are located on both sides of the sixth insulating layer 46, respectively.
As shown in fig. 3, the substrate 10 further includes a second surface 12 opposite the first surface 11, and the semiconductor device further includes a metal layer 70 provided on the second surface.
The invention also provides electronic equipment comprising a circuit board and the semiconductor device of any one of the above, wherein the semiconductor device is electrically connected with the circuit board. The electronic apparatus can achieve all the effects of the above-described semiconductor device.
Example two
The embodiment of the invention also provides a manufacturing method of the semiconductor device, which comprises the following steps:
s101, a substrate 10 is provided.
Wherein the substrate 10 has opposite first and second surfaces 11, 11.
S102, etching treatment is performed on the first surface 11 to form a first trench 13 and a second trench 14 which are spaced apart.
Wherein the dimensions of the first trench 13 and the second trench 14 in the Z direction of the semiconductor may be the same, whereby the first trench 13 and the second trench 14 may be processed in the same process.
S103, a first insulating layer 41 is formed in the first trench 13, and a second insulating layer 42 is formed in the second trench 14.
The thickness of the first insulating layer 41 is the same as the thickness of the second insulating layer 42, and the material of the first insulating layer 41 and the material of the second insulating layer 42 are the same, so that the first insulating layer 41 and the second insulating layer 42 can be formed in the same process.
S104, the N-type conductive layer 22 is formed on the first insulating layer 41, and the second conductive layer 52 is formed on the second insulating layer 42.
Wherein the N-type conductive layer 22 is located in the first trench 13 and the second conductive layer 52 is located in the second trench 14. The dimension of the N-type conductive layer 22 along the Z-direction is the same as the dimension of the second conductive layer 52 along the Z-direction, and when the material of the N-type conductive layer 22 is the same as the material of the second conductive layer 52, the N-type conductive layer 22 and the second conductive layer 52 can be formed in the same process.
S105, the P-type conductive layer 21 is formed on the N-type conductive layer 22.
The P-type conductive layer 21 is located in the first trench 13.
S106, the third insulating layer 43 and the first conductive layer 51 are sequentially formed on the second conductive layer 52.
Wherein the third insulating layer 43 and the first conductive layer 51 are both located within the second trench 14.
The P-type conductive layer 21 and the N-type conductive layer 22 are stacked along the Z-direction of the substrate 10, so that the cross-sectional area thereof can be increased, the dimensions of the P-type conductive layer 21 and the N-type conductive layer 22 along the X-direction can be set to be smaller, the dimensions of the P-type conductive layer 21 and the N-type conductive layer 22 along the Y-direction can be set to be smaller, and better conductivity can be obtained, so that the dimensions of the semiconductor device occupied by the diode 20 in the X-direction and the Y-direction can be greatly reduced, the area occupied by the first surface 11 of the semiconductor device can be further reduced, the area of the first surface 11 of the semiconductor device can be further reduced, the cost of the semiconductor device can be further reduced, and meanwhile, the multi-channel product can be realized.
Further, since the first conductive layer 51 and the second conductive layer 52 in the field effect transistor 50 are also stacked in the Z direction, the stacking direction thereof is the same as the stacking direction of the P-type conductive layer 21 and the N-type conductive layer 22 of the diode 20. In addition, since the field effect transistor 50 itself has a certain thickness, the sum of the dimensions of the P-type conductive layer 21 and the N-type conductive layer 22 in the Z-direction can also be the same as the thickness of the field effect transistor 50, and therefore, there is no need to increase the thickness of the semiconductor device, and the dimensions of the diode 20 in the X-direction and the Y-direction can also be reduced, whereby a better conductivity of the diode 20 can also be obtained on the basis of a reduced area of the first surface 11 of the semiconductor device.
While the invention has been described with reference to several particular embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (10)
1. A semiconductor device is characterized by comprising a substrate, a diode and a first insulating layer;
the substrate is provided with a first surface, a first groove is formed on the first surface, and the first insulating layer is attached to the inner wall of the first groove;
the diode comprises a P-type conductive layer and an N-type conductive layer, wherein the P-type conductive layer and the N-type conductive layer are both positioned in the first groove, a part of the first insulating layer is positioned between the P-type conductive layer and the substrate, a part of the first insulating layer is positioned between the N-type conductive layer and the substrate, the P-type conductive layer and the N-type conductive layer are connected and are laminated along a first direction, and the first direction is the thickness direction of the substrate.
2. The semiconductor device according to claim 1, wherein a second trench is further provided on the first surface, the semiconductor device further comprising a second insulating layer, a third insulating layer, and a field effect transistor, the second insulating layer being attached to an inner wall of the second trench;
the field effect transistor comprises a first conductive layer and a second conductive layer which are positioned in the second groove, part of the second insulating layer is positioned between the first conductive layer and the substrate, part of the second insulating layer is positioned between the second conductive layer and the substrate, the first conductive layer and the second conductive layer are laminated along the first direction, and the third insulating layer is positioned between the first conductive layer and the second conductive layer.
3. The semiconductor device according to claim 2, wherein a dimension of the first trench and the second trench in the first direction is the same.
4. The semiconductor device of claim 2, wherein the P-type conductive layer is closer to the first surface than the N-type conductive layer, the first conductive layer is closer to the first surface than the second conductive layer, and the N-type conductive layer is the same size as the second conductive layer in a first direction.
5. The semiconductor device according to claim 1 or 2, wherein the number of the diode, the first trench, and the first insulating layer are all plural and the same;
the first insulating layers and the diodes are located in the first grooves in a one-to-one correspondence mode, the P-type conducting layers of the diodes are connected, and the N-type conducting layers of the diodes are connected.
6. The semiconductor device according to claim 1 or 2, wherein a plurality of the diodes are arranged in a second direction, each of the diodes extends in a third direction, the second direction and the third direction are each perpendicular to the first direction, and an included angle is formed between the second direction and the third direction.
7. The semiconductor device according to claim 2, further comprising an isolation strap, wherein the diode and the field effect transistor are located on both sides of the isolation strap, respectively.
8. The semiconductor device of claim 1, 2 or 7, further comprising a fourth insulating layer overlying the P-type conductive layer and within the first trench, a surface of the fourth insulating layer facing away from the P-type conductive layer being flush with the first surface; the fifth insulating layer is arranged on the first surface and partially covers the fourth insulating layer.
9. An electronic device comprising a circuit board and the semiconductor device of any one of claims 1-8, the semiconductor device being electrically connected to the circuit board.
10. A method of fabricating a semiconductor device, the method comprising:
providing a substrate, wherein the substrate is provided with a first surface;
etching the first surface to form a first groove and a second groove which are spaced;
forming a first insulating layer in the first trench and forming a second insulating layer in the second trench;
forming an N-type conductive layer on the first insulating layer, and forming a second conductive layer on the second insulating layer;
forming a P-type conductive layer on the N-type conductive layer;
and forming a third insulating layer and a first conductive layer on the second conductive layer in sequence.
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| CN202211569464.5A CN116013920A (en) | 2022-12-08 | 2022-12-08 | Semiconductor device, manufacturing method of semiconductor device and electronic equipment |
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| CN202211569464.5A CN116013920A (en) | 2022-12-08 | 2022-12-08 | Semiconductor device, manufacturing method of semiconductor device and electronic equipment |
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| CN116013920A true CN116013920A (en) | 2023-04-25 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102270662A (en) * | 2010-06-01 | 2011-12-07 | 万国半导体股份有限公司 | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts |
| CN103956388A (en) * | 2014-03-19 | 2014-07-30 | 中航（重庆）微电子有限公司 | Schottky diode semiconductor device and preparation method thereof |
| CN210296387U (en) * | 2018-07-25 | 2020-04-10 | 半导体元件工业有限责任公司 | Trench diode and power semiconductor device |
| CN111564543A (en) * | 2020-05-12 | 2020-08-21 | 厦门乾照光电股份有限公司 | Vertical high-voltage light-emitting diode chip and manufacturing method thereof |
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- 2022-12-08 CN CN202211569464.5A patent/CN116013920A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270662A (en) * | 2010-06-01 | 2011-12-07 | 万国半导体股份有限公司 | Semiconductor power devices manufactured with self-aligned processes and more reliable electrical contacts |
| CN103956388A (en) * | 2014-03-19 | 2014-07-30 | 中航（重庆）微电子有限公司 | Schottky diode semiconductor device and preparation method thereof |
| CN210296387U (en) * | 2018-07-25 | 2020-04-10 | 半导体元件工业有限责任公司 | Trench diode and power semiconductor device |
| CN111564543A (en) * | 2020-05-12 | 2020-08-21 | 厦门乾照光电股份有限公司 | Vertical high-voltage light-emitting diode chip and manufacturing method thereof |
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