TWI763029B - Vertical bipolar transistor device - Google Patents

Vertical bipolar transistor device Download PDF

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TWI763029B
TWI763029B TW109130770A TW109130770A TWI763029B TW I763029 B TWI763029 B TW I763029B TW 109130770 A TW109130770 A TW 109130770A TW 109130770 A TW109130770 A TW 109130770A TW I763029 B TWI763029 B TW I763029B
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heavily doped
epitaxial layer
semiconductor epitaxial
bipolar transistor
transistor device
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TW109130770A
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TW202205605A (en
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葉致廷
黃菘志
莊哲豪
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晶焱科技股份有限公司
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Abstract

A vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one doped well, an isolation structure, and an external conductor. The heavily-doped semiconductor substrate and the doped well have a first conductivity type, and the first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The doped well is formed in the first semiconductor epitaxial layer. The isolation structure, formed in the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer, surrounds the first semiconductor epitaxial layer and the at least one doped well. The external conductor is arranged outside the first semiconductor epitaxial layer and the doped well and electrically connected to the first semiconductor epitaxial layer and the doped well.

Description

垂直式雙極性電晶體裝置Vertical Bipolar Transistor Device

本發明係關於一種垂直式靜電放電技術，且特別關於一種垂直式雙極性電晶體裝置。The present invention relates to a vertical electrostatic discharge technique, and in particular to a vertical bipolar transistor device.

靜電放電（ESD）損壞已成為以奈米級互補式金氧半(CMOS)工藝製造的CMOS積體電路(IC)產品的主要可靠性問題。靜電放電保護裝置通常設計為用於釋放靜電放電能量，因此可以防止積體電路晶片受到靜電放電損壞。Electrostatic discharge (ESD) damage has become a major reliability issue for CMOS integrated circuit (IC) products fabricated in nanoscale complementary metal-oxide-semiconductor (CMOS) processes. ESD protection devices are typically designed to discharge ESD energy and thus protect integrated circuit chips from ESD damage.

靜電放電保護裝置的工作原理如第1圖所示，在印刷電路板（PCB）上，靜電放電保護裝置8並聯欲保護裝置9，當ESD情況發生時，靜電放電保護裝置8係瞬間被觸發，同時，靜電放電保護裝置8亦可提供一低電阻路徑，以供暫態之ESD電流進行放電，讓ESD暫態電流之能量透過靜電放電保護裝置8得以釋放。為了降低靜電放電保護裝置8所佔據的體積與面積，故實現垂直式暫態電壓抑制器以取代橫向暫態電壓抑制器。舉例來說，在美國專利號8928084中，橫向靜電放電保護裝置設於一磊晶層中，且電極設於靜電放電保護裝置之表面。因此，電極佔據許多足印(footprint)區域。在美國專利號9666700中，設於靜電放電保護裝置之表面的電極亦佔據許多足印區域。此外，傳統垂直式暫態電壓抑制器具有某些缺點。在美國專利號7750365中，雖然絕緣式閘極雙極性電晶體為垂直式暫態電壓抑制器，但絕緣式閘極雙極性電晶體需要在晶圓背面多進行一道佈植製程。在美國專利號7781826中，基板與磊晶層屬於相同導電型。此外，P型井區作為雙載子接面電晶體之基極。崩潰介面位於P型井區與磊晶層之間。因為P型井區之深度取決於基極之寬度，故介面之崩潰電壓是難以控制的。The working principle of the electrostatic discharge protection device is shown in Figure 1. On the printed circuit board (PCB), the electrostatic discharge protection device 8 is connected in parallel with the protection device 9. When an ESD situation occurs, the electrostatic discharge protection device 8 is instantly triggered. Meanwhile, the electrostatic discharge protection device 8 can also provide a low resistance path for the transient ESD current to discharge, so that the energy of the ESD transient current can be released through the electrostatic discharge protection device 8 . In order to reduce the volume and area occupied by the electrostatic discharge protection device 8, a vertical transient voltage suppressor is implemented to replace the lateral transient voltage suppressor. For example, in US Pat. No. 8,928,084, the lateral ESD protection device is provided in an epitaxial layer, and the electrodes are provided on the surface of the ESD protection device. Thus, the electrodes occupy many footprint areas. In US Pat. No. 9,666,700, the electrodes disposed on the surface of the ESD protection device also occupy many of the footprint areas. Furthermore, conventional vertical transient voltage suppressors have certain disadvantages. In US Pat. No. 7,750,365, although the insulated gate bipolar transistor is a vertical transient voltage suppressor, the insulated gate bipolar transistor requires an additional implantation process on the backside of the wafer. In US Pat. No. 7,781,826, the substrate and the epitaxial layer are of the same conductivity type. In addition, the P-well region serves as the base of the bi-carrier junction transistor. The collapse interface is located between the P-type well region and the epitaxial layer. Because the depth of the P-well depends on the width of the base, the breakdown voltage of the interface is difficult to control.

因此，本發明係在針對上述的困擾，提出一種垂直式雙極性電晶體裝置，以解決習知所產生的問題。Therefore, the present invention proposes a vertical bipolar transistor device to solve the above-mentioned problems.

本發明提供一種垂直式雙極性電晶體裝置，其係自由地調整雙載子接面電晶體之增益與崩潰電壓。The present invention provides a vertical bipolar transistor device which can freely adjust the gain and breakdown voltage of the bipolar junction transistor.

本發明提供一種垂直式雙極性電晶體裝置，其包含一重摻雜半導體基板、一第一半導體磊晶層、至少一摻雜井區、一隔離結構與一外部導體。重摻雜半導體基板與摻雜井區具有第一導電型，第一半導體磊晶層具有第二導電型。第一半導體磊晶層設於重摻雜半導體基板上，摻雜井區設於第一半導體磊晶層中。隔離結構設於重摻雜半導體基板與第一半導體磊晶層中，並圍繞第一半導體磊晶層與摻雜井區。外部導體設於摻雜井區與第一半導體磊晶層之外側，並電性連接摻雜井區與第一半導體磊晶層。The invention provides a vertical bipolar transistor device, which comprises a heavily doped semiconductor substrate, a first semiconductor epitaxial layer, at least one doped well region, an isolation structure and an outer conductor. The heavily doped semiconductor substrate and the doped well region have a first conductivity type, and the first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is disposed on the heavily doped semiconductor substrate, and the doped well region is disposed in the first semiconductor epitaxial layer. The isolation structure is arranged in the heavily doped semiconductor substrate and the first semiconductor epitaxial layer, and surrounds the first semiconductor epitaxial layer and the doped well region. The outer conductor is arranged on the outside of the doped well region and the first semiconductor epitaxial layer, and is electrically connected to the doped well region and the first semiconductor epitaxial layer.

在本發明之一實施例中，第一導電型為N型，第二導電型為P型。In an embodiment of the present invention, the first conductivity type is N-type, and the second conductivity type is P-type.

在本發明之一實施例中，第一導電型為P型，第二導電型為N型。In an embodiment of the present invention, the first conductivity type is P-type, and the second conductivity type is N-type.

在本發明之一實施例中，垂直式雙極性電晶體裝置更包含至少一第一重摻雜區與至少一第二重摻雜區。第一重摻雜區具有第一導電型，第一重摻雜區設於摻雜井區中。第二重摻雜區具有第二導電型，第二重摻雜區設於第一半導體磊晶層中。第一半導體磊晶層透過第一重摻雜區、第二重摻雜區與外部導體電性連接摻雜井區。In one embodiment of the present invention, the vertical bipolar transistor device further includes at least one first heavily doped region and at least one second heavily doped region. The first heavily doped region has a first conductivity type, and the first heavily doped region is disposed in the doped well region. The second heavily doped region has a second conductivity type, and the second heavily doped region is disposed in the first semiconductor epitaxial layer. The first semiconductor epitaxial layer is electrically connected to the doped well region through the first heavily doped region and the second heavily doped region and the outer conductor.

在本發明之一實施例中，第二重摻雜區圍繞第一重摻雜區與摻雜井區。In an embodiment of the present invention, the second heavily doped region surrounds the first heavily doped region and the doped well region.

在本發明之一實施例中，第一重摻雜區之數量為複數個，第二重摻雜區之數量為複數個，摻雜井區之數量為複數個，所有第一重摻雜區分別設於所有摻雜井區中，所有摻雜井區與所有第二重摻雜區交替設置。In an embodiment of the present invention, the number of the first heavily doped regions is plural, the number of the second heavily doped regions is plural, the number of the doped well regions is plural, and all the first heavily doped regions They are respectively arranged in all doped well regions, and all doped well regions and all second heavily doped regions are alternately arranged.

在本發明之一實施例中，垂直式雙極性電晶體裝置更包含一重摻雜埋層，其係設於重摻雜半導體基板與第一半導體磊晶層之間，並位於摻雜井區之正下方。In one embodiment of the present invention, the vertical bipolar transistor device further includes a heavily doped buried layer, which is disposed between the heavily doped semiconductor substrate and the first semiconductor epitaxial layer, and is located between the doped well region Directly below.

在本發明之一實施例中，重摻雜埋層具有第一導電型，隔離結構之底部深於介於重摻雜埋層與第一半導體磊晶層之間的介面。In one embodiment of the present invention, the heavily doped buried layer has a first conductivity type, and the bottom of the isolation structure is deeper than the interface between the heavily doped buried layer and the first semiconductor epitaxial layer.

在本發明之一實施例中，重摻雜埋層具有第二導電型，隔離結構之底部深於介於重摻雜埋層與重摻雜半導體基板之間的介面。In one embodiment of the present invention, the heavily doped buried layer has the second conductivity type, and the bottom of the isolation structure is deeper than the interface between the heavily doped buried layer and the heavily doped semiconductor substrate.

在本發明之一實施例中，重摻雜埋層接觸隔離結構。In one embodiment of the present invention, the heavily doped buried layer contacts the isolation structure.

在本發明之一實施例中，重摻雜半導體基板電性連接一第一接腳，且外部導體電性連接一第二接腳。In an embodiment of the present invention, the heavily doped semiconductor substrate is electrically connected to a first pin, and the outer conductor is electrically connected to a second pin.

在本發明之一實施例中，垂直式雙極性電晶體裝置更包含一第二半導體磊晶層，其係設於重摻雜半導體基板與第一半導體磊晶層之間，並位於摻雜井區之正下方。In an embodiment of the present invention, the vertical bipolar transistor device further includes a second semiconductor epitaxial layer, which is disposed between the heavily doped semiconductor substrate and the first semiconductor epitaxial layer and located in the doping well directly below the area.

在本發明之一實施例中，第二半導體磊晶層具有第一導電型，隔離結構之底部深於介於第二半導體磊晶層與第一半導體磊晶層之間的介面。In one embodiment of the present invention, the second semiconductor epitaxial layer has the first conductivity type, and the bottom of the isolation structure is deeper than the interface between the second semiconductor epitaxial layer and the first semiconductor epitaxial layer.

在本發明之一實施例中，第二半導體磊晶層具有第二導電型，隔離結構之底部深於介於第二半導體磊晶層與重摻雜半導體基板之間的介面。In one embodiment of the present invention, the second semiconductor epitaxial layer has the second conductivity type, and the bottom of the isolation structure is deeper than the interface between the second semiconductor epitaxial layer and the heavily doped semiconductor substrate.

基於上述，垂直式雙極性電晶體裝置根據第一半導體磊晶層之電阻率與厚度，自由地調整雙載子接面電晶體之增益與崩潰電壓。垂直式雙極性電晶體裝置可根據第一半導體磊晶層與重摻雜埋層之電阻率，具有大範圍之崩潰電壓。Based on the above, the vertical bipolar transistor device can freely adjust the gain and breakdown voltage of the bipolar junction transistor according to the resistivity and thickness of the first semiconductor epitaxial layer. The vertical bipolar transistor device can have a wide range of breakdown voltages according to the resistivity of the first semiconductor epitaxial layer and the heavily doped buried layer.

茲為使　貴審查委員對本發明的結構特徵及所達成的功效更有進一步的瞭解與認識，謹佐以較佳的實施例圖及配合詳細的說明，說明如後：Hereby, in order to make your examiners have a further understanding and understanding of the structural features of the present invention and the effects achieved, I would like to assist with the preferred embodiment drawings and coordinate detailed descriptions, and the descriptions are as follows:

本發明之實施例將藉由下文配合相關圖式進一步加以解說。盡可能的，於圖式與說明書中，相同標號係代表相同或相似構件。於圖式中，基於簡化與方便標示，形狀與厚度可能經過誇大表示。可以理解的是，未特別顯示於圖式中或描述於說明書中之元件，為所屬技術領域中具有通常技術者所知之形態。本領域之通常技術者可依據本發明之內容而進行多種之改變與修改。Embodiments of the present invention will be further explained with the help of the related drawings below. Wherever possible, in the drawings and the description, the same reference numbers refer to the same or similar components. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It should be understood that the elements not particularly shown in the drawings or described in the specification have forms known to those of ordinary skill in the art. Those skilled in the art can make various changes and modifications based on the content of the present invention.

除非另有說明，否則某些條件句子或單詞，例如“可以”，“可能”，“可能”或“可能”，通常試圖表示本發明中的實施例具有的含義，但也可以解釋為可能不需要的功能，元素或步驟。 在其他實施例中，可能不需要這些特徵，元素或步驟。Certain conditional sentences or words, such as "may", "may", "may" or "may", are generally intended to mean what an embodiment in this invention has, but can also be interpreted as possibly not unless otherwise stated The required function, element or step. In other embodiments, these features, elements or steps may not be required.

於下文中關於“一個實施例”或“一實施例”之描述係指關於至少一實施例內所相關連之一特定元件、結構或特徵。因此，於下文中多處所出現之“一個實施例”或 “一實施例”之多個描述並非針對同一實施例。再者，於一或多個實施例中之特定構件、結構與特徵可依照一適當方式而結合。The following description of "one embodiment" or "an embodiment" refers to a particular element, structure or feature associated with at least one embodiment. Thus, the appearances of "one embodiment" or "an embodiment" in various places below are not directed to the same embodiment. Furthermore, the specific components, structures and features in one or more embodiments may be combined in a suitable manner.

在整個說明書和申請專利範圍中使用某些術語來指代特定部件。 本領域的技術人員意識到，組件可以被稱為不同的名稱。本公開內容不旨在區分名稱不同但功能相同的組件。在說明書和申請專利範圍中，術語“包括”以開放式方式使用，因此應解釋為表示“包括但不限於”。 短語“被耦合到”、“耦合到”和“正耦合到”旨在包括任何間接或直接連接。 因此，如果本揭露提到第一設備與第二設備耦合，則意味著第一設備可以通過電連接、無線通信、光通信或其他信號連接在有/無直接或間接地利用其他中間設備或連接方式連接到第二設備。Certain terms are used throughout the specification and claims to refer to specific components. Those skilled in the art realize that components may be called by different names. This disclosure is not intended to distinguish between components that have different names but have the same function. In the specification and claims, the term "including" is used in an open-ended fashion and should therefore be interpreted to mean "including but not limited to". The phrases "coupled to", "coupled to" and "being coupled to" are intended to include any indirect or direct connection. Therefore, if this disclosure mentions that a first device is coupled with a second device, it means that the first device may utilize other intermediate devices or connections, either directly or indirectly, through electrical connections, wireless communications, optical communications, or other signal connections, with/without way to connect to the second device.

為了降低靜電放電保護裝置所佔據的面積，並在不需要增加靜電放電保護裝置所佔據的面積的前提下，增強靜電放電等級，且達到均勻的電流分布與優良的熱散逸，提供一種垂直式雙極性電晶體裝置。In order to reduce the area occupied by the electrostatic discharge protection device, enhance the level of electrostatic discharge without increasing the area occupied by the electrostatic discharge protection device, and achieve uniform current distribution and excellent heat dissipation, a vertical dual Polarized transistor device.

第2圖為本發明之垂直式雙極性電晶體裝置之第一實施例之結構剖視圖。以下請參閱第2圖，並介紹本發明之垂直式雙極性電晶體裝置10之第一實施例，其係包含一重摻雜半導體基板12、一第一半導體磊晶層14、至少一摻雜井區16、一隔離結構18與一外部導體20。在第一實施例中，係使用一個或多個摻雜井區16。為了清楚與方便，第一實施例係以一個摻雜井區16為例。重摻雜半導體基板12與摻雜井區16具有第一導電型，第一半導體磊晶層14具有第二導電型。在第一實施例中，第一導電型為N型，第二導電型為P型。FIG. 2 is a cross-sectional view of the structure of the first embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 2 below, and introduce a first embodiment of the vertical bipolar transistor device 10 of the present invention, which includes a heavily doped semiconductor substrate 12 , a first semiconductor epitaxial layer 14 , and at least one doped well Region 16 , an isolation structure 18 and an outer conductor 20 . In the first embodiment, one or more doped well regions 16 are used. For the sake of clarity and convenience, the first embodiment takes one doped well region 16 as an example. The heavily doped semiconductor substrate 12 and the doped well region 16 have a first conductivity type, and the first semiconductor epitaxial layer 14 has a second conductivity type. In the first embodiment, the first conductivity type is N type, and the second conductivity type is P type.

第一半導體磊晶層14設於重摻雜半導體基板12上，摻雜井區16設於第一半導體磊晶層14中。重摻雜半導體基板12、第一半導體磊晶層14與摻雜井區16形成一雙載子接面電晶體，其中第一半導體磊晶層14作為雙載子接面電晶體之基極。因為第一半導體磊晶層14之電阻率與厚度容易調整，所以根據第一半導體磊晶層14之電阻率與厚度可以自由調整雙載子接面電晶體之增益與崩潰電壓。隔離結構18之材質可為氧化物或絕緣材質，但本發明並不以此為限。隔離結構18設於重摻雜半導體基板12與第一半導體磊晶層14中，並圍繞摻雜井區16與第一半導體磊晶層14。實際上，垂直式雙極性電晶體裝置10為從晶圓上切割下來之一晶粒。當晶粒從晶圓上切割下時，晶粒沿著隔離結構18之外側切割，以避免對介於重摻雜半導體基板12與第一半導體磊晶層14之間的崩潰介面造成傷害。外部導體20包含但不限於導電層及銲線。舉例來說，外部導體20可為設於第一半導體磊晶層14與摻雜井區16之外側之導電層。具體而言，導電層設於第一半導體磊晶層14與摻雜井區16之頂部。重摻雜半導體基板12電性連接一第一接腳22。外部導體20電性連接一第二接腳24。The first semiconductor epitaxial layer 14 is disposed on the heavily doped semiconductor substrate 12 , and the doped well region 16 is disposed in the first semiconductor epitaxial layer 14 . The heavily doped semiconductor substrate 12 , the first semiconductor epitaxial layer 14 and the doped well region 16 form a dual carrier junction transistor, wherein the first semiconductor epitaxial layer 14 serves as the base of the dual carrier junction transistor. Since the resistivity and thickness of the first semiconductor epitaxial layer 14 can be easily adjusted, the gain and breakdown voltage of the bipolar junction transistor can be freely adjusted according to the resistivity and thickness of the first semiconductor epitaxial layer 14 . The material of the isolation structure 18 can be oxide or insulating material, but the invention is not limited thereto. The isolation structure 18 is disposed in the heavily doped semiconductor substrate 12 and the first semiconductor epitaxial layer 14 and surrounds the doped well region 16 and the first semiconductor epitaxial layer 14 . In practice, the vertical bipolar transistor device 10 is a die cut from a wafer. When the die is cut from the wafer, the die is cut along the outside of the isolation structure 18 to avoid damage to the collapsed interface between the heavily doped semiconductor substrate 12 and the first semiconductor epitaxial layer 14 . The outer conductor 20 includes, but is not limited to, conductive layers and bonding wires. For example, the outer conductor 20 may be a conductive layer disposed outside the first semiconductor epitaxial layer 14 and the doped well region 16 . Specifically, the conductive layer is disposed on top of the first semiconductor epitaxial layer 14 and the doped well region 16 . The heavily doped semiconductor substrate 12 is electrically connected to a first pin 22 . The outer conductor 20 is electrically connected to a second pin 24 .

當正靜電放電能量施加在第一接腳22，且第二接腳24接地時，靜電放電電流從第一接腳22經過重摻雜半導體基板12、第一半導體磊晶層14與摻雜井區16流至第二接腳24。由於外部導體20之存在，第一半導體磊晶層14與摻雜井區16具有相同電壓，所以電流擁擠(current crowding)效應不會發生在摻雜井區16之角落。When positive electrostatic discharge energy is applied to the first pin 22 and the second pin 24 is grounded, the electrostatic discharge current from the first pin 22 passes through the heavily doped semiconductor substrate 12 , the first semiconductor epitaxial layer 14 and the doped well Region 16 flows to second pin 24 . Due to the existence of the outer conductor 20 , the first semiconductor epitaxial layer 14 and the doped well region 16 have the same voltage, so the current crowding effect does not occur at the corners of the doped well region 16 .

第3圖為本發明之垂直式雙極性電晶體裝置之第二實施例之結構剖視圖。請參閱第3圖，並介紹本發明之垂直式雙極性電晶體裝置之第二實施例如下。與第一實施例相比，第二實施例更包含至少一第一重摻雜區26與至少一第二重摻雜區28。第二實施例使用一個或多個第一重摻雜區26與一個或多個第二重摻雜區28。在第二實施例中，以一個第一重摻雜區26與一個第二重摻雜區28為例。第一重摻雜區26具有第一導電型，第二重摻雜區28具有第二導電型。第一重摻雜區26設於摻雜井區16中，第二重摻雜區28設於第一半導體磊晶層14中，第二重摻雜區28可圍繞摻雜井區16與第一重摻雜區26。摻雜井區16透過第一重摻雜區26電性連接外部導體20，第一半導體磊晶層14透過第二重摻雜區28電性連接外部導體20。第一半導體磊晶層14透過第一重摻雜區26、第二重摻雜區28與外部導體20電性連接摻雜井區16。如果外部導體20以導電層實現，則導電層可設於第一重摻雜區26與第二重摻雜區28之頂部。第一重摻雜區26與第二重摻雜區28分別作為摻雜井區16與第一半導體磊晶層14之歐姆接觸，並用來降低外部導體20與摻雜井區16之間的電阻及外部導體20與第一半導體磊晶層14之間的電阻。FIG. 3 is a cross-sectional view of the structure of the second embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 3 and introduce a second embodiment of the vertical bipolar transistor device of the present invention as follows. Compared with the first embodiment, the second embodiment further includes at least one first heavily doped region 26 and at least one second heavily doped region 28 . The second embodiment uses one or more first heavily doped regions 26 and one or more second heavily doped regions 28 . In the second embodiment, a first heavily doped region 26 and a second heavily doped region 28 are used as an example. The first heavily doped region 26 has a first conductivity type, and the second heavily doped region 28 has a second conductivity type. The first heavily doped region 26 is arranged in the doped well region 16 , the second heavily doped region 28 is arranged in the first semiconductor epitaxial layer 14 , and the second heavily doped region 28 can surround the doped well region 16 and the first semiconductor epitaxial layer 14 . A heavily doped region 26 . The doped well region 16 is electrically connected to the outer conductor 20 through the first heavily doped region 26 , and the first semiconductor epitaxial layer 14 is electrically connected to the outer conductor 20 through the second heavily doped region 28 . The first semiconductor epitaxial layer 14 is electrically connected to the doped well region 16 through the first heavily doped region 26 and the second heavily doped region 28 and the outer conductor 20 . If the outer conductor 20 is implemented with a conductive layer, the conductive layer may be provided on top of the first heavily doped region 26 and the second heavily doped region 28 . The first heavily doped region 26 and the second heavily doped region 28 serve as ohmic contacts between the doped well region 16 and the first semiconductor epitaxial layer 14 respectively, and are used to reduce the resistance between the outer conductor 20 and the doped well region 16 and the resistance between the outer conductor 20 and the first semiconductor epitaxial layer 14 .

當正靜電放電能量施加在第一接腳22，且第二接腳24接地時，靜電放電電流從第一接腳22經過重摻雜半導體基板12、第一半導體磊晶層14、摻雜井區16與第一重摻雜區26流至第二接腳24。崩潰介面位於重摻雜半導體基板12與第一半導體磊晶層14之間。由於外部導體20之存在，第一重摻雜區26、第二重摻雜區28、第一半導體磊晶層14與摻雜井區16具有相同電壓，所以電流擁擠(current crowding)效應不會發生在摻雜井區16之角落。When positive electrostatic discharge energy is applied to the first pin 22 and the second pin 24 is grounded, the electrostatic discharge current flows from the first pin 22 through the heavily doped semiconductor substrate 12 , the first semiconductor epitaxial layer 14 , and the doped well The region 16 and the first heavily doped region 26 flow to the second pin 24 . The collapse interface is located between the heavily doped semiconductor substrate 12 and the first semiconductor epitaxial layer 14 . Due to the existence of the outer conductor 20, the first heavily doped region 26, the second heavily doped region 28, the first semiconductor epitaxial layer 14 and the doped well region 16 have the same voltage, so the current crowding effect does not occur Occurs at the corners of the doped well region 16 .

第4圖為本發明之垂直式雙極性電晶體裝置之第三實施例之結構剖視圖。請參閱第4圖，並介紹本發明之垂直式雙極性電晶體裝置之第三實施例如下。與第二實施例相比，第三實施例更包含一重摻雜埋層30，其係設於重摻雜半導體基板12與第一半導體磊晶層14之間，並位於摻雜井區16之正下方。重摻雜埋層30可與隔離結構18分開。重摻雜埋層30與摻雜井區16具有相同的水平位置。重摻雜埋層30具有第一導電型或第二導電型。FIG. 4 is a cross-sectional view of the structure of the third embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 4, and introduce a third embodiment of the vertical bipolar transistor device of the present invention as follows. Compared with the second embodiment, the third embodiment further includes a heavily doped buried layer 30 disposed between the heavily doped semiconductor substrate 12 and the first semiconductor epitaxial layer 14 and located between the doped well regions 16 . Directly below. The heavily doped buried layer 30 may be separated from the isolation structure 18 . The heavily doped buried layer 30 has the same horizontal position as the doped well region 16 . The heavily doped buried layer 30 has the first conductivity type or the second conductivity type.

當重摻雜埋層30具有第一導電型時，崩潰介面位於重摻雜埋層30與第一半導體磊晶層14之間。雖然重摻雜埋層30與重摻雜半導體基板12屬於相同導電型，但重摻雜埋層30之離子之游離能經常大於重摻雜半導體基板12之離子之游離能，這是因為重摻雜埋層30與重摻雜半導體基板12使用不同材料摻雜。舉例來說，重摻雜埋層30使用磷原子摻雜，重摻雜半導體基板12使用砷原子摻雜。因此，介於重摻雜埋層30與第一半導體磊晶層14之間的介面之崩潰電壓經常低於介於第一半導體磊晶層14與重摻雜半導體基板12之間的介面之崩潰電壓。在這樣的情況下，隔離結構18之底部深於介於重摻雜埋層30與第一半導體磊晶層14之間的介面，使隔離結構18保護重摻雜埋層30與第一半導體磊晶層14之間的崩潰介面。當重摻雜埋層30具有第二導電型時，崩潰介面位於重摻雜埋層30與重摻雜半導體基板12之間。垂直式雙極性電晶體裝置10根據第一半導體磊晶層14與重摻雜埋層30之電阻率，可具有一較大範圍之崩潰電壓。在這樣的情況下，隔離結構18之底部深於介於重摻雜埋層30與重摻雜半導體基板12之間的介面，使隔離結構18保護重摻雜埋層30與重摻雜半導體基板12之間的崩潰介面。When the heavily doped buried layer 30 has the first conductivity type, the breakdown interface is located between the heavily doped buried layer 30 and the first semiconductor epitaxial layer 14 . Although the heavily doped buried layer 30 and the heavily doped semiconductor substrate 12 are of the same conductivity type, the dissociation energy of the ions of the heavily doped buried layer 30 is often greater than that of the ions of the heavily doped semiconductor substrate 12. The impurity buried layer 30 and the heavily doped semiconductor substrate 12 are doped with different materials. For example, the heavily doped buried layer 30 is doped with phosphorus atoms, and the heavily doped semiconductor substrate 12 is doped with arsenic atoms. Therefore, the breakdown voltage of the interface between the heavily doped buried layer 30 and the first semiconductor epitaxial layer 14 is often lower than the breakdown voltage of the interface between the first semiconductor epitaxial layer 14 and the heavily doped semiconductor substrate 12 Voltage. In this case, the bottom of the isolation structure 18 is deeper than the interface between the heavily doped buried layer 30 and the first semiconductor epitaxial layer 14, so that the isolation structure 18 protects the heavily doped buried layer 30 and the first semiconductor epitaxial layer 14 The collapse interface between the crystalline layers 14 . When the heavily doped buried layer 30 has the second conductivity type, the breakdown interface is located between the heavily doped buried layer 30 and the heavily doped semiconductor substrate 12 . The vertical bipolar transistor device 10 can have a wide range of breakdown voltages according to the resistivity of the first semiconductor epitaxial layer 14 and the heavily doped buried layer 30 . In this case, the bottom of the isolation structure 18 is deeper than the interface between the heavily doped buried layer 30 and the heavily doped semiconductor substrate 12, so that the isolation structure 18 protects the heavily doped buried layer 30 and the heavily doped semiconductor substrate Crash interface between 12.

當正靜電放電能量施加在第一接腳22，且第二接腳24接地時，靜電放電電流從第一接腳22經過重摻雜半導體基板12、重摻雜埋層30、第一半導體磊晶層14、摻雜井區16與第一重摻雜區26流至第二接腳24。崩潰介面位於重摻雜半導體基板12與重摻雜埋層30之間或位於重摻雜埋層30與第一半導體磊晶層14之間。此外，電流擁擠效應不會發生在摻雜井區16之角落，這是因為由於外部導體20之存在，第一重摻雜區26、第二重摻雜區28、第一半導體磊晶層14與摻雜井區16具有相同電壓。大部分的靜電放電電流僅通過重摻雜埋層30，而不是第一半導體磊晶層14之周圍。因此，靜電放電電流不會通過摻雜井區16之角落。垂直式雙極性電晶體裝置10根據第一半導體磊晶層14與重摻雜埋層30之電阻率，可具有一較大範圍之崩潰電壓。When positive electrostatic discharge energy is applied to the first pin 22 and the second pin 24 is grounded, the electrostatic discharge current flows from the first pin 22 through the heavily doped semiconductor substrate 12 , the heavily doped buried layer 30 , and the first semiconductor epitaxy The crystal layer 14 , the doped well region 16 and the first heavily doped region 26 flow to the second pin 24 . The breakdown interface is located between the heavily doped semiconductor substrate 12 and the heavily doped buried layer 30 or between the heavily doped buried layer 30 and the first semiconductor epitaxial layer 14 . In addition, the current crowding effect does not occur at the corners of the doped well region 16 because due to the presence of the outer conductor 20 , the first heavily doped region 26 , the second heavily doped region 28 , and the first semiconductor epitaxial layer 14 Has the same voltage as the doped well region 16 . Most of the ESD current only passes through the heavily doped buried layer 30 and not around the first semiconductor epitaxial layer 14 . Therefore, ESD current does not pass through the corners of the doped well region 16 . The vertical bipolar transistor device 10 can have a wide range of breakdown voltages according to the resistivity of the first semiconductor epitaxial layer 14 and the heavily doped buried layer 30 .

第5圖為本發明之垂直式雙極性電晶體裝置之第四實施例之結構剖視圖。請參閱第5圖，並介紹本發明之垂直式雙極性電晶體裝置之第四實施例如下。與第三實施例相比，第四實施例之重摻雜埋層30更可完全覆蓋重摻雜半導體基板12，並接觸隔離結構18。重摻雜埋層30係以毯式植入(blanket implantation)方式形成，進而省下一道光罩製程，並減少製作成本。FIG. 5 is a cross-sectional view of the structure of the fourth embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 5, and introduce a fourth embodiment of the vertical bipolar transistor device of the present invention as follows. Compared with the third embodiment, the heavily doped buried layer 30 of the fourth embodiment can completely cover the heavily doped semiconductor substrate 12 and contact the isolation structure 18 . The heavily doped buried layer 30 is formed by blanket implantation, which saves a mask process and reduces manufacturing cost.

第6圖為本發明之垂直式雙極性電晶體裝置之第五實施例之結構剖視圖。請參閱第6圖，並介紹本發明之垂直式雙極性電晶體裝置之第五實施例如下。與第四實施例相比，第五實施例係以複數個第一重摻雜區26、複數個第二重摻雜區28與複數個摻雜井區16為例。所有第一重摻雜區26分別設於所有摻雜井區16中。所有摻雜井區16與所有第二重摻雜區28交替式設置。FIG. 6 is a structural cross-sectional view of a fifth embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 6 and introduce a fifth embodiment of the vertical bipolar transistor device of the present invention as follows. Compared with the fourth embodiment, the fifth embodiment takes a plurality of first heavily doped regions 26 , a plurality of second heavily doped regions 28 and a plurality of doped well regions 16 as an example. All the first heavily doped regions 26 are respectively provided in all the doped well regions 16 . All doped well regions 16 are alternately arranged with all second heavily doped regions 28 .

當正靜電放電能量施加在第一接腳22，且第二接腳24接地時，靜電放電電流從第一接腳22經過重摻雜半導體基板12、重摻雜埋層30、第一半導體磊晶層14、摻雜井區16與第一重摻雜區26流至第二接腳24。崩潰介面位於重摻雜半導體基板12與重摻雜埋層30之間或位於重摻雜埋層30與第一半導體磊晶層14之間。此外，電流擁擠效應不會發生在摻雜井區16之角落，這是因為由於外部導體20之存在，第一重摻雜區26、第二重摻雜區28、第一半導體磊晶層14與摻雜井區16具有相同電壓。在第五實施例中，有複數個雙極性接面電晶體，其中雙極性接面電晶體的數量取決於摻雜井區16之數量。由隔離結構18所圍繞之所有雙極性接面電晶體能增強靜電放電電流之均勻度與靜電放電等級。When positive electrostatic discharge energy is applied to the first pin 22 and the second pin 24 is grounded, the electrostatic discharge current flows from the first pin 22 through the heavily doped semiconductor substrate 12 , the heavily doped buried layer 30 , and the first semiconductor epitaxy The crystal layer 14 , the doped well region 16 and the first heavily doped region 26 flow to the second pin 24 . The breakdown interface is located between the heavily doped semiconductor substrate 12 and the heavily doped buried layer 30 or between the heavily doped buried layer 30 and the first semiconductor epitaxial layer 14 . In addition, the current crowding effect does not occur at the corners of the doped well region 16 because due to the presence of the outer conductor 20 , the first heavily doped region 26 , the second heavily doped region 28 , and the first semiconductor epitaxial layer 14 Has the same voltage as the doped well region 16 . In the fifth embodiment, there are a plurality of bipolar junction transistors, wherein the number of bipolar junction transistors depends on the number of doped well regions 16 . All bipolar junction transistors surrounded by isolation structures 18 can enhance ESD current uniformity and ESD levels.

第7圖為本發明之垂直式雙極性電晶體裝置之第六實施例之結構剖視圖。請參閱第7圖，並介紹本發明之垂直式雙極性電晶體裝置之第六實施例如下。第六實施例與第二實施例差別在於，第六實施例更可包含一第二半導體磊晶層32，其係設於重摻雜半導體基板12與第一半導體磊晶層14之間，並位於摻雜井區16之正下方。第二半導體磊晶層32可完全覆蓋重摻雜半導體基板12。第二半導體磊晶層32具有第一導電型或第二導電型。FIG. 7 is a structural cross-sectional view of a sixth embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 7, and introduce a sixth embodiment of the vertical bipolar transistor device of the present invention as follows. The difference between the sixth embodiment and the second embodiment is that the sixth embodiment may further include a second semiconductor epitaxial layer 32 disposed between the heavily doped semiconductor substrate 12 and the first semiconductor epitaxial layer 14 , and Located directly below the doped well region 16 . The second semiconductor epitaxial layer 32 can completely cover the heavily doped semiconductor substrate 12 . The second semiconductor epitaxial layer 32 has the first conductivity type or the second conductivity type.

當第二半導體磊晶層32具有第一導電型時，崩潰介面位於第二半導體磊晶層32與第一半導體磊晶層14之間。雖然第二半導體磊晶層32與重摻雜半導體基板12屬於相同導電型，但第二半導體磊晶層32之離子之游離能經常大於重摻雜半導體基板12之離子之游離能，這是因為第二半導體磊晶層32與重摻雜半導體基板12使用不同材料摻雜。舉例來說，第二半導體磊晶層32使用磷原子摻雜，重摻雜半導體基板12使用砷原子摻雜。因此，介於第二半導體磊晶層32與第一半導體磊晶層14之間的介面之崩潰電壓經常低於介於第一半導體磊晶層14與重摻雜半導體基板12之間的介面之崩潰電壓。在這樣的情況下，隔離結構18之底部深於介於第二半導體磊晶層32與第一半導體磊晶層14之間的介面，使隔離結構18保護第二半導體磊晶層32與第一半導體磊晶層14之間的崩潰介面。當第二半導體磊晶層32具有第二導電型時，崩潰介面位於第二半導體磊晶層32與重摻雜半導體基板12之間。垂直式雙極性電晶體裝置10根據第一半導體磊晶層14與第二半導體磊晶層32之電阻率，可具有一較大範圍之崩潰電壓。在這樣的情況下，隔離結構18之底部深於介於第二半導體磊晶層32與重摻雜半導體基板12之間的介面，使隔離結構18保護第二半導體磊晶層32與重摻雜半導體基板12之間的崩潰介面。When the second semiconductor epitaxial layer 32 has the first conductivity type, the collapse interface is located between the second semiconductor epitaxial layer 32 and the first semiconductor epitaxial layer 14 . Although the second semiconductor epitaxial layer 32 and the heavily doped semiconductor substrate 12 are of the same conductivity type, the dissociation energy of the ions of the second semiconductor epitaxial layer 32 is often greater than that of the ions of the heavily doped semiconductor substrate 12 , because The second semiconductor epitaxial layer 32 and the heavily doped semiconductor substrate 12 are doped with different materials. For example, the second semiconductor epitaxial layer 32 is doped with phosphorus atoms, and the heavily doped semiconductor substrate 12 is doped with arsenic atoms. Therefore, the breakdown voltage of the interface between the second semiconductor epitaxial layer 32 and the first semiconductor epitaxial layer 14 is often lower than that of the interface between the first semiconductor epitaxial layer 14 and the heavily doped semiconductor substrate 12 breakdown voltage. In this case, the bottom of the isolation structure 18 is deeper than the interface between the second semiconductor epitaxial layer 32 and the first semiconductor epitaxial layer 14, so that the isolation structure 18 protects the second semiconductor epitaxial layer 32 and the first semiconductor epitaxial layer 14. The breakdown interface between the semiconductor epitaxial layers 14 . When the second semiconductor epitaxial layer 32 has the second conductivity type, the collapse interface is located between the second semiconductor epitaxial layer 32 and the heavily doped semiconductor substrate 12 . The vertical bipolar transistor device 10 can have a wide range of breakdown voltages according to the resistivity of the first semiconductor epitaxial layer 14 and the second semiconductor epitaxial layer 32 . In this case, the bottom of the isolation structure 18 is deeper than the interface between the second semiconductor epitaxial layer 32 and the heavily doped semiconductor substrate 12 , so that the isolation structure 18 protects the second semiconductor epitaxial layer 32 and the heavily doped semiconductor substrate 12 . Crash interface between semiconductor substrates 12 .

當正靜電放電能量施加在第一接腳22，且第二接腳24接地時，靜電放電電流從第一接腳22經過重摻雜半導體基板12、第二半導體磊晶層32、第一半導體磊晶層14、摻雜井區16與第一重摻雜區26流至第二接腳24。崩潰介面位於重摻雜半導體基板12與第二半導體磊晶層32之間或位於第二半導體磊晶層32與第一半導體磊晶層14之間。此外，電流擁擠效應不會發生在摻雜井區16之角落，這是因為由於外部導體20之存在，第一重摻雜區26、第二重摻雜區28、第一半導體磊晶層14與摻雜井區16具有相同電壓。因此，靜電放電電流不會通過摻雜井區16之角落。垂直式雙極性電晶體裝置10根據第一半導體磊晶層14與第二半導體磊晶層32之電阻率，可具有一較大範圍之崩潰電壓。When positive electrostatic discharge energy is applied to the first pin 22 and the second pin 24 is grounded, the electrostatic discharge current flows from the first pin 22 through the heavily doped semiconductor substrate 12 , the second semiconductor epitaxial layer 32 , the first semiconductor The epitaxial layer 14 , the doped well region 16 and the first heavily doped region 26 flow to the second pin 24 . The collapse interface is located between the heavily doped semiconductor substrate 12 and the second semiconductor epitaxial layer 32 or between the second semiconductor epitaxial layer 32 and the first semiconductor epitaxial layer 14 . In addition, the current crowding effect does not occur at the corners of the doped well region 16 because due to the presence of the outer conductor 20 , the first heavily doped region 26 , the second heavily doped region 28 , and the first semiconductor epitaxial layer 14 Has the same voltage as the doped well region 16 . Therefore, ESD current does not pass through the corners of the doped well region 16 . The vertical bipolar transistor device 10 can have a wide range of breakdown voltages according to the resistivity of the first semiconductor epitaxial layer 14 and the second semiconductor epitaxial layer 32 .

第8圖為本發明之垂直式雙極性電晶體裝置之第七實施例之結構剖視圖。請參閱第8圖，並介紹本發明之垂直式雙極性電晶體裝置之第七實施例如下。與第六實施例相比，第七實施例以複數個第一重摻雜區26、複數個第二重摻雜區28與複數個摻雜井區16為例。所有第一重摻雜區26分別設於所有摻雜井區16中。所有摻雜井區16與所有第二重摻雜區28交替式設置。FIG. 8 is a structural cross-sectional view of a seventh embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 8, and introduce a seventh embodiment of the vertical bipolar transistor device of the present invention as follows. Compared with the sixth embodiment, the seventh embodiment takes a plurality of first heavily doped regions 26 , a plurality of second heavily doped regions 28 and a plurality of doped well regions 16 as an example. All the first heavily doped regions 26 are respectively provided in all the doped well regions 16 . All doped well regions 16 are alternately arranged with all second heavily doped regions 28 .

當正靜電放電能量施加在第一接腳22，且第二接腳24接地時，靜電放電電流從第一接腳22經過重摻雜半導體基板12、第二半導體磊晶層32、第一半導體磊晶層14、摻雜井區16與第一重摻雜區26流至第二接腳24。崩潰介面位於重摻雜半導體基板12與第二半導體磊晶層32之間或位於第二半導體磊晶層32與第一半導體磊晶層14之間。此外，電流擁擠效應不會發生在摻雜井區16之角落，這是因為由於外部導體20之存在，第一重摻雜區26、第二重摻雜區28、第一半導體磊晶層14與摻雜井區16具有相同電壓。在第七實施例中，有複數個雙極性接面電晶體，其中雙極性接面電晶體的數量取決於摻雜井區16之數量。由隔離結構18所圍繞之所有雙極性接面電晶體能增強靜電放電電流之均勻度與靜電放電等級。When positive electrostatic discharge energy is applied to the first pin 22 and the second pin 24 is grounded, the electrostatic discharge current flows from the first pin 22 through the heavily doped semiconductor substrate 12 , the second semiconductor epitaxial layer 32 , the first semiconductor The epitaxial layer 14 , the doped well region 16 and the first heavily doped region 26 flow to the second pin 24 . The collapse interface is located between the heavily doped semiconductor substrate 12 and the second semiconductor epitaxial layer 32 or between the second semiconductor epitaxial layer 32 and the first semiconductor epitaxial layer 14 . In addition, the current crowding effect does not occur at the corners of the doped well region 16 because due to the presence of the outer conductor 20 , the first heavily doped region 26 , the second heavily doped region 28 , and the first semiconductor epitaxial layer 14 Has the same voltage as the doped well region 16 . In the seventh embodiment, there are a plurality of bipolar junction transistors, wherein the number of bipolar junction transistors depends on the number of doped well regions 16 . All bipolar junction transistors surrounded by isolation structures 18 can enhance ESD current uniformity and ESD levels.

第9圖為本發明之垂直式雙極性電晶體裝置之第八實施例之結構剖視圖。請參閱第9圖，並介紹本發明之垂直式雙極性電晶體裝置之第八實施例如下。第八實施例與第一實施例差別在於導電型。第八實施例之第一導電型與第二導電型分別為P型與N型，其餘結構已於第一實施例描述，於此不再贅述。FIG. 9 is a cross-sectional view of the structure of an eighth embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 9, and an eighth embodiment of the vertical bipolar transistor device of the present invention is introduced as follows. The difference between the eighth embodiment and the first embodiment lies in the conductivity type. The first conductivity type and the second conductivity type in the eighth embodiment are P-type and N-type, respectively. The rest of the structures have been described in the first embodiment, and will not be repeated here.

當正靜電放電能量施加在第二接腳24，且第一接腳22接地時，靜電放電電流從第二接腳24經過摻雜井區16、第一半導體磊晶層14與重摻雜半導體基板12流至第一接腳22。崩潰介面位於第一半導體磊晶層14與重摻雜半導體基板12之間。由於外部導體20之存在，第一半導體磊晶層14與摻雜井區16具有相同電壓，所以電流擁擠(current crowding)效應不會發生在摻雜井區16之角落。When positive electrostatic discharge energy is applied to the second pin 24 and the first pin 22 is grounded, the electrostatic discharge current flows from the second pin 24 through the doped well region 16 , the first semiconductor epitaxial layer 14 and the heavily doped semiconductor The substrate 12 flows to the first pins 22 . The collapse interface is located between the first semiconductor epitaxial layer 14 and the heavily doped semiconductor substrate 12 . Due to the existence of the outer conductor 20 , the first semiconductor epitaxial layer 14 and the doped well region 16 have the same voltage, so the current crowding effect does not occur at the corners of the doped well region 16 .

第10圖為本發明之垂直式雙極性電晶體裝置之第九實施例之結構剖視圖。請參閱第10圖，並介紹本發明之垂直式雙極性電晶體裝置之第九實施例如下。第九實施例與第二實施例差別在於導電型。第九實施例之第一導電型與第二導電型分別為P型與N型，其餘結構已於第二實施例描述，於此不再贅述。FIG. 10 is a cross-sectional view of the structure of the ninth embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 10, and introduce a ninth embodiment of the vertical bipolar transistor device of the present invention as follows. The difference between the ninth embodiment and the second embodiment lies in the conductivity type. The first conductivity type and the second conductivity type of the ninth embodiment are P-type and N-type, respectively. The rest of the structures have been described in the second embodiment, and will not be repeated here.

當正靜電放電能量施加在第二接腳24，且第一接腳22接地時，靜電放電電流從第二接腳24經過第一重摻雜區26、摻雜井區16、第一半導體磊晶層14與重摻雜半導體基板12流至第一接腳22。崩潰介面位於重摻雜半導體基板12與第一半導體磊晶層14之間。由於外部導體20之存在，第一重摻雜區26、第二重摻雜區28、第一半導體磊晶層14與摻雜井區16具有相同電壓，所以電流擁擠(current crowding)效應不會發生在摻雜井區16之角落。When positive electrostatic discharge energy is applied to the second pin 24 and the first pin 22 is grounded, the electrostatic discharge current from the second pin 24 passes through the first heavily doped region 26 , the doped well region 16 , and the first semiconductor epitaxy The crystal layer 14 and the heavily doped semiconductor substrate 12 flow to the first pins 22 . The collapse interface is located between the heavily doped semiconductor substrate 12 and the first semiconductor epitaxial layer 14 . Due to the existence of the outer conductor 20, the first heavily doped region 26, the second heavily doped region 28, the first semiconductor epitaxial layer 14 and the doped well region 16 have the same voltage, so the current crowding effect does not occur Occurs at the corners of the doped well region 16 .

第11圖為本發明之垂直式雙極性電晶體裝置之第十實施例之結構剖視圖。請參閱第11圖，並介紹本發明之垂直式雙極性電晶體裝置之第十實施例如下。第十實施例與第三實施例差別在於導電型。第十實施例之第一導電型與第二導電型分別為P型與N型，其餘結構已於第三實施例描述，於此不再贅述。FIG. 11 is a cross-sectional view of the structure of the tenth embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 11, and introduce a tenth embodiment of the vertical bipolar transistor device of the present invention as follows. The difference between the tenth embodiment and the third embodiment lies in the conductivity type. The first conductivity type and the second conductivity type of the tenth embodiment are P-type and N-type respectively, and the rest of the structures have been described in the third embodiment and will not be repeated here.

當正靜電放電能量施加在第二接腳24，且第一接腳22接地時，靜電放電電流從第二接腳24經過第一重摻雜區26、摻雜井區16、第一半導體磊晶層14、重摻雜埋層30與重摻雜半導體基板12流至第一接腳22。崩潰介面位於重摻雜半導體基板12與重摻雜埋層30之間或位於重摻雜埋層30與第一半導體磊晶層14之間。此外，電流擁擠效應不會發生在摻雜井區16之角落，這是因為由於外部導體20之存在，第一重摻雜區26、第二重摻雜區28、第一半導體磊晶層14與摻雜井區16具有相同電壓。大部分的靜電放電電流僅通過重摻雜埋層30，而不是第一半導體磊晶層14之周圍。因此，靜電放電電流不會通過摻雜井區16之角落。垂直式雙極性電晶體裝置10根據第一半導體磊晶層14與重摻雜埋層30之電阻率，可具有一較大範圍之崩潰電壓。When positive electrostatic discharge energy is applied to the second pin 24 and the first pin 22 is grounded, the electrostatic discharge current from the second pin 24 passes through the first heavily doped region 26 , the doped well region 16 , and the first semiconductor epitaxy The crystal layer 14 , the heavily doped buried layer 30 and the heavily doped semiconductor substrate 12 flow to the first pin 22 . The breakdown interface is located between the heavily doped semiconductor substrate 12 and the heavily doped buried layer 30 or between the heavily doped buried layer 30 and the first semiconductor epitaxial layer 14 . In addition, the current crowding effect does not occur at the corners of the doped well region 16 because due to the presence of the outer conductor 20 , the first heavily doped region 26 , the second heavily doped region 28 , and the first semiconductor epitaxial layer 14 Has the same voltage as the doped well region 16 . Most of the ESD current only passes through the heavily doped buried layer 30 and not around the first semiconductor epitaxial layer 14 . Therefore, ESD current does not pass through the corners of the doped well region 16 . The vertical bipolar transistor device 10 can have a wide range of breakdown voltages according to the resistivity of the first semiconductor epitaxial layer 14 and the heavily doped buried layer 30 .

第12圖為本發明之垂直式雙極性電晶體裝置之第十一實施例之結構剖視圖。請參閱第12圖，並介紹本發明之垂直式雙極性電晶體裝置之第十一實施例如下。第十一實施例與第四實施例差別在於導電型。第十一實施例之第一導電型與第二導電型分別為P型與N型，其餘結構已於第四實施例描述，於此不再贅述。FIG. 12 is a cross-sectional view of the structure of the eleventh embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 12, and an eleventh embodiment of the vertical bipolar transistor device of the present invention is introduced as follows. The difference between the eleventh embodiment and the fourth embodiment lies in the conductivity type. The first conductivity type and the second conductivity type of the eleventh embodiment are P-type and N-type, respectively. The rest of the structures have been described in the fourth embodiment, and will not be repeated here.

第13圖為本發明之垂直式雙極性電晶體裝置之第十二實施例之結構剖視圖。請參閱第13圖，並介紹本發明之垂直式雙極性電晶體裝置之第十二實施例如下。第十二實施例與第五實施例差別在於導電型。第十二實施例之第一導電型與第二導電型分別為P型與N型，其餘結構已於第五實施例描述，於此不再贅述。FIG. 13 is a cross-sectional view of the structure of the twelfth embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 13, and introduce a twelfth embodiment of the vertical bipolar transistor device of the present invention as follows. The difference between the twelfth embodiment and the fifth embodiment lies in the conductivity type. The first conductivity type and the second conductivity type of the twelfth embodiment are P-type and N-type, respectively. The rest of the structures have been described in the fifth embodiment and will not be repeated here.

當正靜電放電能量施加在第二接腳24，且第一接腳22接地時，靜電放電電流從第二接腳24經過第一重摻雜區26、摻雜井區16、第一半導體磊晶層14、重摻雜埋層30與重摻雜半導體基板12流至第一接腳22。崩潰介面位於重摻雜半導體基板12與重摻雜埋層30之間或位於重摻雜埋層30與第一半導體磊晶層14之間。此外，電流擁擠效應不會發生在摻雜井區16之角落，這是因為由於外部導體20之存在，第一重摻雜區26、第二重摻雜區28、第一半導體磊晶層14與摻雜井區16具有相同電壓。在第十二實施例中，有複數個雙極性接面電晶體，其中雙極性接面電晶體的數量取決於摻雜井區16之數量。由隔離結構18所圍繞之所有雙極性接面電晶體能增強靜電放電電流之均勻度與靜電放電等級。When positive electrostatic discharge energy is applied to the second pin 24 and the first pin 22 is grounded, the electrostatic discharge current from the second pin 24 passes through the first heavily doped region 26 , the doped well region 16 , and the first semiconductor epitaxy The crystal layer 14 , the heavily doped buried layer 30 and the heavily doped semiconductor substrate 12 flow to the first pin 22 . The breakdown interface is located between the heavily doped semiconductor substrate 12 and the heavily doped buried layer 30 or between the heavily doped buried layer 30 and the first semiconductor epitaxial layer 14 . In addition, the current crowding effect does not occur at the corners of the doped well region 16 because due to the presence of the outer conductor 20 , the first heavily doped region 26 , the second heavily doped region 28 , and the first semiconductor epitaxial layer 14 Has the same voltage as the doped well region 16 . In the twelfth embodiment, there are a plurality of bipolar junction transistors, wherein the number of bipolar junction transistors depends on the number of doped well regions 16 . All bipolar junction transistors surrounded by isolation structures 18 can enhance ESD current uniformity and ESD levels.

第14圖為本發明之垂直式雙極性電晶體裝置之第十三實施例之結構剖視圖。請參閱第14圖，並介紹本發明之垂直式雙極性電晶體裝置之第十三實施例如下。第十三實施例與第六實施例差別在於導電型。第十三實施例之第一導電型與第二導電型分別為P型與N型，其餘結構已於第六實施例描述，於此不再贅述。FIG. 14 is a cross-sectional view of the structure of the thirteenth embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 14, and introduce a thirteenth embodiment of the vertical bipolar transistor device of the present invention as follows. The difference between the thirteenth embodiment and the sixth embodiment lies in the conductivity type. The first conductivity type and the second conductivity type of the thirteenth embodiment are P-type and N-type, respectively. The rest of the structures have been described in the sixth embodiment, and will not be repeated here.

當正靜電放電能量施加在第二接腳24，且第一接腳22接地時，靜電放電電流從第二接腳24經過第一重摻雜區26、摻雜井區16、第一半導體磊晶層14、第二半導體磊晶層32與重摻雜半導體基板12流至第一接腳22。崩潰介面位於重摻雜半導體基板12與第二半導體磊晶層32之間或位於第二半導體磊晶層32與第一半導體磊晶層14之間。此外，電流擁擠效應不會發生在摻雜井區16之角落，這是因為由於外部導體20之存在，第一重摻雜區26、第二重摻雜區28、第一半導體磊晶層14與摻雜井區16具有相同電壓。因此，靜電放電電流不會通過摻雜井區16之角落。垂直式雙極性電晶體裝置10根據第一半導體磊晶層14與第二半導體磊晶層32之電阻率，可具有一較大範圍之崩潰電壓。When positive electrostatic discharge energy is applied to the second pin 24 and the first pin 22 is grounded, the electrostatic discharge current from the second pin 24 passes through the first heavily doped region 26 , the doped well region 16 , and the first semiconductor epitaxy The crystal layer 14 , the second semiconductor epitaxial layer 32 and the heavily doped semiconductor substrate 12 flow to the first pins 22 . The collapse interface is located between the heavily doped semiconductor substrate 12 and the second semiconductor epitaxial layer 32 or between the second semiconductor epitaxial layer 32 and the first semiconductor epitaxial layer 14 . In addition, the current crowding effect does not occur at the corners of the doped well region 16 because due to the presence of the outer conductor 20 , the first heavily doped region 26 , the second heavily doped region 28 , and the first semiconductor epitaxial layer 14 Has the same voltage as the doped well region 16 . Therefore, ESD current does not pass through the corners of the doped well region 16 . The vertical bipolar transistor device 10 can have a wide range of breakdown voltages according to the resistivity of the first semiconductor epitaxial layer 14 and the second semiconductor epitaxial layer 32 .

第15圖為本發明之垂直式雙極性電晶體裝置之第十四實施例之結構剖視圖。請參閱第15圖，並介紹本發明之垂直式雙極性電晶體裝置之第十四實施例如下。第十四實施例與第七實施例差別在於導電型。第十四實施例之第一導電型與第二導電型分別為P型與N型，第十四實施例之其餘結構已於第七實施例描述過，於此不再贅述。FIG. 15 is a cross-sectional view of the structure of the fourteenth embodiment of the vertical bipolar transistor device of the present invention. Please refer to FIG. 15, and introduce a fourteenth embodiment of the vertical bipolar transistor device of the present invention as follows. The difference between the fourteenth embodiment and the seventh embodiment lies in the conductivity type. The first conductivity type and the second conductivity type of the fourteenth embodiment are P-type and N-type, respectively. The remaining structures of the fourteenth embodiment have been described in the seventh embodiment, and will not be repeated here.

當正靜電放電能量施加在第二接腳24，且第一接腳22接地時，靜電放電電流從第二接腳24經過第一重摻雜區26、摻雜井區16、第一半導體磊晶層14、第二半導體磊晶層32與重摻雜半導體基板12流至第一接腳22。崩潰介面位於重摻雜半導體基板12與第二半導體磊晶層32之間或位於第二半導體磊晶層32與第一半導體磊晶層14之間。此外，電流擁擠效應不會發生在摻雜井區16之角落，這是因為由於外部導體20之存在，第一重摻雜區26、第二重摻雜區28、第一半導體磊晶層14與摻雜井區16具有相同電壓。在第十四實施例中，有複數個雙極性接面電晶體，其中雙極性接面電晶體的數量取決於摻雜井區16之數量。由隔離結構18所圍繞之所有雙極性接面電晶體能增強靜電放電電流之均勻度與靜電放電等級。When positive electrostatic discharge energy is applied to the second pin 24 and the first pin 22 is grounded, the electrostatic discharge current from the second pin 24 passes through the first heavily doped region 26 , the doped well region 16 , and the first semiconductor epitaxy The crystal layer 14 , the second semiconductor epitaxial layer 32 and the heavily doped semiconductor substrate 12 flow to the first pins 22 . The collapse interface is located between the heavily doped semiconductor substrate 12 and the second semiconductor epitaxial layer 32 or between the second semiconductor epitaxial layer 32 and the first semiconductor epitaxial layer 14 . In addition, the current crowding effect does not occur at the corners of the doped well region 16 because due to the presence of the outer conductor 20 , the first heavily doped region 26 , the second heavily doped region 28 , and the first semiconductor epitaxial layer 14 Has the same voltage as the doped well region 16 . In the fourteenth embodiment, there are a plurality of bipolar junction transistors, wherein the number of bipolar junction transistors depends on the number of doped well regions 16 . All bipolar junction transistors surrounded by isolation structures 18 can enhance ESD current uniformity and ESD levels.

根據上述實施例，垂直式雙極性電晶體裝置根據第一半導體磊晶層之電阻率與厚度，自由地調整雙載子接面電晶體之增益與崩潰電壓。垂直式雙極性電晶體裝置可根據第一半導體磊晶層與重摻雜埋層之電阻率，具有大範圍之崩潰電壓。According to the above embodiment, the vertical bipolar transistor device can freely adjust the gain and breakdown voltage of the bipolar junction transistor according to the resistivity and thickness of the first semiconductor epitaxial layer. The vertical bipolar transistor device can have a wide range of breakdown voltages according to the resistivity of the first semiconductor epitaxial layer and the heavily doped buried layer.

以上所述者，僅為本發明一較佳實施例而已，並非用來限定本發明實施之範圍，故舉凡依本發明申請專利範圍所述之形狀、構造、特徵及精神所為之均等變化與修飾，均應包括於本發明之申請專利範圍內。The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Therefore, all changes and modifications made in accordance with the shape, structure, feature and spirit described in the scope of the patent application of the present invention are equivalent. , shall be included in the scope of the patent application of the present invention.

8:靜電放電保護裝置 9:欲保護裝置 10:垂直式雙極性電晶體裝置 12:重摻雜半導體基板 14:第一半導體磊晶層 16:摻雜井區 18:隔離結構 20:外部導體 22:第一接腳 24:第二接腳 26:第一重摻雜區 28:第二重摻雜區 30:重摻雜埋層 32:第二半導體磊晶層8: Electrostatic discharge protection device 9: To protect the device 10: Vertical Bipolar Transistor Device 12: heavily doped semiconductor substrate 14: The first semiconductor epitaxial layer 16: Doping well area 18: Isolation structure 20: Outer conductor 22: The first pin 24: The second pin 26: The first heavily doped region 28: Second heavily doped region 30: heavily doped buried layer 32: The second semiconductor epitaxial layer

第1圖為先前技術之與積體電路晶片中的欲保護裝置連接之靜電放電保護裝置的電路方塊圖。 第2圖為本發明之垂直式雙極性電晶體裝置之第一實施例之結構剖視圖。 第3圖為本發明之垂直式雙極性電晶體裝置之第二實施例之結構剖視圖。 第4圖為本發明之垂直式雙極性電晶體裝置之第三實施例之結構剖視圖。 第5圖為本發明之垂直式雙極性電晶體裝置之第四實施例之結構剖視圖。 第6圖為本發明之垂直式雙極性電晶體裝置之第五實施例之結構剖視圖。 第7圖為本發明之垂直式雙極性電晶體裝置之第六實施例之結構剖視圖。 第8圖為本發明之垂直式雙極性電晶體裝置之第七實施例之結構剖視圖。 第9圖為本發明之垂直式雙極性電晶體裝置之第八實施例之結構剖視圖。 第10圖為本發明之垂直式雙極性電晶體裝置之第九實施例之結構剖視圖。 第11圖為本發明之垂直式雙極性電晶體裝置之第十實施例之結構剖視圖。 第12圖為本發明之垂直式雙極性電晶體裝置之第十一實施例之結構剖視圖。 第13圖為本發明之垂直式雙極性電晶體裝置之第十二實施例之結構剖視圖。 第14圖為本發明之垂直式雙極性電晶體裝置之第十三實施例之結構剖視圖。 第15圖為本發明之垂直式雙極性電晶體裝置之第十四實施例之結構剖視圖。FIG. 1 is a circuit block diagram of a prior art ESD protection device connected to a device to be protected in an integrated circuit chip. FIG. 2 is a cross-sectional view of the structure of the first embodiment of the vertical bipolar transistor device of the present invention. FIG. 3 is a cross-sectional view of the structure of the second embodiment of the vertical bipolar transistor device of the present invention. FIG. 4 is a cross-sectional view of the structure of the third embodiment of the vertical bipolar transistor device of the present invention. FIG. 5 is a cross-sectional view of the structure of the fourth embodiment of the vertical bipolar transistor device of the present invention. FIG. 6 is a structural cross-sectional view of a fifth embodiment of the vertical bipolar transistor device of the present invention. FIG. 7 is a structural cross-sectional view of a sixth embodiment of the vertical bipolar transistor device of the present invention. FIG. 8 is a structural cross-sectional view of a seventh embodiment of the vertical bipolar transistor device of the present invention. FIG. 9 is a cross-sectional view of the structure of an eighth embodiment of the vertical bipolar transistor device of the present invention. FIG. 10 is a cross-sectional view of the structure of the ninth embodiment of the vertical bipolar transistor device of the present invention. FIG. 11 is a cross-sectional view of the structure of the tenth embodiment of the vertical bipolar transistor device of the present invention. FIG. 12 is a cross-sectional view of the structure of the eleventh embodiment of the vertical bipolar transistor device of the present invention. FIG. 13 is a cross-sectional view of the structure of the twelfth embodiment of the vertical bipolar transistor device of the present invention. FIG. 14 is a cross-sectional view of the structure of the thirteenth embodiment of the vertical bipolar transistor device of the present invention. FIG. 15 is a cross-sectional view of the structure of the fourteenth embodiment of the vertical bipolar transistor device of the present invention.

10:垂直式雙極性電晶體裝置10: Vertical Bipolar Transistor Device

12:重摻雜半導體基板12: heavily doped semiconductor substrate

14:第一半導體磊晶層14: The first semiconductor epitaxial layer

16:摻雜井區16: Doping well area

18:隔離結構18: Isolation structure

20:外部導體20: Outer conductor

22:第一接腳22: The first pin

24:第二接腳24: The second pin

Claims (14)

一種垂直式雙極性電晶體裝置，包含： 一重摻雜半導體基板，具有第一導電型； 一第一半導體磊晶層，具有第二導電型，該第一半導體磊晶層設於該重摻雜半導體基板上； 至少一摻雜井區，具有該第一導電型，該至少一摻雜井區設於該第一半導體磊晶層中； 一隔離結構，設於該重摻雜半導體基板與該第一半導體磊晶層中，並圍繞該第一半導體磊晶層與該至少一摻雜井區；以及 一外部導體，設於該至少一摻雜井區與該第一半導體磊晶層之外側，並電性連接該至少一摻雜井區與該第一半導體磊晶層。A vertical bipolar transistor device comprising: a heavily doped semiconductor substrate having a first conductivity type; a first semiconductor epitaxial layer with a second conductivity type, the first semiconductor epitaxial layer is disposed on the heavily doped semiconductor substrate; at least one doped well region with the first conductivity type, the at least one doped well region is disposed in the first semiconductor epitaxial layer; an isolation structure disposed in the heavily doped semiconductor substrate and the first semiconductor epitaxial layer and surrounding the first semiconductor epitaxial layer and the at least one doped well region; and An outer conductor is disposed on the outer side of the at least one doped well region and the first semiconductor epitaxial layer, and is electrically connected to the at least one doped well region and the first semiconductor epitaxial layer. 如請求項1所述之垂直式雙極性電晶體裝置，其中該第一導電型為N型，該第二導電型為P型。The vertical bipolar transistor device of claim 1, wherein the first conductivity type is N-type, and the second conductivity type is P-type. 如請求項1所述之垂直式雙極性電晶體裝置，其中該第一導電型為P型，該第二導電型為N型。The vertical bipolar transistor device of claim 1, wherein the first conductivity type is P-type, and the second conductivity type is N-type. 如請求項1所述之垂直式雙極性電晶體裝置，更包含： 至少一第一重摻雜區，具有該第一導電型，該至少一第一重摻雜區設於該至少一摻雜井區中；以及 至少一第二重摻雜區，具有該第二導電型，該至少一第二重摻雜區設於該第一半導體磊晶層中，其中該第一半導體磊晶層透過該至少一第一重摻雜區、該至少一第二重摻雜區與該外部導體電性連接該至少一摻雜井區。The vertical bipolar transistor device of claim 1, further comprising: at least one first heavily doped region having the first conductivity type, the at least one first heavily doped region being disposed in the at least one doped well region; and At least one second heavily doped region with the second conductivity type, the at least one second heavily doped region is disposed in the first semiconductor epitaxial layer, wherein the first semiconductor epitaxial layer penetrates through the at least one first semiconductor epitaxial layer The heavily doped region, the at least one second heavily doped region and the outer conductor are electrically connected to the at least one doped well region. 如請求項4所述之垂直式雙極性電晶體裝置，其中該至少一第二重摻雜區圍繞該至少一第一重摻雜區與該至少一摻雜井區。The vertical bipolar transistor device of claim 4, wherein the at least one second heavily doped region surrounds the at least one first heavily doped region and the at least one doped well region. 如請求項4所述之垂直式雙極性電晶體裝置，其中該至少一第一重摻雜區之數量為複數個，該至少一第二重摻雜區之數量為複數個，該至少一摻雜井區之數量為複數個，該些第一重摻雜區分別設於該些摻雜井區中，該些摻雜井區與該些第二重摻雜區交替設置。The vertical bipolar transistor device of claim 4, wherein the number of the at least one first heavily doped region is plural, the number of the at least one second heavily doped region is plural, and the at least one doping region is plural. The number of the mixed well regions is plural, the first heavily doped regions are respectively disposed in the doped well regions, and the doped well regions and the second heavily doped regions are alternately arranged. 如請求項4所述之垂直式雙極性電晶體裝置，更包含一重摻雜埋層，其係設於該重摻雜半導體基板與該第一半導體磊晶層之間，並位於該至少一摻雜井區之正下方。The vertical bipolar transistor device as claimed in claim 4, further comprising a heavily doped buried layer disposed between the heavily doped semiconductor substrate and the first semiconductor epitaxial layer and located on the at least one doped layer Right below the miscellaneous well area. 如請求項7所述之垂直式雙極性電晶體裝置，其中該重摻雜埋層具有該第一導電型，該隔離結構之底部深於介於該重摻雜埋層與該第一半導體磊晶層之間的介面。The vertical bipolar transistor device as claimed in claim 7, wherein the heavily doped buried layer has the first conductivity type, and the bottom of the isolation structure is deeper than between the heavily doped buried layer and the first semiconductor epitaxy interface between layers. 如請求項7所述之垂直式雙極性電晶體裝置，其中該重摻雜埋層具有該第二導電型，該隔離結構之底部深於介於該重摻雜埋層與該重摻雜半導體基板之間的介面。The vertical bipolar transistor device of claim 7, wherein the heavily doped buried layer has the second conductivity type, and the bottom of the isolation structure is deeper than the heavily doped buried layer and the heavily doped semiconductor interface between substrates. 如請求項7所述之垂直式雙極性電晶體裝置，其中該重摻雜埋層接觸該隔離結構。The vertical bipolar transistor device of claim 7, wherein the heavily doped buried layer contacts the isolation structure. 如請求項1所述之垂直式雙極性電晶體裝置，其中該重摻雜半導體基板電性連接一第一接腳，且該外部導體電性連接一第二接腳。The vertical bipolar transistor device of claim 1, wherein the heavily doped semiconductor substrate is electrically connected to a first pin, and the outer conductor is electrically connected to a second pin. 如請求項4所述之垂直式雙極性電晶體裝置，更包含一第二半導體磊晶層，其係設於該重摻雜半導體基板與該第一半導體磊晶層之間，並位於該至少一摻雜井區之正下方。The vertical bipolar transistor device as claimed in claim 4, further comprising a second semiconductor epitaxial layer disposed between the heavily doped semiconductor substrate and the first semiconductor epitaxial layer and located in the at least directly below a doped well region. 如請求項12所述之垂直式雙極性電晶體裝置，其中該第二半導體磊晶層具有該第一導電型，該隔離結構之底部深於介於該第二半導體磊晶層與該第一半導體磊晶層之間的介面。The vertical bipolar transistor device of claim 12, wherein the second semiconductor epitaxial layer has the first conductivity type, and the bottom of the isolation structure is deeper than between the second semiconductor epitaxial layer and the first semiconductor epitaxial layer The interface between semiconductor epitaxial layers. 如請求項12所述之垂直式雙極性電晶體裝置，其中該第二半導體磊晶層具有該第二導電型，該隔離結構之底部深於介於該第二半導體磊晶層與該重摻雜半導體基板之間的介面。The vertical bipolar transistor device of claim 12, wherein the second semiconductor epitaxial layer has the second conductivity type, and the bottom of the isolation structure is deeper than between the second semiconductor epitaxial layer and the heavily doped The interface between hetero semiconductor substrates.
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