CN116011383A

CN116011383A - Circuit schematic diagram route planning system for avoiding signal line coverage

Info

Publication number: CN116011383A
Application number: CN202310042406.5A
Authority: CN
Inventors: 肖承志
Original assignee: Shanghai Hejian Industrial Software Group Co Ltd
Current assignee: Shanghai Hejian Industrial Software Group Co Ltd
Priority date: 2023-01-28
Filing date: 2023-01-28
Publication date: 2023-04-25
Anticipated expiration: 2043-01-28
Also published as: CN116011383B

Abstract

The invention relates to a circuit schematic diagram route planning system for avoiding signal line coverage, which is used for realizing the steps T1 and generating a first constraint set; step T2, traversing the first constraint set, if H { L } exists at the same time _xi ,L _xj Sum H { L } _xj ,L _xi Then L _xi Is split into L _xi ¹ And L _xi ² The method comprises the steps of carrying out a first treatment on the surface of the Step T3, L _xi ¹ And L _xi ² Added to { L ] ₁ ，L ₂ ，…,L _k ,…L _K In { L }, generate ₁ ,L ₂ ,…,L _m ,…,L _M Setting { L } _xi ¹ ,L _xj }、{L _xj ,L _xi ² -adding to the first set of constraints; step T4, based on the first constraint set sum { L ] ₁ ,L ₂ ,…,L _m ,…,L _M A schematic diagram of the circuit between the first module column and the second module column is generated. According to the invention, by splitting the vertical line segments, the overlapping of the horizontal line segments is avoided, the complexity of a circuit schematic diagram is reduced, and the readability is improved.

Description

Circuit schematic diagram route planning system for avoiding signal line coverage

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a circuit schematic diagram route planning system for avoiding signal line coverage.

Background

With the rapid development of very large scale integrated circuit technology, chip designs are becoming more and more complex. In the chip design process, debugging and verification are needed by means of a circuit diagram visualization tool so as to assist a user in discovering potential problems in the design and improve development efficiency. The routing planning of the circuit schematic refers to that the connection relation among the given two or more circuit modules is represented by a plurality of horizontal or vertical signal lines through specific algorithms and constraints, so that a user can conveniently know the logic and hierarchical structure design among the modules. The schematic circuit diagram in the debugging and verifying tool is different from the wiring layout diagram at the rear end, so that the minimum space is used for completing the route planning of all signal lines, the schematic circuit diagram serves the design verification stage, the space is required, the connection relation among all modules in the chip design can be clearly and accurately described, and the hierarchical structure of the whole design is required to be clearly presented.

In the conventional route planning technology of the circuit schematic, only the constraint condition that the mutual coverage (overlay) between different signal lines cannot occur is followed, because the mutual coverage between different signal lines can affect the misjudgment of the connection relation by a user. However, merely considering the above constraint may result in an excessive number of vertical crossings (crosssolvers) between signal lines and an excessive number of signal line bends (Bending). Too many vertical crossings can complicate the schematic diagram of the circuit, reduce the functional readability, and are unfavorable for debugging and verification; the connection relationship becomes complex due to excessive bending times, which is unfavorable for driving and loading signals of the tracking module, thereby reducing the debugging and verification efficiency of the chip design. Therefore, how to provide a new circuit schematic diagram routing planning technology, reduce the complexity of the circuit schematic diagram, improve the readability, facilitate the driving and loading of signals of the user tracking module, and further improve the debugging and verification efficiency of the chip design is a technical problem to be solved.

Disclosure of Invention

The invention aims to provide a circuit schematic diagram route planning system for avoiding signal line coverage, which avoids the occurrence of horizontal line segment overlapping by splitting a vertical line segment, reduces the complexity of a circuit schematic diagram and improves the readability.

A circuit schematic diagram route planning system capable of avoiding signal line coverage comprises a first module column, a second module column, and K signal lines { L } arranged between the first module column and the second module column ₁ ，L ₂ ，…,L _k ,…L _K A preset first constraint condition, a memory and a processor which store calculation and programs, wherein L _k For the Kth signal line, K has a value ranging from 1 to K, L _k The device comprises a vertical line segment, at least two connecting points and a horizontal line segment, wherein the horizontal line segment is positioned between each connecting point and a corresponding pin of a first module column or a second module column, and the connecting direction and the vertical coordinate of each connecting point are known; the first constraint is H { a, b } which means that the vertical line segment of signal line a must be allocated on the first side of the vertical line segment of signal line b.

When the processor executes the computer program, the following steps are implemented:

step T1, traverse { L ] ₁ ，L ₂ ，…,L _k ,…L _K When meeting L _xi Is equal to L _xj Or satisfies L _xj Is equal to L _xi Is set by H { L }, on the ordinate of one of the connection points towards the first side _xi ,L _xj Generating a first constraint set, wherein the second side is opposite to the first side, L _xi 、L _xj Belongs to { L ] ₁ ，L ₂ ，…,L _k ,…L _K The values of ix, jx range from 1 to K, and ix+.jx.

Step T2, traversing the first constraint set, if H { L } is simultaneously present _xi ,L _xj Sum H { L } _xj ,L _xi Then L _xi Is split into L _xi ¹ And L _xi ² Will L _xi Is transferred to L entirely towards the connection point of the first side _xi ¹ Will L _xi Is transferred to L entirely towards the connection point of the second side _xi ² Selecting a distance L _xi ¹ And L _xi ² 1/B height, B, between the nearest unoccupied two adjacent pins above the lowest connection point of (1-B)>1 as L _xi ¹ And L _xi ² Is at L _xi ¹ And L _xi ² The new connection points are respectively arranged on the upper parts and are used for establishing L _xi ¹ And L _xi ² Is connected to the connection of (a).

Step T3, L _xi ¹ And L _xi ² Are added to { L } as a single signal line ₁ ，L ₂ ，…,L _k ,…L _K In { L }, generate ₁ ,L ₂ ,…,L _m ,…,L _M M is greater than K, set { L } _xi ¹ ,L _xj }、{L _xj ,L _xi ² -adding to said first set of constraints.

Step T4, based on the first constraint set and { L ] ₁ ,L ₂ ,…,L _m ,…,L _M A schematic diagram of the circuit between the first module column and the second module column is generated.

Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the circuit schematic diagram route planning system capable of avoiding signal line coverage can achieve quite technical progress and practicality, has wide industrial utilization value, and has at least the following beneficial effects:

The invention avoids the overlapping of horizontal line segments by splitting the vertical line segments, reduces the complexity of a circuit schematic diagram, improves the readability, is convenient for a user to track the driving and loading signals of a module, and further improves the debugging and verification efficiency of chip design.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of signal line sequencing to be processed according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a routing constraint vector of an initial state according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a routing constraint vector updated based on a first constraint set according to an embodiment of the present invention;

FIG. 4 is a diagram of a routing constraint vector updated based on a second set of constraint vectors according to an embodiment of the present invention;

FIG. 5 is a schematic circuit diagram generated in accordance with an embodiment of the present invention;

FIG. 6 is a routing constraint vector diagram updated based on a second constraint set according to a second embodiment of the present invention;

FIG. 7 is a schematic circuit diagram of a second embodiment of the present invention;

FIG. 8 is a routing constraint vector diagram obtained based on updating a second constraint set according to a third embodiment of the present invention;

FIG. 9 is a schematic circuit diagram generated in accordance with a third embodiment of the present invention;

FIG. 10 is a schematic diagram of a circuit generated based on a routing constraint vector diagram updated only on the first set of constraints;

FIG. 11 is a schematic diagram showing overlapping of horizontal segments of two signal lines;

fig. 12 is a schematic diagram of a fourth embodiment of the present invention after performing a process of avoiding overlapping of horizontal segments of two signal lines.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

In an application scenario of generating schematic routing, in addition to avoiding signal line overlap, it is desirable to reduce the number of signal line intersections and signal line bends as much as possible in order to enhance readability. There are different demands in practical applications, for example, in some situations, the space is limited, and thus the number of vertical channels to be set is limited. In some situations, the space is not particularly limited, but the number of signal line crossing points needs to be as small as possible, and in other situations, the number of vertical channels and the number of signal line crossing points need to be considered comprehensively, based on the above three requirements, the present invention proposes the first embodiment, the second embodiment and the third embodiment.

Embodiment 1,

For a space-limited scenario, the present invention proposes a first embodiment, which provides a space constraint-based schematic circuit routing system, comprising M signal lines { L } that need to be arranged between a first module column and a second module column ₁ ,L ₂ ,…,L _m ,…,L _M First constraint set { H { L } ₁ ^i, L ₁ ^j },H{L ₂ ⁱ ,L ₂ ^j },…,H{L _x ⁱ ,L _x ^j },…,H{L _X ⁱ ,L _X ^j Second constraint set { C { L } ₁ ^p ,L ₁ ^q :r ₁ },C{L ₂ ^p ,L ₂ ^q :r ₂ },…,C{L _y ^p ,L _y ^q :r _y },…,C{L _Y ^p ,L _Y ^q :r _Y -memory and processor storing calculations and programs. It should be noted that, in the first module row and the second module row, each module row includes at least one circuit module, each circuit module includes at least one pin, the abscissa of the pins belonging to the same module row is the same, the initial state of the abscissa of the pin is an unknown quantity, by generating a circuit schematic diagram route plan, the specific position of the abscissa can be determined, the ordinate of the pin is a known quantity, and the position can be determined based on the ordinate.

Wherein L is _m For the mth signal line, M has a value ranging from 1 to M, L _m Comprises a vertical line segment, at least two connection points and a horizontal line segment between each connection point and a corresponding pin of the first module column or the second module column. Each signal wire only comprises one vertical line segment, so that bending of the signal wire can be reduced, and readability of a circuit schematic diagram is improved. The connection direction and the ordinate of each connection point are known, and it is understood that the connection point ordinate is the same as the ordinate of the corresponding pin. L (L) ₁ ,L ₂ ,…,L _m ,…,L _M The serial numbers of the corresponding signal lines are sequentially ordered from small to large according to the sequence from the lowest connection point to high.

Stored in the first constraint set are all elements that meet the first constraint, H { L } _x ⁱ ,L _x ^j ' represents L _x ⁱ The vertical segments must be allocated at L _x ^j L on the first side of the vertical line segment _x ⁱ 、L _x ^j All belong to { L ] ₁ ，L ₂ ，…,L _m ,…L _M }，L _x ⁱ ≠L _x ^j The value range of X is 1 to X; the first constraint can avoid mutual coverage between different signal lines in the horizontal direction.

Stored in the second constraint set are all elements that meet the second constraint, C { L } _y ^p ,L _y ^q :r _y ' represents L _y ^p Is located at L _y ^q With respect to L _y ^p Is located at L _y ^q The number of reduced vertical crossings is r on the second side of the vertical segment of (2) _y ，L _y ^p ,L _y ^q All belong to { L ] ₁ ,L ₂ ,…,L _m ,…,L _M }，L _y ^p ≠L _y ^q The first side is the opposite side of the second side, and the value range of Y is 1 to Y. By introducing the second constraint, the number of vertical crossing points can be reduced. The vertical crossing points refer to different signal linesIs the point at which the vertical and horizontal lines intersect.

step S1, based on { L } ₁ ,L ₂ ,…,L _m ,…,L _M Constructing a routing constraint vector diagram comprising a start node, an end node, each L _m Corresponding node G _m Pointing from the start node to G _m Directed edge of (2), and G from _m Directed edges pointing to end nodes.

Step S2, according to H { L } _x ⁱ ,L _x ^j And updating the routing constraint vector diagram, wherein each node always has at least one directed edge pointing to the node and at least one directed edge pointing to another node from the node except for a starting node and a terminating node, and if one directed edge pointing to the second node from the first node exists between the first node and the second node, a vertical line segment representing a signal line corresponding to the first node needs to be distributed on a first side of a vertical line of the signal line corresponding to the second node.

Wherein, based on each H { L } _x ⁱ ,L _x ^j -updating the routing constraint vector graph. As an example, the first side is the left side and the second side is the right side. Or the first side is the right side, and the second side is the left side, and can be specifically set according to specific application requirements.

And S3, acquiring the node number maxN corresponding to the longest edge in the current routing constraint vector diagram, and determining a larger value in maxN and maxA as a target vertical channel number T, wherein maxA is a preset vertical channel maximum value.

Step S4, according to C { L ] _y ^p ,L _y ^q :r _y And updating the routing constraint vector diagram, and executing step S5 when the number of the longest edge nodes of the updated routing constraint vector diagram is equal to T.

It should be noted that in step S4, not all C { L }, are based on _y ^p ,L _y ^q :r _y Updating the route constraint vector graph, but updating one by one, and requiring judgment of the route when updatedIf the number of the longest edge nodes of the constraint vector diagram is equal to T, the updating needs to be stopped, because C { L } is continued after the number of the longest edge nodes of the updated routing constraint vector diagram is equal to T _y ^p ,L _y ^q :r _y Updating the routing constraint vector diagram may result in a further increase in the number of vertical channels.

And S5, generating a circuit schematic diagram between the first module column and the second module column based on the current routing constraint vector diagram.

It should be noted that, the right-left position relationship of the vertical line segment placement of the partial signal line is definitely constrained in the routing constraint vector diagram, and the target vertical channel number T has been determined in step S3, so that T target vertical channels are established in the first module column and the second module column, and the constraint condition in the current routing constraint vector diagram is satisfied, for L ₁ ,L ₂ ,…,L _m ,…,L _M And performing path planning to generate a circuit schematic diagram between the first module column and the second module column.

As an example, if L ₁ ，L ₂ ，…,L _m ,…L _M The signal lines with the same ordinate of the lowest connection point are arranged in the order from short to long. By combining L ₁ ，L ₂ ，…,L _m ,…L _M Ordering facilitates subsequent computations, and improves readability of the generated schematic circuit diagram.

As an example, in the step S2, according to H { L _x ⁱ ,L _x ^j -updating the routing constraint vector graph, comprising:

step R1, sequentially obtaining each H { L } _x ⁱ ,L _x ^j According to H { L } _x ⁱ ,L _x ^j Delete L _x ⁱ Corresponding node G _x ⁱ The directed edge currently pointing to the end node, the delete start node points to L _x ^j Corresponding node G _x ^j Is directed at G _x ⁱ And G _x ^j Construction of G therebetween _x ⁱ Pointing to G _x ^j Is a directional edge of (a).

As an example, the step S4 includes:

step S41, obtaining each C { L } in the current second constraint set _y ^p ,L _y ^q :r _y Weight W corresponding to _y ，W _y If at L _y ^p Corresponding node G _y ^p And L _y ^q Corresponding node G _y ^q G is added between _y ^p Pointing to G _y ^q From a start node to an end node and through G _y ^p And G _y ^q The number of nodes of the longest path of (a) is determined.

It will be appreciated that in step S41, L is not reduced _y ^p Corresponding node G _y ^p And L _y ^q Corresponding node G _y ^q G is added between _y ^p Pointing to G _y ^q But assume that the addition is performed, and the directed edges from the start node to the end node after the addition are obtained and pass through G _y ^p And G _y ^q As C { L }, the number of nodes of the longest path of (a) _y ^p ,L _y ^q :r _y Weight W corresponding to _y 。

Step S42, the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^p Deleting the directed edge currently pointing to the ending node, and pointing the starting node to the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^q Directed edge delete of (2), at the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^p And G _y ^q Construction of G therebetween _y ^p Pointing to G _y ^q Is a directional edge of (a).

It will be appreciated that as the routing constraint vector graph is updated, some of the nodes correspond to fingersThe directed edges to the end nodes may have been deleted, as may the directed edges to some of the nodes from the start node, so that in step S42, only the minimum W currently exists _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^p Only when the directed edge of the ending node is currently pointed to, the current minimum W needs to be executed _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^p The operation of deleting the directed edge currently pointing to the end node; similarly, only the current existing start node points to the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^q Only if the directed edge of (1) is needed to be executed to point the start node to the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^q Is deleted from the edge.

Wherein, preferably, if there are a plurality of minimum W _y Then a plurality of minimum W _y Corresponding C { L _y ^p ,L _y ^q :r _y L in } _y ^p W with minimum sequence number _y As the current minimum W _y The method comprises the steps of carrying out a first treatment on the surface of the If a plurality of minimum W _y Corresponding C { L _y ^p ,L _y ^q :r _y Minimum L of } _y ^p The serial numbers correspond to a plurality of numbers, the minimum W _y Corresponding plurality of minimum L _y ^p L in sequence number _y ^q W with minimum sequence number _y As the current minimum W _y 。

Step S43, judging whether the longest edge node number of the current route constraint vector diagram is equal to T, if yes, determining the current route constraint vector diagram as a target vector diagram, executing step S5, otherwise, determining the minimum W _y C { L _y ^p ,L _y ^q :r _y Delete from the second constraint set, return to execution step S41.

Through steps S41 to S43, the number of vertical intersections can be reduced as much as possible while ensuring that space constraints are satisfied.

As an example, the step S5 includes:

and S51, setting T vertical channels between the first module column and the second module column, according to the constraint condition of the current routing constraint vector diagram, avoiding overlapping of vertical line segments of signal lines, setting M signal lines in the T vertical channels, setting corresponding horizontal line segments to establish connection points of the signal lines and corresponding pins, and generating a circuit schematic diagram between the first module column and the second module column.

The existing method for avoiding overlapping of vertical line segments of the signal line falls within the protection scope of the present invention, and the present invention further provides a processing method for avoiding overlapping of vertical line segments of the signal line. As an example, the system further comprises a third set of constraints { V ₁ ,V ₂ ,…,V _z ,…V _Z }, wherein V is _z Representing the z-th subset of signal lines, V _z Comprises at least two signal lines V _z Belongs to { L ] ₁ ,L ₂ ,…,L _m ,…,L _M Identical V _z The vertical lines of the signal lines in (a) cannot be allocated in the same vertical channel, maxV is V _z In order to avoid overlapping of vertical segments, it is understood that the number of vertical channels must be greater than maxV, and in the case of space constraints, it is preferred that maxa=maxV, but it is understood that maxA may be greater than maxV if space constraints allow.

On the basis of setting the third constraint set, as an example, the step S5 includes:

step S51 ^， And sequentially acquiring signal line serial numbers corresponding to each level of nodes from the starting point node of the current routing constraint vector diagram, and generating a circuit schematic diagram between the first module column and the second module column by following constraint conditions in a third constraint set according to the sequence from small to large of the signal line serial numbers corresponding to each level of nodes.

As an example, the step S51 specifically includes:

a1, starting from a starting node of a current routing constraint vector diagram, acquiring a signal line sequence number corresponding to each stage of node, and obtaining (G) according to the signal line sequence number from small to large ₁ ^w ,G ₂ ^w ,…,G _u ^w ,…,G _f(w) ^w )，G _u ^w The value range of u is 1 to f (W), f (W) is the total number of the W-th level nodes, the value range of W is 1 to W, and W is the total level number.

Step A2, creating a first vertical channel between the first module column and the second module column, connecting G ₁ ¹ Corresponding vertical line segments are arranged in the first vertical channel, and corresponding horizontal line segments are arranged to establish G ₁ ¹ The connection of the corresponding connection point and the corresponding pin is set to u= 2,w =1, and step A3 is performed.

Step A3, starting from the first vertical channel, judging whether the signal line corresponding to the placed vertical line segment is corresponding to G in the vertical channel where the vertical line segment is placed at present one by one _u ^w Is of the same kind of V _z If not, G _u ^w Corresponding vertical line segments are arranged in the vertical channel of the signal line which is placed at present, and corresponding horizontal line segments are arranged to establish G _u ^w The connection point of the corresponding vertical line segment is connected with the corresponding pin; if all vertical channels on which signal lines are currently placed cannot be placed with G _u ^w Corresponding signal line, a new vertical channel placement G is created _u ^w Corresponding vertical line segments; and corresponding horizontal line segments are arranged to establish G _u ^w The corresponding connection point is connected with the corresponding pin.

As an example, in step A3, the signal lines sequentially add new vertical channels in a direction from the first side toward the second side. It should be noted that, in step A3, from the first vertical channel, whether each vertical channel accords with the vertical channel currently analyzed is sequentially analyzed, although the signal lines corresponding to the placed vertical line segments are all corresponding to G _u ^w Is of the same kind of V _z If not, G _u ^w Corresponding vertical lineThe segments are placed in the vertical channel currently being analyzed and no further vertical channels behind need to be determined. When all the channels with the vertical segments are analyzed completely and all the channels do not meet the placement conditions, a new vertical channel needs to be created to place G _u ^w Corresponding vertical line segments.

Step A4, if u < f (W), u=u+1 is set, and the process returns to step A3, if u=f (W), and W < W, u=1 is set, w=w+1, and the process returns to step A3, and if u=f (W), and w=w, the process ends.

It should be noted that, through the steps A1 to A4, after the vertical lines of the schematic circuit diagram satisfy the left-right distribution relationship, the lowest connection points are arranged in the order from low to high along the direction from the first side to the second side as far as possible, so as to improve the readability of the schematic circuit diagram.

It should be noted that all existing ways of generating the first constraint set fall within the protection scope of the present invention. The invention further proposes a way of generating a first set of constraints, which, as an example, when the processor executes the computer program, implements the following steps:

Step E1, traversing { L ] ₁ ,L ₂ ,…,L _m ,…,L _M When meeting L _i1 Is equal to L _j1 Or satisfies L _j1 Is equal to L _i1 Is set by H { L }, on the ordinate of one of the connection points towards the first side _i1 ,L _j1 -adding to the first set of constraints.

It will be appreciated that { L }, is required ₁ ,L ₂ ,…,L _m ,…,L _M The signal lines in the two are compared pairwise to find out all H { L { meeting the conditions _i1 ,L _j1 }。

Step E2, based on all H { L } _i1 ,L _j1 -generating said first set of constraints, wherein L _i1 、L _j1 All belong to { L ] ₁ ,L ₂ ,…,L _m ,…,L _M The value range of i1 and j1 is 1 to M, and i1 is not equal to j1.

It should be noted that all the existing ways of generating the second constraint set fall within the protection scope of the present invention. The invention further proposes a way of generating a second set of constraints, which, as an example, when the processor executes the computer program, implements the following steps:

step C1, traversing { L ] ₁ ,L ₂ ,…,L _m ,…,L _M }。

Step C2, obtaining L _i2 Is at L _j2 On the first side of the vertical line segment L _i2 And L _j2 In the overlapping portion of the vertical line segments of L _i2 Number of connection points towards the second side and L _j2 The sum of the number of connection points towards the first side cv1.

Step C3, obtaining L _i2 Is at L _j2 On the second side of the vertical line segment L _i2 And L _j2 In the overlapping portion of the vertical line segments of L _i2 The number of connection points towards the first side and L _j2 And the sum cv2 of the number of connection points towards the second side.

Step C4, if cv1 is smaller than cv2, setting C { L } _i2 ,L _j2 Cv2-cV1, adding to the second constraint set, and if cV1 is greater than cV2, setting C { L } _j2 ,L _i2 cV1-cV2 based on all C { L } _i2 ,L _j2 :cv2-cv1}、C{L _j2 ,L _i2 Cv1-cv2} generates the second set of constraints, where L _i2 、L _j2 All belong to { L ] ₁ ,L ₂ ,…,L _m ,…,L _M The value range of i2, j2 is 1 to M, and i2+.j2.

The second constraint set can be quickly and accurately generated through the steps C1-C4.

It should be noted that all the existing ways of generating the third constraint set fall within the protection scope of the present invention. The invention further proposes a way of generating a third set of constraints, which, as an example, when the processor executes the computer program, implements the following steps:

step D1, initializing a queue to be empty, and setting L ₁ Added to the queue, set m=2.

Step D2, determining the lowest highest connection point in the current queue as a reference point, and judging L _m If the lowest connection point of the (b) is lower than the reference point, executing step D3, otherwise, executing step D4.

Step D3, L _m Added to the queue if m<And M, setting m=m+1, returning to the execution step D2, if m=M, constructing all signal lines in the current queue to generate a signal line subset, placing the signal line subset in the third constraint set, generating the third constraint set, and ending the flow.

And D4, constructing and generating a subset of the signal lines from all the signal lines in the current queue, placing the subset of the signal lines in the third constraint set, deleting the signal lines corresponding to the current reference point from the current queue, and returning to the step D2.

All the signal line subsets can be quickly and accurately acquired through the steps D1-D4, so that a third constraint set is generated.

The first embodiment reduces the number of vertical crossing points as much as possible under the condition of preferentially meeting space constraint, route planning is concise and clear, complexity of a circuit schematic diagram is reduced, readability is improved, driving and loading signals of a user tracking module are facilitated, and debugging and verification efficiency of chip design is improved.

Embodiment II,

The present invention provides a second embodiment, which provides a schematic circuit diagram routing system based on vertical cross point constraint, comprising M signal lines { L ] arranged between a first module column and a second module column ₁ ,L ₂ ,…,L _m ,…,L _M First constraint set { H { L } ₁ ^i, L ₁ ^j },H{L ₂ ⁱ ,L ₂ ^j },…,H{L _x ⁱ ,L _x ^j },…,H{L _X ⁱ ,L _X ^j Second constraint set { C { L } ₁ ^p ,L ₁ ^q :r ₁ },C{L ₂ ^p ,L ₂ ^q :r ₂ },…,C{L _y ^p ,L _y ^q :r _y },…,C{L _Y ^p ,L _Y ^q :r _Y } and a third constraint set { V } ₁ ,V ₂ ,…,V _z ,…V _Z The system comprises a first module column, a second module column, a memory and a processor, wherein the memory and the processor store calculation and programs, the first module column and the second module column are used for storing calculation and programs, each module column comprises at least one circuit module, each circuit module comprises at least one pin, the abscissas of the pins belonging to the same module column are the same, the initial state of the abscissas of the pins is an unknown quantity, the specific position of the abscissas can be determined by generating a circuit schematic diagram route planning, the abscissas of the pins are known quantities, and the position can be judged on the basis of the abscissas.

Wherein L is _m For the mth signal line, M has a value ranging from 1 to M, L _m The circuit schematic diagram comprises a vertical line segment, at least two connecting points and a horizontal line segment between each connecting point and a corresponding pin positioned in the first module column or the second module column, wherein the connecting direction and the vertical coordinate of each connecting point are known, and each signal line only comprises one vertical line segment, so that bending of the signal line can be reduced, and the readability of the circuit schematic diagram is improved. The connection direction and the ordinate of each connection point are known, and it is understood that the connection point ordinate is the same as the ordinate of the corresponding pin. L (L) ₁ ,L ₂ ,…,L _m ,…,L _M The serial numbers of the corresponding signal lines are sequentially ordered from small to large according to the sequence from the lowest connection point to high. As an example, if L ₁ ，L ₂ ，…,L _m ,…L _M The signal lines with the same ordinate of the lowest connection point are arranged in the order from short to long. By combining L ₁ ，L ₂ ，…,L _m ,…L _M Ordering facilitates subsequent computations, and improves readability of the generated schematic circuit diagram.

Stored in the second constraint set are all elements that meet the second constraint, C { L } _y ^p ,L _y ^q :r _y ' represents L _y ^p Is located at L _y ^q With respect to L _y ^p Is located at L _y ^q The number of reduced vertical crossings is r on the second side of the vertical segment of (2) _y ，L _y ^p ,L _y ^q All belong to { L ] ₁ ,L ₂ ,…,L _m ,…,L _M }，L _y ^p ≠L _y ^q The first side is the opposite side of the second side, and the value range of Y is 1 to Y; by introducing the second constraint, the number of vertical crossing points can be reduced. The vertical crossing point refers to a point at which the vertical and horizontal lines of different signal lines intersect.

Stored in the third constraint set are all subsets of signal lines that meet the third constraint, V _z Representing the z-th subset of signal lines, V _z Comprises at least two signal lines V _z Belongs to { L ] ₁ ,L ₂ ,…,L _m ,…,L _M Identical V _z The vertical lines of the signal lines in (a) cannot be allocated in the same vertical channel, maxV is V _z Maximum number of medium signal lines; by introducing a third constraint, overlapping of vertical lines of different signal lines can be avoided.

It should be noted that all the existing ways of generating the first constraint set, the second constraint set, and the third constraint set fall within the protection scope of the present invention. The manner of generating the first constraint set, the second constraint set and the third constraint set according to the present invention is described in the first embodiment, and is not described herein.

step H1, based on { L ] ₁ ,L ₂ ,…,L _m ,…,L _M Constructing a routing constraint vector diagram comprising a start node, an end node, each L _m Corresponding node G _m Pointing from the start node to G _m Directed edges of (2) and from G _m Directed edges pointing to end nodes.

Step H2, according to all H { L } _x ⁱ ,L _x ^j And updating the routing constraint vector diagram, wherein each node always has at least one directed edge pointing to the node and at least one directed edge pointing to another node from the node except for a starting node and a terminating node, and if one directed edge pointing to the second node from the first node exists between the first node and the second node, a vertical line segment representing a signal line corresponding to the first node needs to be distributed on a first side of a vertical line of the signal line corresponding to the second node.

Wherein, based on each H { L } _x ⁱ ,L _x ^j -updating the routing constraint vector graph. As an example, the first side is the left side and the second side is the right side. Or the first side is the right side, and the second side is the left side, and can be specifically set according to specific application requirements. The step H2 may be implemented by using the step R1 of the embodiment, which is not described herein.

Step H3, according to all C { L } _y ^p ,L _y ^q :r _y -updating the routing constraint vector graph.

Wherein, according to each C { L } _y ^p ,L _y ^q :r _y -updating the routing constraint vector graph to achieve a reduction of the number of vertical crossings as much as possible.

And H4, starting from a starting point node of the current routing constraint vector diagram, sequentially acquiring signal line sequence numbers corresponding to each stage of nodes, and generating a circuit schematic diagram between the first module column and the second module column by following constraint conditions in a third constraint set according to the sequence from small to large of the signal line sequence numbers corresponding to each stage of nodes.

Step H4 can be specifically implemented through steps A1-A4, and steps A1-A4 are described in detail in the embodiment and are not described herein.

It should be noted that, the left-right positional relationship of the vertical line segments of the partial signal lines are definitely constrained in the routing constraint vector diagram, and the vertical line segments of the signal lines are definitely constrained in the third constraint set cannot be set in the same vertical channel, so that the L can be determined based on the current routing constraint vector diagram and the third constraint set ₁ ,L ₂ ,…,L _m ,…,L _M And performing path planning to generate a circuit schematic diagram between the first module column and the second module column.

As an example, the step H3 includes:

step H31, randomly obtaining a C { L } from the current second constraint set _y ^p ,L _y ^q :r _y C { L } to be obtained _y ^p ,L _y ^q :r _y G corresponding to _y ^p Deleting the directed edge currently pointing to the ending node, and pointing the starting node to the acquired C { L } _y ^p ,L _y ^q :r _y G corresponding to _y ^q Is deleted on the directed edge of the obtained C { L } _y ^p ,L _y ^q :r _y G corresponding to _y ^p And G _y ^q Construction of G therebetween _y ^p Pointing to G _y ^q Is a directional edge of (a).

It will be appreciated that, with the update of the routing constraint vector diagram, the directed edges of some nodes pointing to the end nodes may have been deleted, and the directed edges of the start nodes pointing to some nodes may have been deleted, so that in step H31, only the acquired C { L) currently exists _y ^p ,L _y ^q :r _y G corresponding to _y ^p When the directed edge of the ending node is currently pointed to, the execution of the obtained C { L } is only needed _y ^p ,L _y ^q :r _y G corresponding to _y ^p The operation of deleting the directed edge currently pointing to the end node; similarly, only the currently existing start node points to the acquired C { L } _y ^p ,L _y ^q :r _y G corresponding to _y ^q Only if the directed edge of (1) is needed to be executed to point the start node to the acquired C { L }, the start node is directed to the acquired C { L }, the C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^q Is deleted from the edge.

Step H32, the currently acquired C { L }, is processed _y ^p ,L _y ^q :r _y And deleting from the second constraint set, returning to the step S41 until the second constraint set is empty.

All C { L } can be quickly and efficiently based on the steps H31-H32 _y ^p ,L _y ^q :r _y Update routing constraint vector graph.

If it is required to reduce the number of vertical channels as much as possible under the condition of preferentially reducing the vertical crossing points, the step H3 may further include:

step H31 ^， Acquiring each C { L { in the current second constraint set _y ^p ,L _y ^q :r _y Weight W corresponding to _y ，W _y If at L _y ^p Corresponding node G _y ^p And L _y ^q Corresponding node G _y ^q G is added between _y ^p Pointing to G _y ^q From a start node to an end node and through G _y ^p And G _y ^q The number of nodes of the longest path of (a) is determined.

It will be appreciated that step H31 ^， Not to L _y ^p Corresponding node G _y ^p And L _y ^q Corresponding node G _y ^q G is added between _y ^p Pointing to G _y ^q But assume that the addition is performed, and the directed edges from the start node to the end node after the addition are obtained and pass through G _y ^p And G _y ^q As C { L }, the number of nodes of the longest path of (a) _y ^p ,L _y ^q :r _y Weight W corresponding to _y 。

Step H32 ^， Will currently minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^p Deleting the directed edge currently pointing to the ending node, and pointing the starting node to the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^q Directed edge delete of (2), at the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^p And G _y ^q Construction of G therebetween _y ^p Pointing to G _y ^q Is a directional edge of (a).

It will be appreciated that, as the routing constraint vector graph is updated, the directed edges of some nodes that point to the end node may have been deleted, and the directed edges of some nodes that point to the start node may have been deleted, thus, step H32 ^， Of which only the minimum W currently exists _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^p Only when the directed edge of the ending node is currently pointed to, the current minimum W needs to be executed _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^p The operation of deleting the directed edge currently pointing to the end node; similarly, only the current existing start node points to the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^q Only if the directed edge of (1) is needed to be executed to point the start node to the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^q Is provided withAnd deleting the edges.

Step H33 ^， Will currently minimum W _y C { L _y ^p ,L _y ^q :r _y Deleting the second constraint set, judging whether the current second constraint set is empty, if so, executing the step H4, otherwise, returning to execute the step H31 ^，。

By the step H31 ^， Step H32 ^， It is possible to obtain the same routing constraint vector diagram as the results of the steps H31 to H32, and it is also possible to obtain a routing constraint vector diagram having a smaller number of nodes on the longest side with respect to the routing constraint vector diagram updated in the steps H31 to H32, thereby reducing the number of vertical channels of the final generated schematic circuit diagram.

The second embodiment reduces the number of vertical crossing points to the greatest extent, so that the route planning is concise and clear, the complexity of a circuit schematic diagram is reduced, the readability is improved, the driving and signal loading of the user tracking module are facilitated, and the debugging and verification efficiency of the chip design is further improved.

Third embodiment,

For the scenario that the number of vertical channels and the number of signal line crossing points need to be comprehensively considered, the invention provides a third embodiment, and the third embodiment provides a circuit schematic routing system, which comprises M signal lines { L } needing to be arranged between a first module column and a second module column ₁ ,L ₂ ,…,L _m ,…,L _M Go (f) firstConstraint set { H { L } ₁ ^i, L ₁ ^j },H{L ₂ ⁱ ,L ₂ ^j },…,H{L _x ⁱ ,L _x ^j },…,H{L _X ⁱ ,L _X ^j Second constraint set { C { L } ₁ ^p ,L ₁ ^q :r ₁ },C{L ₂ ^p ,L ₂ ^q :r ₂ },…,C{L _y ^p ,L _y ^q :r _y },…,C{L _Y ^p ,L _Y ^q :r _Y } and a third constraint set { V } ₁ ,V ₂ ,…,V _z ,…V _Z The system comprises a first module column, a second module column, a memory and a processor, wherein the memory and the processor store calculation and programs, the first module column and the second module column are used for storing calculation and programs, each module column comprises at least one circuit module, each circuit module comprises at least one pin, the abscissas of the pins belonging to the same module column are the same, the initial state of the abscissas of the pins is an unknown quantity, the specific position of the abscissas can be determined by generating a circuit schematic diagram route planning, the abscissas of the pins are known quantities, and the position can be judged on the basis of the abscissas.

Wherein L is _m For the mth signal line, M has a value ranging from 1 to M, L _m The circuit schematic diagram comprises a vertical line segment, at least two connecting points and a horizontal line segment between each connecting point and a corresponding pin of the first module column or the second module column, wherein each signal line only comprises one vertical line segment, so that bending of the signal line can be reduced, and readability of the circuit schematic diagram is improved. The connection direction and the ordinate of each connection point are known, and it is understood that the connection point ordinate is the same as the ordinate of the corresponding pin. L (L) ₁ ,L ₂ ,…,L _m ,…,L _M The serial numbers of the corresponding signal lines are sequentially ordered from small to large according to the sequence from the lowest connection point to high. As an example, if L ₁ ，L ₂ ，…,L _m ,…L _M The signal lines with the same ordinate of the lowest connection point are arranged in the order from short to long. By combining L ₁ ，L ₂ ，…,L _m ,…L _M Ordering facilitates subsequent computations, and improves readability of the generated schematic circuit diagram.

Stored in the third constraint set are all subsets of signal lines that meet the third constraint, V _z Representing the z-th subset of signal lines, V _z Comprises at least two signal lines V _z Belongs to { L ] ₁ ,L ₂ ,…,L _m ,…,L _M Identical V _z The vertical lines of the signal lines in (a) cannot be allocated in the same vertical channel, maxV is V _z Maximum number of medium signal lines; by introducing a third constraint, a difference can be avoidedThe vertical lines of the signal lines overlap.

step F1, based on { L ] ₁ ,L ₂ ,…,L _m ,…,L _M Constructing a routing constraint vector diagram comprising a start node, an end node, each L _m Corresponding node G _m Pointing from the start node to G _m Directed edges of (2) and from G _m Directed edges pointing to end nodes.

Step F2, according to H { L _x ⁱ ,L _x ^j And updating the routing constraint vector diagram, wherein each node always has at least one directed edge pointing to the node and at least one directed edge pointing to another node from the node except for a starting node and a terminating node, and if one directed edge pointing to the second node from the first node exists between the first node and the second node, a vertical line segment representing a signal line corresponding to the first node needs to be distributed on a first side of a vertical line of the signal line corresponding to the second node.

Wherein, based on each H { L } _x ⁱ ,L _x ^j -updating the routing constraint vector graph. As an example, the first side is the left side and the second side is the right side. Or the first side is the right side, and the second side is the left side, and can be specifically set according to specific application requirements. The step F2 may be implemented by using the step R1 of the embodiment, which is not described herein.

And F3, acquiring the node number maxN corresponding to the longest edge in the current routing constraint vector diagram, and determining a larger value in the maxN and the maxV as a target vertical channel number T.

Step F4, according to C { L ] _y ^p ,L _y ^q :r _y Updating the routing constraint vector diagram, and judging each C { L { after the longest edge node number of the updated routing constraint vector diagram is equal to T _y ^p ,L _y ^q :r _y Updating whether the number F of the longest edge nodes increased by the routing constraint vector diagram meets r _y >n is F, if satisfied, based on the C { L } _y ^p ,L _y ^q :r _y Updating the routing constraint vector graph, otherwise, skipping the C { L } to _y ^p ,L _y ^q :r _y All over C { L }, until completion _y ^p ,L _y ^q :r _y And updating the routing constraint vector diagram, wherein n is an integer greater than or equal to 1.

Wherein, in order to comprehensively consider the number of vertical channels and the number of signal line intersections, it is necessary to continue the judgment based on C { L } when the number of the longest edge nodes of the updated routing constraint vector diagram is equal to T _y ^p ,L _y ^q :r _y When updating the routing constraint vector diagram, the relationship between the number of reduced cross nodes and the number of increased vertical tracks is determined to be C { L }, based on _y ^p ,L _y ^q :r _y Updating the routing constraint vector graph, otherwise, skipping the C { L } to _y ^p ,L _y ^q :r _y }. Preferably, n has a value of 2.

And F5, starting from a starting point node of the current routing constraint vector diagram, sequentially acquiring signal line sequence numbers corresponding to each stage of nodes, and generating a circuit schematic diagram between the first module column and the second module column according to constraint conditions in a third constraint set by the signal line sequence numbers corresponding to each stage of nodes from small to large.

Step F5 can be specifically implemented through steps A1-A4, and steps A1-A4 are described in detail in the embodiment and are not described herein.

Note that, the left and right positions of the vertical line segment placement of the partial signal line are explicitly constrained in the routing constraint vector diagramThe relation, and the vertical line segments of the third constraint set which explicitly limit which signal lines can not be arranged in the same vertical channel, therefore, the vector diagram and the third constraint set can be constrained to L based on the current route ₁ ,L ₂ ,…,L _m ,…,L _M And performing path planning to generate a circuit schematic diagram between the first module column and the second module column.

As an example, the step F4 includes:

step F41, obtaining each C { L } in the current second constraint set _y ^p ,L _y ^q :r _y Weight W corresponding to _y ，W _y If at L _y ^p Corresponding node G _y ^p And L _y ^q Corresponding node G _y ^q G is added between _y ^p Pointing to G _y ^q From a start node to an end node and through G _y ^p And G _y ^q The number of nodes of the longest path of (a) is determined.

It will be appreciated that in step F41L is not _y ^p Corresponding node G _y ^p And L _y ^q Corresponding node G _y ^q G is added between _y ^p Pointing to G _y ^q But assume that the addition is performed, and the directed edges from the start node to the end node after the addition are obtained and pass through G _y ^p And G _y ^q As C { L }, the number of nodes of the longest path of (a) _y ^p ,L _y ^q :r _y Weight W corresponding to _y 。

Step F42, if the number of the longest edge nodes of the current routing constraint vector diagram is smaller than T, step F43 is executed, and if the number of the longest edge nodes of the current routing constraint vector diagram is equal to T, step F44 is executed.

Step F43, minimum W at present _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^p Deleting the directed edge currently pointing to the ending node, and pointing the starting node to the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^q Directed edge delete of (2), at the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^p And G _y ^q Construction of G therebetween _y ^p Pointing to G _y ^q Step F45 is performed.

It will be appreciated that, with the update of the routing constraint vector diagram, the directed edges of some nodes pointing to the end nodes may have been deleted, and the directed edges of the start nodes pointing to some nodes may have been deleted, so that in step F43, only the minimum W currently exists _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^p Only when the directed edge of the ending node is currently pointed to, the current minimum W needs to be executed _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^p The operation of deleting the directed edge currently pointing to the end node; similarly, only the current existing start node points to the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^q Only if the directed edge of (1) is needed to be executed to point the start node to the current minimum W _y C { L _y ^p ,L _y ^q :r _y G corresponding to _y ^q Is deleted from the edge.

Step F44, executing step F41 to obtain each current C { L } _y ^p ,L _y ^q :r _y Weight W corresponding to _y Judging the minimum W _y C { L _y ^p ,L _y ^q :r _y Updating whether the number F of the longest edge nodes increased by the routing constraint vector diagram meets r _y >n is equal to F, if yes, executing step F43, otherwise, executing step F45;

step F45, the current minimum W _y C { L _y ^p ,L _y ^q :r _y Delete from the second constraint set, return to execution step F41.

The routing constraint vector diagram can be updated by comprehensively considering the decrease amount of the number of the cross nodes and the increase amount of the number of the vertical channels through the steps F41 to F45.

In the third embodiment, the number of the vertical cross points and the number of the vertical channels required to be increased are comprehensively considered, so that route planning is concise and clear, the complexity of a circuit schematic diagram is reduced, the readability is improved, the driving and signal loading of a user tracking module are facilitated, and the debugging and verification efficiency of chip design is further improved.

It should be noted that, in general, the overlapping of the horizontal line segments of the signal line may be avoided by the first constraint condition, but in some special cases, the overlapping of the horizontal line segments of the signal line cannot be avoided by the first constraint condition, and the first constraint condition conflicts, so that the fourth embodiment is further proposed in the present invention.

The first, second and third embodiments are further described below by way of specific examples. As illustrated in the example of fig. 1, the first module column is module column 1, including circuit module a; the second module column is module column 2, which includes circuit module B and circuit module C, and includes 9 signal lines in total, and has been arranged in order from low to high at the lowest connection point in fig. 1. The arrow direction represents the connection direction of the connection point. It should be noted that, at this stage, the horizontal line segment may not be drawn, because the abscissa is not well defined, and the corresponding horizontal line segment is drawn after the determination by the routing plan. The first constraint set obtained based on the example shown in fig. 1 is { H {1,2}, H {5,1}, H {4,8}, the second constraint set is { C {4,3:2}, C {4,9:2}, C {5,3:2}, C {7,2:2}, C {7,6:2}, C {3,1:2}, C {4,5:1}, C {7,4:2}, C {6,5:1}, C {7,5:3}, C {8,5:2}, and the third constraint set is { V {1,2,3,4,5, 6,7}, V {2,4,5,6,8}, V {4,8,9}, maxv=5, and it should be noted that in this embodiment, the first side is the left side.

Based on the example shown in fig. 1, a corresponding route constraint vector diagram is constructed, and the initial state is the route constraint vector diagram shown in fig. 2. And updating the routing constraint vector diagram based on H {1,2}, H {5,1}, and H {4,8}, to obtain the routing constraint vector diagram shown in FIG. 3. Next, for the scenario described in embodiment one, first, maxn=3 is calculated from the current routing constraint vector diagram (longest edge: node 5->Node 1->Node 2), maxv=5. Thus t=5. However, the order of the C rules needs to be determined by ordering the C rules. Based on the weight calculated by the current routing constraint vector diagram, updating the routing constraint vector diagram based on C {4,3:2} according to the weight ordering, wherein the number of the longest edge nodes of the updated routing constraint vector diagram is 2 and is smaller than 5. Therefore, C {4,3:2} is deleted from the second constraint set, weights are recalculated based on the current routing constraint vector diagram, reordered, and C { L } with the minimum current weights is acquired _y ^p ,L _y ^q :r _y Update routing constraint vector graph. And so on until after updating the routing constraint vector diagram based on C {4,5:1}, the number of nodes at the longest edge of the current routing constraint vector diagram is 5 (node 4->Node 5->Node 3->Node 1->Node 2), as shown in fig. 4. In the first embodiment, the schematic circuit diagram shown in fig. 5 can be drawn based on the routing constraint vector diagram shown in fig. 4.

For embodiment two, based on all C { L } _y ^p ,L _y ^q :r _y Updating the routing constraint vector diagram shown in fig. 2 to obtain the routing constraint vector diagram shown in fig. 6, and generating the schematic circuit diagram shown in fig. 7 based on the routing constraint vector diagram shown in fig. 6.

For embodiment three, taking n=2 as an example, after the routing constraint vector diagram shown in fig. 4 is obtained, the following is based on fig. 4The illustrated routing constraint vector diagram further acquires C {7,5:3} corresponding to the current minimum weight, if the routing constraint vector diagram is updated based on C {7,5:3}, the number of reduced vertical crossing points is 3, the number of newly added longest edge nodes is 0, and r is satisfied _y >n.f, updating the routing constraint vector diagram based on C {7,5:3}, and so on, until all C { L } _y ^p ,L _y ^q :r _y And judging that the updating is finished to obtain a routing constraint vector diagram shown in fig. 8, and generating a circuit schematic diagram shown in fig. 9 based on the routing constraint vector diagram shown in fig. 8 in a third embodiment.

If only the signal lines are considered to be non-overlapping, the schematic circuit diagram shown in fig. 10 can be generated directly based on the routing constraint vector diagram shown in fig. 3. The routing arrangement shown in fig. 10 is compact, with the number of vertical intersections=26 and the number of vertical channels 5. Based on

In fig. 5 obtained in the first embodiment, the number of vertical intersections is 21, and the number of vertical intersections is reduced by 4 compared with fig. 10, under the constraint of keeping the number of vertical channels to be 5.

In fig. 7 obtained in the second embodiment, the number of vertical intersections is 12 without considering the number of vertical channels, and 9 vertical intersections are reduced as compared with fig. 10.

In fig. 9 obtained in the third embodiment, when the number of vertical channels and the number of vertical intersections are taken into consideration, the number of vertical intersections is 16, and the number of vertical channels is 6, and compared with fig. 10, only 1 vertical channel is added, and 5 vertical intersections are reduced.

As can be seen from the comparison, the schematic circuit diagrams obtained in the first, second and third embodiments can achieve simple and clear route planning, reduce complexity of the schematic circuit diagram, improve readability, facilitate driving and loading signals of the user tracking module, and further improve debugging and verification efficiency of chip design, compared with fig. 10 in which first number lines are overlapped.

Fourth embodiment,

A fourth embodiment provides a schematic circuit diagram routing system for avoiding signal line coverage, including a first module row, a second module row, and a first module row and a second module rowK signal lines { L between columns ₁ ，L ₂ ，…,L _k ,…L _K The system comprises a first module column, a second module column, a memory and a processor, wherein the memory and the processor are used for storing calculation and programs, the first constraint condition is preset, the memory and the processor are used for storing calculation and programs, the first module column and the second module column are used for storing calculation and programs, each module column comprises at least one circuit module, each circuit module comprises at least one pin, the abscissas of the pins belonging to the same module column are identical, the initial state of the abscissas of the pins is an unknown quantity, the specific position of the abscissas can be determined through generating a circuit schematic diagram route planning, the abscissas of the pins are known quantities, and the position can be judged on the basis of the abscissas.

Wherein L is _k For the Kth signal line, K has a value ranging from 1 to K, L _k The circuit schematic diagram comprises a vertical line segment, at least two connecting points and a horizontal line segment between each connecting point and a corresponding pin of the first module column or the second module column, wherein each signal line only comprises one vertical line segment, so that bending of the signal line can be reduced, and readability of the circuit schematic diagram is improved. The connection direction and the ordinate of each connection point are known, and it is understood that the connection point ordinate is the same as the ordinate of the corresponding pin. The first constraint is H { a, b } which means that the vertical line segment of signal line a must be allocated on the first side of the vertical line segment of signal line b.

When H { L } is simultaneously present _xi ,L _xj Sum H { L } _xj ,L _xi When a first constraint conflict occurs, L cannot be avoided by the first constraint alone _xi And L _xj Overlapping part of the horizontal line segments of (2), so step T2 further adds L _xi Is split into L _xi ¹ And L _xi ² And establish L _xi ¹ And L _xi ² Is connected to the connection of (a). In addition, the distance L is selected _xi ¹ And L _xi ² The 1/B height between the nearest unoccupied adjacent two pins above the lowest connection point of the lowest of the plurality can enable the connection L to be as much as possible _xi ¹ And L _xi ² Is placed at a lower position, reducing the number of vertical intersections that need to be increased. The value of B can be an integer of 2, 4 and the like, preferably, the value of B is 2, so that the neatness of the circuit schematic diagram is improved.

Step T3, L _xi ¹ And L _xi ² Are added to { L } as a single signal line ₁ ，L ₂ ，…,L _k ,…L _K In }, give birth toInto { L ] ₁ ,L ₂ ,…,L _m ,…,L _M M is greater than K, set { L } _xi ¹ ,L _xj }、{L _xj ,L _xi ² -adding to said first set of constraints.

It should be noted that { L-based ₁ ,L ₂ ,…,L _m ,…,L _M Any processing manner of the first, second and third embodiments may be further implemented by the first constraint set, and will not be described herein.

Wherein, the left-right position relation of the vertical line segment placement of partial signal lines is definitely restrained in the first constraint set, for L ₁ ,L ₂ ,…,L _m ,…,L _M And (3) path planning is carried out, and overlapping of vertical line segments is avoided, so that a circuit schematic diagram between the first module column and the second module column can be generated.

In the step T2, the newly added connection point is located at L _xi ¹ And L _xi ² And extending the vertical line segment with the newly added connection point outside the vertical line segment to the corresponding newly added connection point above one corresponding vertical line segment and outside the other corresponding vertical line segment. It will be appreciated that the length of the vertical segment above the vertical segment for the newly added connection point is the distance from the highest connection point to the lowest connection point assigned. The length of the vertical line segment of the newly added connection point outside the vertical line segment is the distance from the highest connection point allocated to the newly added connection point.

For further explanation, a specific embodiment is provided, assuming that H {1,2} and H {2,1} coexist, as illustrated in fig. 10, splitting the vertical line segment of the signal line 1 is required, splitting the vertical line segment of the signal line 1 into two vertical line segments of 1.1 and 1.2, and transferring both left connections of the original 1 to 1.1, transferring both right connections to 1.2, then connecting 1.1 and 1.2, as illustrated in fig. 11, and finally constructing H {1.1,2} and H {2,1.2}, in which channel represents a channel.

As an example, in the step T3, L ₁ ,L ₂ ,…,L _m ,…,L _M The lowest connection points are arranged in order from low to high. If L ₁ ，L ₂ ，…,L _m ,…L _M The signal lines with the same ordinate of the lowest connection point are arranged in the order from short to long. By combining L ₁ ，L ₂ ，…,L _m ,…L _M Ordering facilitates subsequent computations, and improves readability of the generated schematic circuit diagram.

As an example, the step T4 includes:

step T41, according to L ₁ ,L ₂ ,…,L _m ,…,L _M Drawing a vertical segment of each signal line in a vertical channel between the first module column and the second module column following each constraint condition in the first set of constraints;

and step T42, setting corresponding horizontal line segments to establish connection between connection points of each signal line and corresponding pins, and generating a circuit schematic diagram between the first module column and the second module column.

In the process of generating the schematic circuit diagram through the steps T41 to T42, overlapping of the vertical segments is avoided. The existing manner of avoiding overlapping of vertical line segments falls entirely within the scope of the present invention.

The invention still further provides a way to avoid overlapping of vertical segments, as an example, the system further comprises a third set of constraints { V ₁ ,V ₂ ,…,V _z ,…V _Z }, wherein V is _z Representing the z-th subset of signal lines, V _z Comprises at least two signal lines V _z Belongs to { L ] ₁ ,L ₂ ,…,L _m ,…,L _M Identical V _z The vertical lines of the signal lines in (a) cannot be allocated in the same vertical channel. The specific construction of the third constraint set is already described in detail in the first step D1-step D4 of the embodiment, and will not be described herein.

On the basis of constructing the third constraint set, as an example, the step T4 is replaced by:

step T4 ^， Based on the first constraint set, the third constraint set and { L } ₁ ,L ₂ ,…,L _m ,…,L _M A schematic diagram of the circuit between the first module column and the second module column is generated.

Specifically, the step T4 ^， Comprising the following steps:

step T41 ^， Adjusting L based on a first set of constraints ₁ ,L ₂ ,…,L _m ,…,L _M Is arranged in the order of: if H { a, b }, and signal line a is arranged before signal line b, signal line b is adjusted to the previous position of signal line a, and a new rank (L) is generated after all adjustments based on the first constraint set ₁ ^， ,L ₂ ^， ,…,L _m ^， ,…,L _M ^， )，L _m ^， To adjust the signal line at the m-th position after sequencing.

Step T42 ^， Creating a first vertical channel between the first module column and the second module column, adding L ₁ ^， Corresponding vertical line segments are arranged in the first vertical channel, and corresponding horizontal line segments are arranged to establish L ₁ ^， Is connected with the corresponding pin, m=2 is set, and step T43 is executed ^，。

Step T43 ^， Judging whether the signal line is positioned with L from the first vertical channel one by one _m ^， Is of the same kind of V _z If not, then L _m ^， The corresponding vertical line segment is arranged in the vertical channel of the signal line which is placed at present, and the corresponding horizontal line segment is arranged to establish L _m ^， Is connected with the corresponding pin; if all vertical channels on which signal lines are currently placed cannot be placed with L _m ^， Corresponding vertical line segment, a new vertical channel placement L is created _m ^， Corresponding vertical line segments; and setting corresponding horizontal line segment establishmentL _m ^， Is connected to the corresponding pin.

Step T44 ^， If m is<M, then set m=m+1, return to execute step T43 ^， If m=m, the flow ends.

In the embodiment, the mode of splitting the vertical line segments is adopted, so that the overlapping of horizontal line segments is avoided, the complexity of a circuit schematic diagram is reduced, the readability is improved, the driving and loading signals of a user tracking module are facilitated, and the debugging and verification efficiency of chip design is further improved.

It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.

The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.

Claims

1. A circuit schematic route planning system for avoiding signal line coverage is characterized in that,

comprises a first module column, a second module column, and K signal lines { L } arranged between the first module column and the second module column ₁ ，L ₂ ，…,L _k ,…L _K First constraint condition preset, store meterA memory and a processor for an algorithm, wherein,

L _k for the Kth signal line, K has a value ranging from 1 to K, L _k The device comprises a vertical line segment, at least two connecting points and a horizontal line segment, wherein the horizontal line segment is positioned between each connecting point and a corresponding pin of a first module column or a second module column, and the connecting direction and the vertical coordinate of each connecting point are known; the first constraint is H { a, b }, H { a, b } indicating that the vertical line segment of the signal line a must be allocated on the first side of the vertical line segment of the signal line b;

step T1, traverse { L ] ₁ ，L ₂ ，…,L _k ,…L _K When meeting L _xi Is equal to L _xj Or satisfies L _xj Is equal to L _xi Is set by H { L }, on the ordinate of one of the connection points towards the first side _xi ,L _xj Generating a first constraint set, wherein the second side is opposite to the first side, L _xi 、L _xj Belongs to { L ] ₁ ，L ₂ ，…,L _k ,…L _K The value range of ix, jx is 1 to K, and ix is not equal to jx;

step T2, traversing the first constraint set, if H { L } is simultaneously present _xi ,L _xj Sum H { L } _xj ,L _xi Then L _xi Is split into L _xi ¹ And L _xi ² Will L _xi Is transferred to L entirely towards the connection point of the first side _xi ¹ Will L _xi Is transferred to L entirely towards the connection point of the second side _xi ² Selecting a distance L _xi ¹ And L _xi ² 1/B height, B, between the nearest unoccupied two adjacent pins above the lowest connection point of (1-B)>1 as L _xi ¹ And L _xi ² Is at L _xi ¹ And L _xi ² The new connection points are respectively arranged on the upper parts and are used for establishing L _xi ¹ And L _xi ² Is connected with the connecting part of the connecting part;

step T3, L _xi ¹ And L _xi ² Are added to { L } as a single signal line ₁ ，L ₂ ，…,L _k ,…L _K In { L }, generate ₁ ,L ₂ ,…,L _m ,…,L _M M is greater than K, set { L } _xi ¹ ,L _xj }、{L _xj ,L _xi ² -adding to said first set of constraints;

2. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

in the step T2, the newly added connection point is located at L _xi ¹ And L _xi ² And extending the vertical line segment with the newly added connection point outside the vertical line segment to the corresponding newly added connection point above one corresponding vertical line segment and outside the other corresponding vertical line segment.

3. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

in the step T3, L ₁ ,L ₂ ,…,L _m ,…,L _M The lowest connection points are arranged in order from low to high.

4. The system of claim 3, wherein the system further comprises a controller configured to control the controller,

the step T4 includes:

step T41, according to L ₁ ,L ₂ ,…,L _m ,…,L _M Following each constraint in the first set of constraints, drawing a vertical line of each signal line in a vertical channel between the first module column and the second module columnA segment;

5. The system of claim 3, wherein the system further comprises a controller configured to control the controller,

the system further comprises a third constraint set { V } ₁ ,V ₂ ,…,V _z ,…V _Z }, wherein V is _z Representing the z-th subset of signal lines, V _z Comprises at least two signal lines V _z Belongs to { L ] ₁ ,L ₂ ,…,L _m ,…,L _M Identical V _z The vertical lines of the signal lines in (a) cannot be allocated in the same vertical channel.

6. The system of claim 5, wherein the system further comprises a controller configured to control the controller,

when the processor executes the computer program, the following steps are also implemented:

step D1, initializing a queue to be empty, and setting L ₁ Adding to a queue, setting m=2;

Step D2, determining the lowest highest connection point in the current queue as a reference point, and judging L _m If the lowest connection point of the two points is lower than the reference point, executing the step D3, otherwise, executing the step D4;

step D3, L _m Added to the queue if m<Setting m=m+1, returning to the execution step D2, if m=m, constructing all signal lines in the current queue to generate a signal line subset, placing the signal line subset in the third constraint set, generating the third constraint set, and ending the flow;

7. The system of claim 5, wherein the system further comprises a controller configured to control the controller,

the step T4 is replaced by:

8. The system of claim 7, wherein the system further comprises a controller configured to control the controller,

said step T4 ^， Comprising the following steps:

step T41 ^， Adjusting L based on a first set of constraints ₁ ,L ₂ ,…,L _m ,…,L _M Is arranged in the order of: if H { a, b }, and signal line a is arranged before signal line b, signal line b is adjusted to the previous position of signal line a, and a new rank (L) is generated after all adjustments based on the first constraint set ₁ ^， ,L ₂ ^， ,…,L _m ^， ,…,L _M ^， )，L _m ^， To adjust the signal line at the m-th position after sequencing;

step T42 ^， Creating a first vertical channel between the first module column and the second module column, adding L ₁ ^， Corresponding vertical line segments are arranged in the first vertical channel, and corresponding horizontal line segments are arranged to establish L ₁ ^， Is connected with the corresponding pin, m=2 is set, and step T43 is executed ^，；

Step T43 ^， Judging whether the signal line is positioned with L from the first vertical channel one by one _m ^， Is of the same kind of V _z If not, then L _m ^， The corresponding vertical line segment is arranged in the vertical channel of the signal line which is placed at present, and the corresponding horizontal line segment is arranged to establish L _m ^， Is connected with the corresponding pin; if all vertical channels on which signal lines are currently placed cannot be placed with L _m ^， Corresponding vertical line segment, a new vertical channel placement L is created _m ^， Corresponding vertical line segments; and sets up corresponding horizontal line segment to establish L _m ^， Is connected with the corresponding pin;