CN116007771A - Digital temperature sensor - Google Patents

Abstract

The application provides a digital temperature sensor, which comprises an oscillator, a phase discriminator and a counter; the voltage-controlled oscillator is respectively connected with the phase discriminator and the counter, and the phase discriminator is also connected with the counter; an oscillator for receiving an input voltage to generate a clock signal that varies with the input voltage; wherein the input voltage varies with temperature; the phase discriminator is used for converting the clock signal generated by the voltage-controlled oscillator into a pulse signal after detecting that the clock signal reaches a preset frequency; the counter is used for counting the frequency of the clock signal output by the voltage-controlled oscillator and outputting a data coding value corresponding to the counting value when the level state of the detection pulse signal is a first preset level; the data encoded values are used to characterize the temperature values. The method and the device can reduce the area of the device and the power consumption of the device.

Description

Digital temperature sensor

Technical Field

The application relates to the technical field of integrated circuits, in particular to a digital temperature sensor.

Background

With the vigorous development of microprocessors, more and more microprocessors are being developed in the directions of miniaturization, low cost, low power consumption and high integration. In the prior art, a micro-processor integrated with a temperature sensor is presented, and the temperature sensor is usually integrated with an Analog-to-Digital Converter (ADC), so that a bandgap voltage proportional to absolute temperature is detected by using the Analog-to-digital converter in a voltage domain to detect temperature.

However, in the course of research and practice of the prior art, the inventors of the present application found that, although the temperature sensor integrated in the analog-to-digital converter has advantages of high accuracy, good linearity, wide measurement temperature range, low voltage sensitivity, etc., it has disadvantages of large area and high power consumption due to the need of using the analog-to-digital converter to detect the temperature.

The foregoing description is provided for general background information and does not necessarily constitute prior art.

Disclosure of Invention

Aiming at the technical problems, the application provides a digital temperature sensor which can reduce the area of a device and the power consumption of the device.

The application provides a digital temperature sensor, which comprises an oscillator, a phase discriminator and a counter; the oscillator is respectively connected with the phase detector and the counter, and the phase detector is also connected with the counter;

the oscillator is used for receiving an input voltage to generate a clock signal which varies with the input voltage; wherein the input voltage varies with temperature;

the phase discriminator is used for converting the clock signal generated by the oscillator into a pulse signal after detecting that the clock signal reaches a preset frequency;

the counter is used for counting the frequency of the clock signal output by the oscillator and outputting a data coding value corresponding to the counted value when the level state of the pulse signal is detected to be a first preset level; the data encoding values are used to characterize the temperature values.

Optionally, the digital temperature sensor further comprises an input circuit, wherein the input circuit comprises a charge-discharge capacitor, and the charge-discharge capacitor is used for sampling the input voltage and outputting the sampled voltage to the oscillator.

Optionally, the input circuit further includes a switch unit, where the switch unit is configured to control an amount of charge that the charge-discharge capacitor needs to accumulate to charge to the first preset level, and control the oscillator to discharge the charge-discharge capacitor.

Optionally, the phase detector is further configured to switch the level state of the pulse signal to a second preset level after the charge-discharge capacitor discharges, and stop counting by the counter.

Optionally, the digital temperature sensor further comprises a logic control unit, wherein the logic control unit is respectively connected with the oscillator, the phase detector, the counter and the switch unit and is used for controlling the switch state of the switch unit and controlling the enabling switch states of the oscillator, the phase detector and the counter.

Optionally, the digital temperature sensor further comprises a delay unit, wherein the delay unit is respectively connected with the oscillator, the phase discriminator and the counter;

the delay unit is used for receiving the clock signal output by the oscillator, converting the clock signal into a delay clock signal and outputting the delay clock signal to the phase discriminator;

the phase discriminator is also used for comparing the clock signal with the delay clock signal and outputting a corresponding pulse signal according to the comparison result.

Optionally, the delay unit is further configured to output the delay clock signal to the counter, the phase discriminator is further configured to output the pulse signal to the counter, and the counter is further configured to count a frequency of the delay clock signal when a level state of the pulse signal is the first preset level, and output a corresponding data encoding value according to the count value.

Optionally, the oscillator includes a plurality of inverters connected in series, wherein an output terminal of a last inverter is connected to an input terminal of a first inverter, and a supply voltage of each inverter is the input voltage.

Optionally, the logic control unit comprises a voltage comparator, a latch, an exclusive-or gate and an NOT gate which are electrically connected in sequence;

the voltage comparator is used for outputting a signal of a first preset level when the input voltage in the process of monitoring the charge-discharge capacitor sampling reaches a reference voltage, and outputting the input voltage to the latch;

the latch is used for outputting the signal of the first preset level after receiving the input voltage and the pulse signal;

the exclusive-OR gate is used for comparing the received reference voltage with the level state of the output signal of the latch and outputting a first enabling signal of a first preset level or a second preset level according to the comparison result;

and the NOT gate is used for converting the first enabling signal into a second enabling signal, and the first enabling signal and the second enabling signal are used for controlling the state of the switch unit.

Optionally, the counting the frequency of the clock signal output by the oscillator and outputting the data coding value corresponding to the count value includes:

detecting the pulse width of the pulse signal and determining the corresponding counting time length;

counting the frequency of the clock signal according to the counting time length to obtain a corresponding counting value;

and determining a corresponding data coding value according to the counting value.

The implementation of the embodiment of the application has the following beneficial effects:

as described above, the digital temperature sensor provided by the present application includes an oscillator, a phase detector, and a counter; the oscillator is respectively connected with the phase discriminator and the counter, and the phase discriminator is also connected with the counter; an oscillator for receiving an input voltage to generate a clock signal that varies with the input voltage; the phase discriminator is used for converting the clock signal generated by the detection oscillator into a pulse signal after the clock signal reaches a preset frequency; the counter is used for counting the frequency of the clock signal output by the oscillator and outputting a data coding value corresponding to the counting value when the level state of the detection pulse signal is a first preset level; the data encoded values are used to characterize the temperature values. Because this application compares with traditional temperature sensor, need not extra increase area great and the higher analog-to-digital converter of consumption, also can realize detecting the effect of temperature, can reduce digital temperature sensor's device area like this to reduce whole consumption. Therefore, the method and the device can reduce the area of the device and the power consumption of the device.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application. In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

FIG. 1 is a schematic diagram of a first implementation of a digital temperature sensor provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of a second implementation of a digital temperature sensor provided in an embodiment of the present application;

fig. 3 is a schematic structural diagram of a logic control unit according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a third implementation of a digital temperature sensor provided in an embodiment of the present application;

fig. 5 is a schematic structural diagram of a voltage-controlled oscillator according to an embodiment of the present application;

fig. 6 is a schematic flow chart of temperature measurement provided in an embodiment of the present application.

The realization, functional characteristics and advantages of the present application will be further described with reference to the embodiments, referring to the attached drawings. Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the element defined by the phrase "comprising one … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element, and furthermore, elements having the same name in different embodiments of the present application may have the same meaning or may have different meanings, a particular meaning of which is to be determined by its interpretation in this particular embodiment or by further combining the context of this particular embodiment.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope herein. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context. Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" specify the presence of stated features, steps, operations, elements, components, items, categories, and/or groups, but do not preclude the presence, presence or addition of one or more other features, steps, operations, elements, components, items, categories, and/or groups. The terms "or," "and/or," "including at least one of," and the like, as used herein, may be construed as inclusive, or meaning any one or any combination. For example, "including at least one of: A. b, C "means" any one of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; a and B and C ", again as examples," A, B or C "or" A, B and/or C "means" any of the following: a, A is as follows; b, a step of preparing a composite material; c, performing operation; a and B; a and C; b and C; a and B and C). An exception to this definition will occur only when a combination of elements, functions, steps or operations are in some way inherently mutually exclusive.

It should be understood that, although the steps in the flowcharts in the embodiments of the present application are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited in order and may be performed in other orders, unless explicitly stated herein. Moreover, at least some of the steps in the figures may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order of their execution not necessarily occurring in sequence, but may be performed alternately or alternately with other steps or at least a portion of the other steps or stages.

The words "if", as used herein, may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determination" or "when detected (stated condition or event)" or "in response to detection (stated condition or event), depending on the context.

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

In the following description, suffixes such as "module", "component", or "unit" for representing elements are used only for facilitating the description of the present application, and are not of specific significance per se. Thus, "module," "component," or "unit" may be used in combination.

In the prior art, a micro-processor integrated with a temperature sensor is presented, and the temperature sensor is usually integrated with an Analog-to-Digital Converter (ADC), so that a bandgap voltage proportional to absolute temperature is detected by using the Analog-to-digital converter in a voltage domain to detect temperature. Although the temperature sensor integrated in the analog-to-digital converter has advantages of high accuracy, good linearity, wide measurement temperature range, low voltage sensitivity, etc., it has disadvantages of large area and high power consumption because the analog-to-digital converter is required to detect the temperature.

In order to solve the above problems, the present application provides a digital temperature sensor, which can reduce the area of a device and reduce the power consumption of the device.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a first implementation of a digital temperature sensor according to an embodiment of the present application. The digital temperature sensor comprises a voltage controlled oscillator 10, a phase detector 20 and a counter 30; the voltage-controlled oscillator 10 is respectively connected with the phase detector 20 and the counter 30, and the phase detector 20 is also connected with the counter 30;

a voltage-controlled oscillator 10 for receiving an input voltage to generate a clock signal that varies with the input voltage; wherein the input voltage varies with temperature;

the phase detector 20 is configured to convert the clock signal generated by the voltage-controlled oscillator into a pulse signal after detecting that the clock signal reaches a preset frequency;

a counter 30 for counting the frequency of the clock signal output from the voltage-controlled oscillator and outputting a data code value corresponding to the counted value when the level state of the detection pulse signal is a first preset level; the data encoded values are used to characterize the temperature values.

Specifically, in the present embodiment, the digital temperature sensor includes a voltage-controlled oscillator 10, a phase detector 20, and a counter 30, wherein a first end of the voltage-controlled oscillator 10 is configured to receive an input voltage, so as to generate a clock signal CLK that varies with a variation of the input voltage Vctrl, and the input voltage Vctrl varies with a variation of temperature, so as to induce a frequency variation of the clock signal CLK.

The first end of the phase detector 20 is electrically connected to the second end of the voltage-controlled oscillator 10, and the phase detector 20 is configured to output the clock signal CLK reaching the preset frequency as a pulse signal, that is, the phase detector 20 detects whether the clock signal CLK generated by the voltage-controlled oscillator 10 reaches the preset frequency, if so, the clock signal CLK is converted into a pulse signal (Trigger signal), where the preset frequency is mainly set based on the accuracy of the digital temperature sensor.

The first end of the counter 30 is connected to the second end of the voltage-controlled oscillator 10, the second end of the counter 30 is connected to the second end of the phase detector 20, when the counter 30 detects that the pulse signal output by the phase detector 20 is at a first preset level (for example, a high level), the counter 30 starts counting the clock signal CLK frequency output by the voltage-controlled oscillator 10, that is, counting the number of square waves of the clock signal, so as to output a corresponding data coding value Dout according to the counted value until the pulse signal is not at the first preset level (level is pulled down), and the detected different temperature values are represented by the different data coding values Dout.

As can be seen, the digital temperature sensor in this embodiment can achieve the effect of detecting temperature only through the voltage-controlled oscillator 10, the phase detector 20 and the counter 30, and compared with the conventional temperature sensor that needs to detect temperature by using an analog-to-digital converter, the digital temperature sensor in this embodiment does not need to increase an analog-to-digital converter with larger area and higher power consumption, so that the device area of the digital temperature sensor can be reduced, and the overall power consumption can be reduced. Therefore, the method and the device can reduce the area of the device and the power consumption of the device.

Optionally, in some embodiments, the digital temperature sensor may specifically further include an input circuit, where the input circuit is connected to the first end of the voltage-controlled oscillator 10, the input voltage Vctrl is output to the voltage-controlled oscillator 10 through the input circuit, the input circuit includes a charge-discharge capacitor C1, the input voltage Vctrl is sampled through the charge-discharge capacitor C1, and the sampled voltage is output to the voltage-controlled oscillator 10.

In a specific embodiment, the charge-discharge capacitor C1 of the input circuit needs a preset charge amount to be accumulated when the charge-discharge capacitor C1 is charged to a first preset level, wherein the preset charge amount is based on the requirement of the charge-discharge capacitor C1 for subsequent discharge. Discharging the charge-discharge capacitor C1 through the voltage-controlled oscillator 10, wherein in the process of discharging the charge-discharge capacitor C1, the frequency of a clock signal CLK output by the voltage-controlled oscillator 10 decreases along with the decrease of an input voltage Vctrl, the voltage-controlled oscillator 10 inputs the output clock signal CLK to the phase detector 20 and the counter 30, and when the phase detector 30 detects that the clock signal CLK reaches a preset frequency, the clock signal CLK is output as a pulse signal and the pulse signal is output to the counter 30; when the counter 30 detects that the pulse signal is at the high level, it starts counting the frequency of the clock signal CLK output from the voltage controlled oscillator 10, and outputs the final data code Dout, and the counter 30 stops operating until the pulse signal becomes at the low level.

Optionally, in some embodiments, the input circuit may specifically further include a switching unit, where the switching unit is configured to control an amount of charge that is required to be accumulated by the charge-discharge capacitor C1 to the first preset level, and control the voltage-controlled oscillator 10 to discharge the charge-discharge capacitor C1.

Specifically, the input circuit further includes a switch unit connected to the charge-discharge capacitor C1, where the switch unit includes a first switch S1 and a second switch S2, a first end of the first switch S1 is connected to the input voltage, a second end of the first switch S1 and a first end of the second switch S2 are connected to one end of the charge-discharge capacitor C1, a second end of the second switch S2 is connected to one end of the voltage-controlled oscillator 10, and the switch unit controls, through the first switch S1 and the second switch S2, an amount of charge that needs to be accumulated when the charge-discharge capacitor C1 is charged to a first preset level, and controls the voltage-controlled oscillator 10 to discharge the charge-discharge capacitor C1.

Alternatively, in some embodiments, the phase detector 20 may be further specifically configured to switch the level state of the pulse signal to the second preset level after the discharging of the charge-discharge capacitor C1 is completed, and stop counting by the counter 30.

Specifically, the phase detector 20 in this embodiment is further configured to switch the level state of the pulse signal to a second preset level (e.g. low level) after the voltage-controlled oscillator 10 controls the charge-discharge capacitor C1 to discharge, and stop counting by the counter 30.

Optionally, as shown in fig. 2, in some embodiments, the digital temperature sensor may specifically further include a logic control unit 40, where the logic control unit 40 is connected to the voltage controlled oscillator 10, the phase detector 20, the counter 30, and the switching unit, and is configured to control a switching state of the switching unit, and control an enabling switching state of the voltage controlled oscillator 10, the phase detector 20, and the counter 30, respectively.

Specifically, in the present embodiment, the digital temperature sensor further includes a logic control unit 40 for respectively connecting with the voltage controlled oscillator 10, the phase detector 20, the counter 30, and the switching unit, where the logic control unit is configured to control the switching states of the first switch S1 and the second switch S2 of the switching unit, and control the enabled switching states of the voltage controlled oscillator 10, the phase detector 20, and the counter 30. In a specific implementation process, the logic control unit 40 controls the first switch S1 to be closed and controls the second switch S2 to be opened, and at this time, the charge-discharge capacitor C1 starts to be charged, and the charge amount required to be accumulated for charging to the first preset level is charged; then, the logic control unit 40 controls the first switch S1 to be opened and controls the second switch S2 to be closed, so that the charge-discharge capacitor C1 is discharged through the voltage-controlled oscillator 10, and the clock signal CLK output by the voltage-controlled oscillator 10 decreases along with the decrease of the input voltage Vctrl during the discharge of the charge-discharge capacitor C1. The clock signal output by the voltage-controlled oscillator 10 is input to the phase detector 20 and the counter 30, and when the phase detector 20 detects that the frequency of the clock signal reaches the preset frequency, the clock signal is output as a pulse signal; when the counter 30 detects that the pulse signal is in the first preset level state (e.g., high level), the counter 30 starts counting the frequency of the clock signal CLK output by the voltage-controlled oscillator 10, and the counter 30 outputs the final data code Dout until the pulse signal is no longer in the first preset level state (e.g., the pulse signal is changed to low level), at which time the counter 30 stops working.

Alternatively, as shown in fig. 3, in some embodiments, the logic control unit 40 may specifically include a voltage comparator, a latch, an exclusive or gate, and an nor gate electrically connected in sequence;

the voltage comparator is used for outputting a signal of a first preset level when the input voltage in the sampling process of the monitoring charge-discharge capacitor C1 reaches the reference voltage, and outputting the input voltage to the latch;

the latch is used for outputting a signal of a first preset level after receiving the input voltage and the pulse signal;

an exclusive or gate for comparing the received reference voltage with the level state of the output signal of the latch and outputting a first enable signal of a first preset level or a second preset level according to the comparison result;

and the NOT gate is used for converting the first enabling signal into the second enabling signal, and the first enabling signal and the second enabling signal are used for controlling the state of the switch unit.

In a specific embodiment, the logic control unit 40 comprises a voltage comparator, a latch, an exclusive-or gate and a not gate electrically connected in sequence, wherein the latch is preferably an SR latch. The voltage comparator is electrically connected with the charge-discharge capacitor C1 for monitoring whether the input voltage (Track voltage in FIG. 3) during the sampling process of the charge-discharge capacitor C1 reaches the reference voltage Vref, and the pulse signal (Trigger signal in FIG. 3) is low level during the capacitor sampling stage, and the exclusive OR gate in the logic control unit 40 outputs

The signal and EN signal (enable signal) respectively control the first switch S1 to be closed, and the second switch S2 to be opened, so as to control the charge amount accumulated by the charge-discharge capacitor C1 charged to the reference voltage to reach a preset value, and if the voltage comparator monitors that the input voltage in the sampling process of the charge-discharge capacitor C1 reaches the reference voltage Vref, a high level signal is output and is input to the input end (S end in fig. 3) of the latch of the next stage, so that the output level of the latch is pulled up; exclusive-OR gateThe output level of the exclusive or gate is pulled down when the output of the latch is pulled up, and the output level of the exclusive or gate is pulled down when the output of the latch is pulled up>

The signal is a low signal and the EN signal is pulled high by the NOT gate, thereby according to

The signal and the EN signal respectively control the first switch S1 to be opened, the second switch S2 to be closed, the discharge of the charge-discharge capacitor C1 is realized through the voltage-controlled oscillator 10, and the phase discriminator 20 and the counter 30 start to work at the same time, until the discharge of the charge-discharge capacitor C1 is finished, the phase discriminator 20 pulls down the level of the pulse signal and outputs the Dout signal at the same time, thus completing the temperature measurement once.

As shown in fig. 4, in the discharging process of the charge-discharge capacitor C1, the frequency of the clock signal CLK output by the voltage-controlled oscillator 10 decreases along with the decrease of the input voltage Vctrl, the clock signal CLK output by the voltage-controlled oscillator 10 is input to the phase detector 20 and the delay unit 50, and the phase detector 20 compares the clock signal CLK output by the voltage-controlled oscillator 10 with the delay clock signal clk_dly output by the delay unit 50, and when the two clock signals overlap, the phase detector 20 outputs a pulse signal (Trigger signal in fig. 4). When the pulse signal is at the high level, the counter 30 starts to count the frequency of the clock signal output by the voltage-controlled oscillator 10 until the pulse signal becomes the low level, when the pulse signal is at the low level, the counter 30 stops counting, the delay clock signal clk_dly output by the delay unit 50 and the pulse signal output by the phase detector 20 are simultaneously input to the counter 30, the pulse width of the pulse signal is calculated, so that the working duration of the counter 30 is determined according to the pulse width, the counter 30 counts the frequency of the delay clock signal in the working duration, and accordingly, a corresponding data code value Dout is output according to the count value, and different data code values Dout are used for representing different temperature values.

The latch may be an SR latch as described in the above embodiments, or may be any other suitable latch.

Optionally, as shown in fig. 4, in some embodiments, the digital temperature sensor may specifically further include a delay unit 50, where the delay unit 50 is connected to the voltage-controlled oscillator 10, the phase detector 20, and the counter 30, respectively;

the delay unit 50 is configured to receive the clock signal output by the voltage-controlled oscillator 10, convert the clock signal into a delayed clock signal, and output the delayed clock signal to the phase detector 20;

the phase detector 20 is further configured to compare the clock signal with the delayed clock signal, and output a corresponding pulse signal according to the comparison result.

Optionally, in some embodiments, the delay unit 50 may be further specifically configured to output a delayed clock signal to the counter 30, the phase detector is further configured to output a pulse signal to the counter 30, and the counter 30 is further configured to count a frequency of the delayed clock signal when a level state of the pulse signal is a first preset level, and output a corresponding data encoding value according to the count value.

Specifically, in the present embodiment, the digital temperature sensor further includes a delay unit 50 connected to the voltage-controlled oscillator 10, the phase detector 20, and the counter 30, where the delay unit 50 is configured to convert the clock signal output by the voltage-controlled oscillator 10 into a delayed clock signal, and output the delayed clock signal to the phase detector 20 and the counter 30. The clock signal output by the voltage-controlled oscillator 10 is firstly output to the phase detector 20 and the delay unit 50, the phase detector 20 compares the clock signal CLK output by the voltage-controlled oscillator 10 with the delay clock signal clk_dly output by the delay unit 50, and when the clock signal CLK and the delay clock signal clk_dly coincide, the phase detector 20 outputs a Trigger signal (Trigger signal in fig. 4), which is a pulse signal; when the trigger signal (i.e., the pulse signal) is in the first preset level state, the counter 30 starts counting the frequency of the clock signal output by the voltage-controlled oscillator 10 until the pulse signal becomes low, i.e., the first preset level state is not maintained any more, and the counter 30 stops counting. The delay clock signal output by the delay unit 50 and the pulse signal output by the phase detector 20 are input to the counter 30 at the same time, when the level of the pulse signal is the first preset level, the pulse width of the pulse signal is calculated, so that the working time of the counter 30 is determined according to the pulse width, the counter 30 counts the frequency of the delay clock signal in the working time, so that the corresponding data coding value Dout is output according to the count value, and the output data coding value Dout under different temperature conditions is also different correspondingly.

In a specific implementation process, when an input voltage Vctrl is introduced into the voltage-controlled oscillator 10 through an input circuit connected to the voltage-controlled oscillator 10, the input circuit has a charge-discharge capacitor C1, and sampling of the input voltage Vctrl is implemented through the charge-discharge capacitor C1, the charge-discharge capacitor C1 starts to be charged until the amount of charge accumulated at a first preset level reaches a preset value, where the preset value is based on meeting a subsequent discharge requirement of the charge-discharge capacitor C1; the voltage-controlled oscillator 10 discharges the charge-discharge capacitor C1, and the frequency of the clock signal CLK output from the voltage-controlled oscillator 10 decreases as the input voltage Vctrl decreases during the discharge of the charge-discharge capacitor C1. The clock signal CLK output by the voltage-controlled oscillator 10 is input to the phase detector 20 and the delay unit 50, and the phase detector 20 compares the output clock signal CLK of the voltage-controlled oscillator 10 with the delay clock signal clk_dly output by the delay unit 50, and when the two clocks are coincident, the phase detector 20 outputs a trigger signal, and the trigger signal is a pulse signal; when the pulse signal is at the high level, the counter 30 starts counting the frequency of the clock signal output from the voltage-controlled oscillator 10 until the pulse signal becomes low. The counter 30 stops counting at the time of low level. The delayed clock signal clk_dly output by the delay unit 50 and the pulse signal output by the phase detector 20 are simultaneously input to the counter 30, and the pulse width of the pulse signal is calculated, so that the working time of the counter 30 is determined according to the pulse width, and the counter 30 counts the frequency of the delayed clock signal within the working time, so that the corresponding data coding value Dout is output according to the count value.

In addition, when the input circuit is provided with the first switch S1 and the second switch S2, when the first switch S1 is closed and the second switch S2 is opened, the charge-discharge capacitor C1 is charged to the charge amount accumulated by the first preset level; when the first switch S1 is opened and the second switch S2 is closed, discharging of the charge-discharge capacitance C1 is achieved by controlling the voltage-controlled oscillator 10.

When the digital temperature sensor further includes a logic control unit 40 respectively connected to the voltage controlled oscillator 10, the phase detector 20, the counter 30, the delay unit 50, and the switching unit, the logic control unit 40 controls the open and closed states of the first switch S1 and the second switch S2 in the switching unit, and controls the enable switches of other respective modules. When the logic control unit 40 controls the first switch S1 to be closed and controls the second switch S2 to be opened, the charge amount accumulated when the charge-discharge capacitor C1 is charged to the first preset level reaches the preset value, and then the logic control unit 40 controls the first switch S1 to be opened and the second switch S2 to be closed, the charge-discharge capacitor C1 is discharged through the voltage-controlled oscillator 10, and during the discharging process of the charge-discharge capacitor C1, the frequency of the clock signal CLK output by the voltage-controlled oscillator 10 decreases along with the decrease of the input voltage Vctrl. The clock signal output from the voltage-controlled oscillator 10 is input to the phase detector 20 and the delay unit 50, and the phase detector 20 compares the output clock signal CLK of the voltage-controlled oscillator 10 with the delay clock signal clk_dly output from the delay unit 50, and when the two clock signals overlap, the phase detector 20 outputs a trigger signal (pulse signal). When the pulse signal is at the high level, the counter 30 starts counting the frequency of the clock signal output from the voltage-controlled oscillator 10 until the pulse signal becomes low, i.e., the counter 30 stops counting when the pulse signal is at the low level. The delayed clock signal clk_dly output by the delay unit 50 and the pulse signal output by the phase detector 20 are simultaneously input to the counter 30, the working time of the counter 30 is determined according to the pulse width of the signal, and the counter 30 counts the frequency of the delayed clock signal within the working time, so that a corresponding data coding value Dout is output according to the count value.

Alternatively, in some embodiments, the voltage-controlled oscillator 10 may specifically include a plurality of inverters connected in series, where an output terminal of the last inverter is connected to an input terminal of the first inverter, and a supply voltage of each inverter is the input voltage Vref. For example, as shown in fig. 5, the voltage-controlled oscillator in the present embodiment is composed of three stages of standard inverters connected in series. Because the voltage-controlled oscillator 10 in this embodiment does not additionally adopt a power supply to supply power, but directly uses the charge-discharge capacitor C1 after sampling, so that the previous sampling charge can be effectively reused, the overall power consumption of the temperature sensor can be effectively further reduced, and meanwhile, the frequency change caused by the change of the power supply voltage is effectively avoided, so that the condition that the temperature detection is inaccurate due to inaccurate counting of the frequency is avoided.

In addition to the above configuration, other adaptive voltage-controlled oscillators may be used for the voltage-controlled oscillator 10. It will be appreciated that the digital temperature sensor in the above embodiments may be a ring oscillator instead of the voltage-controlled oscillator 10, besides the voltage-controlled oscillator 10.

Optionally, in some embodiments, the step of counting the frequency of the clock signal output by the voltage-controlled oscillator 10 by the counter 30 and outputting the data code value corresponding to the counted value may specifically include:

detecting the pulse width of the pulse signal and determining the corresponding counting time length;

counting the frequency of the clock signal according to the counting time length to obtain a corresponding counting value;

and determining a corresponding data coding value according to the count value.

Specifically, for the counter 30, the pulse width of the pulse signal output by the phase detector 20 is detected first, so that the counting duration of the counter 30 is determined according to the pulse width, the counter 30 counts the frequency of the clock signal output by the voltage-controlled oscillator 10 within the counting duration, the counting mode is mainly to calculate the square wave number of the clock signal, the square wave number is related to the frequency of the clock signal, a corresponding count value is obtained, and based on a preset encoding rule, such as binary encoding, the count value is converted into a corresponding binary data encoding value, so that different temperature values are represented by the data encoding value.

As shown in fig. 6, fig. 6 provides a method of temperature measurement, comprising the steps of: in the charging process of the charge-discharge capacitor C1, judging whether the sampled input voltage is equal to the reference voltage, if so, starting to discharge the charge-discharge capacitor C1 and starting to count; if not, the charge-discharge capacitor C1 is continuously charged; judging whether the pulse signal is in a high level or not, if so, outputting a data coding value corresponding to the counting value, and continuously charging the charge-discharge capacitor C1; if not, the charge-discharge capacitor C1 continues to discharge, and the counter continues to count until the pulse signal is at the high level. The temperature measurement method is implemented in the digital temperature sensor, and receives an input voltage through the voltage-controlled oscillator 10 to generate a clock signal which varies with the input voltage; after detecting that the clock signal generated by the voltage-controlled oscillator 10 reaches a preset frequency, the phase detector 20 converts the clock signal into a pulse signal; finally, when the level state of the detection pulse signal is the first preset level, the counter 30 counts the frequency of the clock signal output by the voltage-controlled oscillator 10 and outputs a data coding value corresponding to the count value; the data encoded values are used to characterize the temperature values. In each conversion process, the charge amount of the charge-discharge capacitor C1 charged each time is fixed, after the charge amount accumulated by the charge-discharge capacitor C1 charged to the reference voltage reaches a preset value, the subsequent voltage-controlled oscillator 10 starts to discharge, and the data code value Dout is counted and output by the counter 30, when the temperature changes, the frequency of the voltage-controlled oscillator 10 changes, so that the discharge time of the charge-discharge capacitor C1 is different, the pulse width of the pulse signal is affected, the working time of the counter 30 changes, the count number of the counter 30 changes, different data code values are output under different temperature conditions, and the temperature detection can be completed without using an analog-digital converter.

The foregoing embodiments are merely examples of the present application, and are not intended to limit the scope of the patent application, so that all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, such as the combination of technical features of the embodiments, or direct or indirect application to other related technical fields, are included in the scope of the patent protection of the present application.

In addition, the present application may use the same or different reference numerals for structural elements having the same or similar characteristics. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In this application, the term "for example" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "for example" is not necessarily to be construed as preferred or advantageous over other embodiments. The previous description is provided to enable any person skilled in the art to make or use the present application. In the above description, various details are set forth for purposes of explanation.

It will be apparent to one of ordinary skill in the art that the present application may be practiced without these specific details. In other instances, well-known structures and processes have not been shown in detail to avoid unnecessarily obscuring the description of the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Claims (10)

1. A digital temperature sensor, comprising an oscillator, a phase detector and a counter; the oscillator is respectively connected with the phase detector and the counter, and the phase detector is also connected with the counter;

the oscillator is used for receiving an input voltage to generate a clock signal which varies with the input voltage; wherein the input voltage varies with temperature;

the phase discriminator is used for converting the clock signal generated by the oscillator into a pulse signal after detecting that the clock signal reaches a preset frequency;

the counter is used for counting the frequency of the clock signal output by the oscillator and outputting a data coding value corresponding to the counted value when the level state of the pulse signal is detected to be a first preset level; the data encoding values are used to characterize the temperature values.

2. The digital temperature sensor of claim 1, further comprising an input circuit comprising a charge-discharge capacitor for sampling the input voltage and outputting a sampled voltage to the oscillator.

3. The digital temperature sensor of claim 2, wherein the input circuit further comprises a switching unit for controlling an amount of charge that the charge-discharge capacitor needs to accumulate to charge to the first preset level, and controlling the oscillator to discharge the charge-discharge capacitor.

4. The digital temperature sensor according to claim 3, wherein the phase detector is further configured to switch the level state of the pulse signal to a second preset level after the charge-discharge capacitor is discharged, and stop counting by the counter.

5. The digital temperature sensor of claim 4, further comprising a logic control unit respectively coupled to the oscillator, the phase detector, the counter, and the switching unit for controlling a switching state of the switching unit and for controlling an enabling switching state of the oscillator, the phase detector, and the counter.

6. The digital temperature sensor according to any one of claims 1 to 5, further comprising a delay unit connected to the oscillator, phase detector and counter, respectively;

the delay unit is used for receiving the clock signal output by the oscillator, converting the clock signal into a delay clock signal and outputting the delay clock signal to the phase discriminator;

the phase discriminator is also used for comparing the clock signal with the delay clock signal and outputting a corresponding pulse signal according to the comparison result.

7. The digital temperature sensor according to claim 6, wherein the delay unit is further configured to output the delay clock signal to the counter, the phase detector is further configured to output the pulse signal to the counter, and the counter is further configured to count a frequency of the delay clock signal when a level state of the pulse signal is the first preset level, and output a corresponding data encoding value according to the count value.

8. The digital temperature sensor of claim 1, wherein the oscillator comprises a plurality of series-connected inverters, wherein an output of a last inverter is connected to an input of a first inverter, and wherein a supply voltage of each inverter is the input voltage.

9. The digital temperature sensor of claim 5, wherein the logic control unit comprises a voltage comparator, a latch, an exclusive or gate, and an nor gate electrically connected in sequence;

the voltage comparator is used for outputting a signal of a first preset level when the input voltage in the process of monitoring the charge-discharge capacitor sampling reaches a reference voltage, and outputting the input voltage to the latch;

the latch is used for outputting the signal of the first preset level after receiving the input voltage and the pulse signal;

the exclusive-OR gate is used for comparing the received reference voltage with the level state of the output signal of the latch and outputting a first enabling signal of a first preset level or a second preset level according to the comparison result;

and the NOT gate is used for converting the first enabling signal into a second enabling signal, and the first enabling signal and the second enabling signal are used for controlling the state of the switch unit.

10. The digital temperature sensor according to claim 1, wherein the counting the frequency of the clock signal output from the oscillator and outputting the data code value corresponding to the counted value comprises:

detecting the pulse width of the pulse signal and determining the corresponding counting time length;

counting the frequency of the clock signal according to the counting time length to obtain a corresponding counting value;

and determining a corresponding data coding value according to the counting value.

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