CN115996579A - SOT-MRAM and manufacturing method thereof - Google Patents

SOT-MRAM and manufacturing method thereof Download PDF

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Publication number
CN115996579A
CN115996579A CN202111206785.4A CN202111206785A CN115996579A CN 115996579 A CN115996579 A CN 115996579A CN 202111206785 A CN202111206785 A CN 202111206785A CN 115996579 A CN115996579 A CN 115996579A
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layer
insulating layer
sot
magnetic tunnel
tunnel junction
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毕冲
娄凯华
刘明
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN202111206785.4A priority Critical patent/CN115996579A/en
Priority to PCT/CN2021/124434 priority patent/WO2023060627A1/en
Publication of CN115996579A publication Critical patent/CN115996579A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N52/00—Hall-effect devices
    • H10N52/01—Manufacture or treatment

Abstract

The invention provides an SOT-MRAM and a manufacturing method thereof. Each memory cell includes an SOT layer deposited on a substrate, a magnetic tunnel junction disposed on the SOT layer. An antiferromagnetic insulating layer surrounding at least the sides of the free layer in each magnetic tunnel junction is also included, and the direction of the magnetic moment of the antiferromagnetic insulating layer is parallel to the direction of the write current in the SOT layer. By additionally arranging an antiferromagnetic insulating layer which at least surrounds the side surface of the free layer in each magnetic tunnel junction on the side surface of each magnetic tunnel junction and enabling the magnetic moment direction of the antiferromagnetic insulating layer to be parallel to the direction of writing current, an in-plane magnetic field can be provided for the free layer, so that the SOT-MRAM can be turned over without an external magnetic field, and the problem that SOT-MRAM cannot be integrated on a large scale due to the fact that an external magnetic field needs to be applied in the writing process is solved. The added antiferromagnetic insulating layer is arranged around the magnetic tunnel junction, so that the magnetic tunnel junction is protected from the surrounding environment.

Description

SOT-MRAM and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductors, in particular to an SOT-MRAM and a manufacturing method thereof.
Background
Magnetic Random Access Memory (MRAM) is one of the most promising memory technologies in new types of memory, and is expected to replace Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). The core structure of MRAM is a Magnetic Tunnel Junction (MTJ) structure, which is composed of a sandwich structure of two ferromagnetic layers and one tunneling layer. Of the two ferromagnetic layers, one whose magnetization can be reversed by electric current or magnetic field is called the free layer; the magnetization of the other layer remains unchanged all the time, called the reference layer (fixed layer). When the magnetization directions of the free layer and the reference layer are parallel, the MTJ is in a low resistance state; when they are antiparallel, the MTJ is then in a high resistance state. The high and low resistance states may be used to store data "0" and "1". MRAM is classified into STT type and SOT type according to the difference of read/write modes. The SOT-MRAM read-write path is separated, the write time can reach 0.5ns, and the SOT-MRAM read-write path is superior to the STT-MRAM in the aspects of device reliability, stability, read-write speed and the like. However, a key problem faced by SOT-MRAM in applications is the need to apply an external magnetic field to determine the magnetization direction of SOT-MRAM. Since the external magnetic field cannot be integrated into the chip in a large scale, SOT-MRAM faces a critical technical problem in practical application.
To solve the problem of non-external magnetic field inversion of SOT-MRAM, various alternatives to external magnetic fields have been proposed in academia and industry, mainly including inducing a gradient of magnetic anisotropy in-plane, inducing an in-plane Exchange-coupled (Exchange) magnetic field and Dipole (Dipole) magnetic field by interfacial coupling of ferromagnetic or antiferromagnetic multilayers, and growing another ferromagnetic layer on the other side of the free layer to provide an additional external magnetic field. The creation of in-plane magnetic anisotropy gradients is not useful for large scale integration because of the need to induce non-uniformities in the free layer in-plane of the structure or material composition. And an external magnetic field is induced by means of interface coupling of ferromagnetic or antiferromagnetic multilayer films, which need to be in close contact with the SOT layer. Since the resistance of these multilayer films is much lower than that of the SOT layer, most of the write current is shunted into these multilayer films, reducing the write efficiency of the SOT layer and increasing the write power consumption. In addition, since the in-plane magnetic anisotropy of these ferromagnetic multilayer films is not strong enough, these ferromagnetic layers themselves face the problem of thermal stability, and thus this solution of SOT without external field inversion faces the problem of low data stability and retention capability.
Disclosure of Invention
The invention provides an SOT-MRAM and a manufacturing method thereof, which are used for solving the problem that the SOT-MRAM cannot be integrated on a large scale because an external magnetic field needs to be applied in the writing process.
In a first aspect, the present invention provides an SOT-MRAM including a substrate, and a plurality of memory cells disposed on the substrate. Each memory cell includes an SOT layer deposited on a substrate for passing a write current, and a magnetic tunnel junction disposed on the SOT layer, wherein the magnetic tunnel junction includes: a free layer deposited on the SOT layer, an insulating layer laminated on the free layer, and a reference layer laminated on the insulating layer. The SOT-MRAM further includes an antiferromagnetic insulating layer surrounding at least the sides of the free layer in each magnetic tunnel junction, and the antiferromagnetic insulating layer has a magnetic moment parallel to the direction of the write current in the SOT layer.
In the scheme, the anti-ferromagnetic insulating layer which at least surrounds the side surface of the free layer in each magnetic tunnel junction is additionally arranged on the side surface of each magnetic tunnel junction, and the magnetic moment direction of the anti-ferromagnetic insulating layer is parallel to the direction of write current, so that an in-plane magnetic field can be provided for the free layer, and the free layer can be used for the non-external magnetic field inversion of the SOT-MRAM, so that the problem that the SOT-MRAM cannot be integrated on a large scale due to the fact that an external magnetic field needs to be applied in the writing process is solved. The added antiferromagnetic insulating layer is arranged around the magnetic tunnel junction, so that the magnetic tunnel junction is protected from the surrounding environment.
In a specific embodiment, the antiferromagnetic insulating layer wraps at least all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction. The anti-ferromagnetic insulating layer is increased in height, machining difficulty is reduced, and meanwhile the magnetic tunnel junction is better protected from being influenced by the surrounding environment.
In one particular embodiment, the antiferromagnetic insulating layer fills the space between adjacent magnetic tunnel junctions in the plurality of memory cells. The processing difficulty is reduced, and the magnetic tunnel junction is better protected from the surrounding environment.
In a specific embodiment, the material of the antiferromagnetic insulating layer is any one of CoFeB oxide, coOx, feOx, niOx, crOx, mnOx, coFe2O4, or a mixture or alloy made of any of several materials.
In one embodiment, the antiferromagnetic insulating layer surrounds each magnetic tunnel junction with a thickness of at least 0.5 nm to reduce manufacturing difficulties while providing an in-plane magnetic field that is sufficiently stable and reliable.
In a second aspect, the present invention also provides a method for fabricating a SOT-MRAM, the method comprising:
providing a substrate;
providing a plurality of memory cells on a substrate, comprising: depositing a plurality of SOT layers for passing a write current on a substrate; forming a magnetic tunnel junction on each SOT layer, wherein the magnetic tunnel junction comprises: a free layer deposited on the SOT layer, an insulating layer laminated on the free layer, and a reference layer laminated on the insulating layer;
forming an antiferromagnetic insulating layer surrounding at least the sides of the free layer in each magnetic tunnel junction;
the magnetic moment direction of the antiferromagnetic insulating layer is adjusted so that the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current.
In the scheme, the anti-ferromagnetic insulating layer which at least surrounds the side surface of the free layer in each magnetic tunnel junction is additionally arranged on the side surface of each magnetic tunnel junction, and the magnetic moment direction of the anti-ferromagnetic insulating layer is parallel to the direction of write current, so that an in-plane magnetic field can be provided for the free layer, and the free layer can be used for the non-external magnetic field inversion of the SOT-MRAM, so that the problem that the SOT-MRAM cannot be integrated on a large scale due to the fact that an external magnetic field needs to be applied in the writing process is solved. The added antiferromagnetic insulating layer is arranged around the magnetic tunnel junction, so that the magnetic tunnel junction is protected from the surrounding environment.
In a specific embodiment, forming an antiferromagnetic insulating layer surrounding at least the sides of the free layer in each magnetic tunnel junction comprises: and (3) adopting a sputtering process to enable the incidence angle between sputtered ions and the surface of the substrate to be in the range of more than 0 degrees and less than 90 degrees, and growing anti-ferromagnetic insulating materials on all sides of the free layer, the insulating layer and the reference layer in each magnetic tunnel junction so as to form the anti-ferromagnetic insulating layer which surrounds all sides of the free layer, the insulating layer and the reference layer in each magnetic tunnel junction. The anti-ferromagnetic insulating material layer is formed on all sides of the magnetic tunnel junction conveniently by increasing the height of the anti-ferromagnetic insulating layer, so that the processing difficulty is reduced, and the magnetic tunnel junction is better protected from the surrounding environment.
In a specific embodiment, forming the antiferromagnetic insulating layer around at least the sides of the free layer in each magnetic tunnel junction further comprises: and adopting a vertical sputtering process to continuously fill the antiferromagnetic insulating material or other insulating materials between the adjacent antiferromagnetic insulating layers so as to fill the space between the adjacent magnetic tunnel junctions. The processing difficulty is reduced, and the magnetic tunnel junction is better protected from the surrounding environment.
In a specific embodiment, forming a magnetic tunnel junction on each SOT layer and forming an antiferromagnetic insulating layer surrounding at least the free layer sides in each magnetic tunnel junction includes:
filling a dielectric material between adjacent SOT layers on the substrate to form dielectric layers;
depositing a free material layer on the SOT layer and the dielectric layer;
depositing a layer of insulating material over the free material layer;
depositing a reference material layer on the insulating material layer;
covering a layer of photoresist on the reference material layer;
performing photoetching pattern exposure, and reserving photoresist above each magnetic tunnel junction;
and oxidizing the ferromagnetic materials which are not protected by the photoresist in the reference material layer and the free material layer into antiferromagnetic materials by adopting a plasma oxidation process so as to form magnetic tunnel junctions below the reserved photoresist and form antiferromagnetic insulating layers which fill the spaces between adjacent magnetic tunnel junctions in the plurality of memory cells. The method is convenient for processing the magnetic tunnel junction and the antiferromagnetic insulating layer at the same time, and does not need to carry out patterning etching in the process of manufacturing the magnetic tunnel junction, thereby avoiding the process of precisely controlling the etching depth to the SOT layer in the process of large-scale integration of SOT-MRAM, and further avoiding the phenomenon of greatly changing the device performance caused by a small amount of over-etching of the SOT layer.
In a specific embodiment, adjusting the magnetic moment direction of the antiferromagnetic insulating layer such that the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current comprises: vacuum annealing the antiferromagnetic insulating layer with the application of an external magnetic field; wherein the annealing temperature is higher than the Neel temperature of the antiferromagnetic insulating layer material, and the direction of the external magnetic field is parallel to the direction of the write current in the SOT layer. So as to adjust the magnetic moment direction of the antiferromagnetic insulating layer to be parallel to the direction of the write current in the SOT layer.
In a specific embodiment, the manufacturing method further includes, before vacuum annealing the antiferromagnetic insulating layer: an upper electrode is formed over each magnetic tunnel junction to form an upper electrode prior to vacuum annealing, preventing oxidation of the reference layer surface during annealing.
Drawings
FIG. 1 is a schematic diagram of an SOT-MRAM according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a single memory cell in an SOT-MRAM according to an embodiment of the invention;
FIG. 3 is a schematic illustration of an antiferromagnetic insulating layer sputtered on a side of a magnetic tunnel junction according to an embodiment of the invention;
FIG. 4 is a schematic diagram of an embodiment of the present invention after exposure to a lithographic pattern during SOT-MRAM fabrication by oxidation;
FIG. 5 is a schematic diagram showing the oxidation degree after plasma oxidation in the SOT-MRAM fabrication by oxidation according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a structure for forming a Hall rod in an SOT-MRAM test structure according to an embodiment of the present invention;
FIG. 7 is a schematic structural view of a magnetic tunnel junction fabricated at the center of the Hall bar shown in FIG. 6;
FIG. 8 is a schematic diagram of a sample and test of a single memory cell on an SOT-MRAM according to an embodiment of the invention.
Reference numerals:
10-substrate 11-SOT layer 111-transverse Hall rod 112-longitudinal Hall rod
12-magnetic tunnel junction 13-antiferromagnetic insulating layer 14-dielectric layer 15-photoresist
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to facilitate understanding of the SOT-MRAM provided by the embodiments of the present invention, an application scenario of the SOT-MRAM provided by the embodiments of the present invention will be described below, where the SOT-MRAM is used as a memory and applied to a server or other devices. The SOT-MRAM is described in detail below with reference to the accompanying drawings.
Referring to fig. 1, 2 and 3, the SOT-MRAM according to the present invention includes a substrate 10 and a plurality of memory cells disposed on the substrate 10. Each memory cell includes an SOT layer 11 deposited on a substrate 10 for passing a write current, and a magnetic tunnel junction 12 disposed on the SOT layer 11, wherein the magnetic tunnel junction 12 includes: a free layer deposited on the SOT layer 11, an insulating layer laminated on the free layer, and a reference layer laminated on the insulating layer. The SOT-MRAM also includes an antiferromagnetic insulating layer 13 surrounding at least the free layer sides in each magnetic tunnel junction 12, and the antiferromagnetic insulating layer 13 has a magnetic moment oriented parallel to the direction of the write current in the SOT layer 11.
In the above-mentioned scheme, by adding the antiferromagnetic insulating layer 13 around at least the side surface of the free layer in each magnetic tunnel junction 12 and making the magnetic moment direction of the antiferromagnetic insulating layer 13 parallel to the direction of the write current, an in-plane magnetic field can be provided for the free layer for the non-external magnetic field inversion of the SOT-MRAM, so as to solve the problem that the SOT-MRAM cannot be integrated on a large scale due to the application of an external magnetic field in the writing process. And the added antiferromagnetic insulating layer 13 is arranged around the magnetic tunnel junction 12, so that the magnetic tunnel junction 12 is protected from the surrounding environment. The following describes each of the above structures in detail with reference to the accompanying drawings.
In providing the substrate 10, the substrate 10 serves as a carrier structure for all memory cells, and may be made of silicon dioxide or the like, on which a word line structure, a bit line structure, or the like may have been integrally provided.
Referring to fig. 1, 2 and 3, a plurality of memory cells are provided on a substrate 10, each memory cell including an SOT layer 11 deposited on the substrate 10, and a magnetic tunnel junction 12 provided on the SOT layer 11. The magnetic tunnel junction 12 is a sandwich-like layered structure comprising, in order, a free layer deposited on the SOT layer 11, an insulating layer layered on the free layer, and a reference layer layered on the insulating layer. The material of the SOT layer 11 may be a metal layer with spin hall effect, a topological material layer, or other materials with spin orbit coupling effect, and one metal or an alloy formed by a combination of several metals of the metals Pt, ta, W, mo, au, al, biSe, irMn may be used as the material of the SOT layer 11. The SOT layer 11 is used to pass a write current to cause the magnetization direction of the free layer in the magnetic tunnel junction 12 to be flipped. A plurality of memory cells may be formed on the substrate 10 in an array arrangement to form a memory array. The free layer and the reference layer are made of homogeneous ferromagnetic material, and in particular, metal Fe, co, ni, coFeB or any combination of metal and alloy can be used as the free layer and the reference layer. Wherein the material of the insulating layer can be goldThe metal oxide may be, for example, alO x 、MgO、SiO 2 、HfO x And the like as the material of the insulating layer in the magnetic tunnel junction 12.
Referring to fig. 1 and 3, the SOT-MRAM further includes an antiferromagnetic insulating layer 13 surrounding at least the free layer sides of each magnetic tunnel junction 12. I.e. the antiferromagnetic insulating layer 13 surrounds at least the sides of the free layer in each magnetic tunnel junction 12, so that the antiferromagnetic insulating layer 13 has the effect of protecting the magnetic tunnel junction 12 from the surrounding environment by virtue of its positional properties disposed around the magnetic tunnel junction 12. In particular, when antiferromagnetic insulating layer 13 is provided, antiferromagnetic insulating layer 13 may wrap around only the sides of the free layer in each magnetic tunnel junction 12, and not the sides of the insulating layer and reference layer of each magnetic tunnel junction 12. It is also possible to wrap around only the sides of the free and insulating layers in each magnetic tunnel junction 12, and not the sides of the reference layer of each magnetic tunnel junction 12. Referring to fig. 1 and 3, all sides of the free layer, the insulating layer, and the reference layer in each magnetic tunnel junction 12 may be further wrapped around to increase the height of the antiferromagnetic insulating layer 13, reduce the processing difficulty, and better protect the magnetic tunnel junction 12 from the surrounding environment. It should be noted that the antiferromagnetic insulating layer 13 surrounds each magnetic tunnel junction 12 with a thickness of at least 0.5 nm to reduce manufacturing difficulties while providing an in-plane magnetic field that is sufficiently stable and reliable as provided by the antiferromagnetic insulating layer 13. Specifically, the antiferromagnetic insulating layer 13 may have a thickness of 0.5 nm, 1nm, 10 nm, 100nm, 1 micron, 10 microns, 100 microns, 300 microns, 500 microns, etc. around the sides of each magnetic tunnel junction 12, no thinner than any value of 0.5 nm. Of course, the antiferromagnetic insulating layer 13 may further fill the space between adjacent magnetic tunnel junctions 12 in the plurality of memory cells, i.e., the antiferromagnetic insulating material is filled between adjacent magnetic tunnel junctions 12, and the antiferromagnetic insulating layer 13 is formed to replace the dielectric layer between adjacent magnetic tunnel junctions 12. To reduce processing difficulties while better protecting magnetic tunnel junction 12 from the surrounding environment.
In addition, it is also necessary to adjust the magnetic moment direction of the antiferromagnetic insulating layer 13 so that the magnetic moment direction of the antiferromagnetic insulating layer 13 is parallel to the direction of the write current in the SOT layer 11. Specifically, the magnetic moment direction of the antiferromagnetic insulating layer 13 may be the same as the direction of the write current in the SOT layer 11, or the magnetic moment direction of the antiferromagnetic insulating layer 13 may be opposite to the direction of the write current in the SOT layer 11, so as to provide an in-plane magnetic field for the free layer, and the free layer is used for the non-external magnetic field inversion of the SOT-MRAM, so as to solve the problem that the SOT-MRAM cannot be integrated on a large scale due to the application of an external magnetic field in the writing process.
In determining the material of the antiferromagnetic insulating layer 13, the material of the antiferromagnetic insulating layer 13 may be any one of oxide of CoFeB, coOx, feOx, niOx, crOx, mnOx, coFe O4, or a mixture or alloy made of any of several materials.
By adding an antiferromagnetic insulating layer 13 around at least the side of the free layer in each magnetic tunnel junction 12 and making the magnetic moment direction of the antiferromagnetic insulating layer 13 parallel to the direction of the write current, an in-plane magnetic field can be provided to the free layer for the non-external magnetic field inversion of the SOT-MRAM, so as to solve the problem that the SOT-MRAM cannot be integrated on a large scale due to the application of an external magnetic field during the writing process. And the added antiferromagnetic insulating layer 13 is arranged around the magnetic tunnel junction 12, so that the magnetic tunnel junction 12 is protected from the surrounding environment.
In addition, the embodiment of the invention also provides a manufacturing method of the SOT-MRAM, referring to fig. 1 to 5, the manufacturing method comprises the following steps:
providing a substrate 10;
a plurality of memory cells are provided on the substrate 10, comprising: depositing a plurality of SOT layers 11 for passing a write current on a substrate 10; a magnetic tunnel junction 12 is formed on each SOT layer 11, wherein the magnetic tunnel junction 12 includes: a free layer deposited on the SOT layer 11, an insulating layer laminated on the free layer, and a reference layer laminated on the insulating layer;
forming an antiferromagnetic insulating layer 13 surrounding at least the free layer sides in each magnetic tunnel junction 12;
the magnetic moment direction of the antiferromagnetic insulating layer 13 is adjusted so that the magnetic moment direction of the antiferromagnetic insulating layer 13 is parallel to the direction of the write current.
In the above-mentioned scheme, by adding the antiferromagnetic insulating layer 13 around at least the side surface of the free layer in each magnetic tunnel junction 12 and making the magnetic moment direction of the antiferromagnetic insulating layer 13 parallel to the direction of the write current, an in-plane magnetic field can be provided for the free layer for the non-external magnetic field inversion of the SOT-MRAM, so as to solve the problem that the SOT-MRAM cannot be integrated on a large scale due to the application of an external magnetic field in the writing process. And the added antiferromagnetic insulating layer 13 is arranged around the magnetic tunnel junction 12, so that the magnetic tunnel junction 12 is protected from the surrounding environment. It should be noted that the above steps are not limited to the order, i.e., the steps may be adjusted to prepare any one of the SOT-MRAM. Each of the above steps is described in detail below with reference to the accompanying drawings.
First, referring to fig. 2, a substrate 10 is provided, and the substrate 10 serves as a carrier structure for all memory cells, and may be made of silicon dioxide or the like, on which a word line structure, a bit line structure, or the like may have been integrally provided.
Next, with continued reference to fig. 2, a plurality of memory cells are disposed on the substrate 10. In the case of providing a plurality of memory cells, a plurality of SOT layers 11 for passing a write current are first deposited on a substrate 10. Thereafter, a magnetic tunnel junction 12 is formed on each SOT layer 11, and the magnetic tunnel junction 12 is a sandwich-like layered structure including, in order, a free layer deposited on the SOT layer 11, an insulating layer layered on the free layer, and a reference layer layered on the insulating layer. The material of the SOT layer 11 may be a metal layer with spin hall effect, a topological material layer, or other materials with spin orbit coupling effect, and one metal or an alloy formed by a combination of several metals of the metals Pt, ta, W, mo, au, al, biSe, irMn may be used as the material of the SOT layer 11. The SOT layer 11 is used to pass a write current to cause the magnetization direction of the free layer in the magnetic tunnel junction 12 to be flipped. A plurality of memory cells may be formed on the substrate 10 in an array arrangement,to form a memory array. The free layer and the reference layer are made of homogeneous ferromagnetic material, and in particular, metal Fe, co, ni, coFeB or any combination of metal and alloy can be used as the free layer and the reference layer. Wherein the material of the insulating layer can be metal oxide, such as AlO x 、MgO、SiO 2 、HfO x And the like as the material of the insulating layer in the magnetic tunnel junction 12.
Next, referring to fig. 1 and 3, an antiferromagnetic insulating layer 13 surrounding at least the free layer sides in each magnetic tunnel junction 12 is formed. That is, the antiferromagnetic insulating layer 13 surrounds at least the side surface of the free layer in each magnetic tunnel junction 12, so that the antiferromagnetic insulating layer 13 has the function of protecting the magnetic tunnel junction 12 from the surrounding environment by utilizing the positional characteristics of its placement around the magnetic tunnel junction 12. In particular, when wrapping around, the antiferromagnetic insulating layer 13 may wrap around only the sides of the free layer in each magnetic tunnel junction 12, and not around the sides of the insulating layer and reference layer of each magnetic tunnel junction 12. It is also possible to wrap around only the sides of the free and insulating layers in each magnetic tunnel junction 12, and not the sides of the reference layer of each magnetic tunnel junction 12. All sides of the free layer, insulating layer and reference layer in each magnetic tunnel junction 12 may also be wrapped around to increase the height of the antiferromagnetic insulating layer 13, reduce processing difficulty, and better protect the magnetic tunnel junction 12 from the surrounding environment. It should be noted that the antiferromagnetic insulating layer 13 surrounds each magnetic tunnel junction 12 with a thickness of at least 0.5 nm to reduce manufacturing difficulties while providing an in-plane magnetic field that is sufficiently stable and reliable as provided by the antiferromagnetic insulating layer 13. Specifically, the antiferromagnetic insulating layer 13 may have a thickness of 0.5 nm, 1nm, 10 nm, 100nm, 1 micron, 10 microns, 100 microns, 300 microns, 500 microns, etc. around the sides of each magnetic tunnel junction 12, no thinner than any value of 0.5 nm. Of course, the antiferromagnetic insulating layer 13 may further fill the space between adjacent magnetic tunnel junctions 12 in the plurality of memory cells, i.e., the antiferromagnetic insulating material is filled between adjacent magnetic tunnel junctions 12, and the antiferromagnetic insulating layer 13 is formed to replace the dielectric layer between adjacent magnetic tunnel junctions 12. To reduce processing difficulties while better protecting magnetic tunnel junction 12 from the surrounding environment.
In particular, the antiferromagnetic insulating layer 13 may be formed in various ways. Two ways of forming the antiferromagnetic insulating layer 13 by sputtering and oxidation are described below.
First, the antiferromagnetic insulating layer 13 may be formed using a sputtering process, which is a process commonly used in conventional MRAM fabrication. At this time, before the antiferromagnetic insulating layer 13 is formed, the SOT layer 11 and the magnetic tunnel junction 12 as shown in fig. 2 have been processed, that is, the SOT layer 11 and the magnetic tunnel junction 12 are formed on the substrate 10 by patterning etching, specifically, a multi-layer film of the magnetic tunnel junction 12 may be sequentially grown on the substrate 10, and then the magnetic tunnel junction 12 is patterned by photolithography exposure and ion etching, and the etching depth is as deep as the SOT layer 11, to form the SOT layer 11 and the magnetic tunnel junction 12 as shown in fig. 2. After that, the antiferromagnetic insulating layer 13 is formed by using a sputtering process, that is, after the etching of the magnetic tunnel junction 12 is completed, the antiferromagnetic insulating material is grown on the side surface of the magnetic tunnel junction 12 instead of the normal insulating material, so that the formed antiferromagnetic insulating material serves as a filler to protect the magnetic tunnel junction 12. It is desirable in this process to have antiferromagnetic insulating layer 13 wrap around all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction 12, i.e., antiferromagnetic insulating layer 13 wraps around all sides of each magnetic tunnel junction 12.
In forming the antiferromagnetic insulating layer 13 around at least the sides of the free layer in each magnetic tunnel junction 12, a sputtering process may be used to cause the angle of incidence between sputtered ions and the surface of the substrate 10 to be in the range of greater than 0 degrees and less than 90 degrees, and the antiferromagnetic insulating material is grown on all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction 12 to form the antiferromagnetic insulating layer 13 around all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction 12. That is, by sputtering, an antiferromagnetic insulating layer 13 is grown around the patterned magnetic tunnel junction 12, and the angle of incidence of the sputtered ions with the surface of the substrate 10 is between 0 degrees and 90 degrees. The antiferromagnetic insulating material may be any one of CoFeB oxide, coOx, feOx, niOx, crOx, mnOx, coFe2O4, or a mixture or alloy made of any of several materials. In addition, by forming the antiferromagnetic insulating material layer around all sides of each magnetic tunnel junction 12 by the incidence angle between the sputtered ions and the surface of the substrate 10 in the range of 1 degree, 10 degrees, 20 degrees, 30 degrees, 40 degrees, 50 degrees, 60 degrees, 70 degrees, 80 degrees, 89 degrees, etc., more than 0 degrees and less than 90 degrees, the process difficulty is reduced while better protecting the magnetic tunnel junction 12 from the surrounding environment by increasing the height of the antiferromagnetic insulating layer 13. In addition, the thickness of the antiferromagnetic insulating layer 13 grown on the side of the magnetic tunnel junction 12 by the sputtering process is preferably greater than 1nm, ensuring that the antiferromagnetic insulating layer 13 is sufficiently thick on the side of the magnetic tunnel junction 12.
Thereafter, the vertical sputtering process may be further employed to continue to fill the space between adjacent antiferromagnetic insulating layers 13 with antiferromagnetic insulating material or other insulating material to fill the space between adjacent magnetic tunnel junctions 12. Specifically, a vertical sputtering process may be further adopted to fill the antiferromagnetic insulating material between the adjacent antiferromagnetic insulating layers 13, so that the finally formed antiferromagnetic insulating layers 13 fill the space between the adjacent magnetic tunnel junctions 12, so that the finally formed antiferromagnetic insulating layers 13 replace the dielectric layer between the adjacent magnetic tunnel junctions 12, thereby reducing the processing difficulty and better protecting the magnetic tunnel junctions 12 from the surrounding environment. Of course, a vertical sputtering process may be further used to fill the adjacent antiferromagnetic insulating layers 13 with other types of insulating materials besides antiferromagnetic insulating materials, so as to fill the dielectric material between the adjacent antiferromagnetic insulating materials to form a dielectric layer.
Next, a manner of forming the antiferromagnetic insulating layer 13 by oxidation will be described. In this process, it is necessary to have antiferromagnetic insulating layer 13 fill the space between adjacent magnetic tunnel junctions 12 in the plurality of memory cells. In addition, in this process, the formation of the magnetic tunnel junction 12 and the antiferromagnetic insulating layer 13 on each SOT layer 11 are simultaneously formed, so that the order of steps in the foregoing method needs to be adjusted. The SOT layer 11 has been formed on the substrate 10 before the antiferromagnetic insulating layer 13 is formed by oxidation, i.e. the SOT layer 11 has been formed on the substrate 10 by patterning etching.
In particular, in forming a magnetic tunnel junction 12 on each SOT layer 11 and an antiferromagnetic insulating layer 13 surrounding at least the free layer sides of each magnetic tunnel junction 12, referring to FIG. 4, it is first necessary to fill the dielectric material between adjacent SOT layers 11 on the substrate 10 to form a dielectric layer 14 to form a planar end surface over the SOT layers 11. Then, as shown in fig. 4, a free material layer is deposited on the SOT layer 11 and the dielectric layer 14, that is, a ferromagnetic material is deposited on the SOT layer 11 and the dielectric layer 14 as a material layer for forming a free layer later. Next, a layer of insulating material is deposited on the free material layer, i.e. an insulating material is deposited on the free material layer as a material layer for the subsequent formation of the insulating layer. Next, a reference material layer is deposited on the insulating material layer, i.e. a ferromagnetic material is deposited on the insulating material layer as a material layer for the subsequent formation of the reference layer. Thereafter, a layer of photoresist is coated over the reference material layer, and the pattern of the magnetic tunnel junction 12 is subsequently transferred to the photoresist by photolithographic exposure. Thereafter, referring to fig. 4, a photolithographic pattern exposure is performed, leaving a photoresist 15 over each magnetic tunnel junction 12, i.e., the region where the magnetic tunnel junction 12 is to be formed, below the photoresist 15 left over the surface of the reference material layer. Thereafter, referring to fig. 5, a plasma oxidation process is used to oxidize the ferromagnetic material of the reference material layer and the free material layer, which is not protected by the photoresist 15, to an antiferromagnetic material to form magnetic tunnel junctions 12 under the remaining photoresist 15 and to form antiferromagnetic insulating layers 13 filling the spaces between adjacent magnetic tunnel junctions 12 in the plurality of memory cells. I.e. by plasma oxidation, the ferromagnetic material layers in the magnetic tunnel junction 12, in particular the free material layer and the reference material layer, are oxidized where they are not protected by the photoresist 15. The free material layer and the reference material layer above the SOT layer 11 are all oxidized by controlling the oxidation time, as shown in fig. 5. At this time, the oxide layer of the ferromagnetic material layer at the uncovered area of the photoresist 15 serves as the antiferromagnetic insulating layer 13 shown in fig. 1. Thereafter, the remaining photoresist 15 is removed to facilitate the simultaneous processing of the magnetic tunnel junction 12 and the antiferromagnetic insulating layer 13 without the need for patterned etching during the fabrication of the magnetic tunnel junction 12, thereby avoiding the need for precisely controlling the etching depth to the SOT layer 11 during SOT-MRAM mass integration. In addition, the SOT layer 11 is usually only 3-8 nanometers, even a small amount of over etching can cause a great change of the device performance, and if no patterning etching is performed in the process of manufacturing the magnetic tunnel junction 12, the phenomenon of great change of the device performance caused by a small amount of over etching of the SOT layer 11 is avoided.
Next, it is necessary to adjust the magnetic moment direction of the antiferromagnetic insulating layer 13 so that the magnetic moment direction of the antiferromagnetic insulating layer 13 is parallel to the direction of the write current. Specifically, the magnetic moment direction of the antiferromagnetic insulating layer 13 may be the same as the direction of the write current in the SOT layer 11, or the magnetic moment direction of the antiferromagnetic insulating layer 13 may be opposite to the direction of the write current in the SOT layer 11, so as to provide an in-plane magnetic field for the free layer, and the free layer is used for the non-external magnetic field inversion of the SOT-MRAM, so as to solve the problem that the SOT-MRAM cannot be integrated on a large scale due to the application of an external magnetic field in the writing process.
In particular, when the magnetic moment direction of the antiferromagnetic insulating layer 13 is adjusted, the antiferromagnetic insulating layer 13 may be vacuum annealed with an external magnetic field applied, and the magnetic moment direction of the antiferromagnetic insulating layer 13 may be adjusted by adjusting the annealing temperature and the direction of the external magnetic field. Specifically, the annealing temperature needs to be adjusted to be higher than the ear temperature of the antiferromagnetic insulating layer 13 material to change the diamagnetic material into the paramagnetic material. The direction of the external magnetic field is also parallel to the direction of the write current in the SOT layer 11, specifically, the direction of the external magnetic field may be the same as the direction of the write current in the SOT layer 11 or may be opposite to the direction of the write current in the SOT layer 11, so that the magnetic moment direction in the antiferromagnetic insulating layer 13 is guided to be the same parallel to the direction of the write current in the SOT layer 11, so as to provide an in-plane magnetic field to the free layer for non-external magnetic field inversion of the SOT-MRAM. And the external magnetic field is applied all the way through the annealing process until the antiferromagnetic insulating layer 13 is cooled to room temperature, so as to adjust the magnetic moment direction of the antiferromagnetic insulating layer 13, and the magnetic moment direction in the antiferromagnetic insulating layer is parallel to the direction of the write current in the SOT layer 11.
In addition, an upper electrode may be formed over each magnetic tunnel junction 12 prior to vacuum annealing the antiferromagnetic insulating layer 13 to prevent oxidation of the reference layer surface during annealing.
One way to fabricate the test structure of a SOT-MRAM is shown in FIGS. 6-8. Referring to fig. 6, an 8nm thick Ta layer is first sputtered on a substrate 1010 (Si sheet) and patterned into a hall bar structure containing one lateral hall bar 111 and one longitudinal hall bar 112 as the SOT layer 11 in each memory cell. The width of the transverse hall bar 111 may be 2 micrometers and the width of the longitudinal hall bar 112 may be 2 micrometers. Then depositing a CoFeB material layer with the thickness of 0.8nm on the substrate 10 and the Hall rod structure in sequence to be used as a material layer for processing a free layer; depositing a MgO material layer with the thickness of 1nm as a material layer for processing the insulating layer; a 1.2nm thick layer of CoFeB material was deposited as the material layer for the process reference layer. Thereafter, referring to fig. 7, circular magnetic tunnel junctions 12 having a diameter of 100nm were fabricated at the intersection regions where the intersection region areas of the longitudinal and lateral hall bars 111 were 2 micrometers×2 micrometers by photolithography and etching, with etching depths to the Ta layer, i.e., each layer above the Ta layer, was etched. The antiferromagnetic insulating layer 13 may then be processed according to the sputtering process shown above. For example, niO may be sputtered in the region surrounding the etched magnetic tunnel junction 12 x The sputtering angle was 45 degrees and the sputtering thickness was 20nm. Subsequently, the NiO of 60nm is sputtered again by adopting a vertical sputtering mode x An antiferromagnetic insulating layer 13 is formed that fills all of the space between adjacent magnetic tunnel junctions 12. Thereafter, ti 15nm/Cu 100nm/Au 50nm was again exposed to electron beam and deposited as the upper electrode, and the sample preparation was completed as shown in FIG. 8. Of course, before depositing the upper electrode material layer, a Ta material layer with a thickness of 15nm can be deposited on the reference layer as a material layer for processing the buffer layer in other additional layers, so as to increase the bonding strength of the upper electrode and prevent the upper electrode from falling off. Thereafter, the prepared sample was subjected to 350℃under a magnetic field of 5kOeAnnealing for 10 min. In the process of annealing temperature rise and temperature reduction, the external magnetic field is kept at 5kOe all the time until the sample is cooled to normal temperature. And an external magnetic field is applied in a direction parallel to the extending direction of the lateral hall bar 111. The prepared sample and the test schematic diagram are shown in fig. 8, wherein a transverse hall bar 111 is used as a write current channel, and write current is introduced; the longitudinal hall bar 112 serves as a read current path through which a read current is passed.
By adding an antiferromagnetic insulating layer 13 around at least the side of the free layer in each magnetic tunnel junction 12 and making the magnetic moment direction of the antiferromagnetic insulating layer 13 parallel to the direction of the write current, an in-plane magnetic field can be provided to the free layer for the non-external magnetic field inversion of the SOT-MRAM, so as to solve the problem that the SOT-MRAM cannot be integrated on a large scale due to the application of an external magnetic field during the writing process. And the added antiferromagnetic insulating layer 13 is arranged around the magnetic tunnel junction 12, so that the magnetic tunnel junction 12 is protected from the surrounding environment.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims (11)

1. An SOT-MRAM, comprising:
a substrate;
a plurality of memory cells disposed on the substrate, each memory cell including an SOT layer deposited on the substrate for passing a write current, and a magnetic tunnel junction disposed on the SOT layer; wherein the magnetic tunnel junction comprises: a free layer deposited on the SOT layer, an insulating layer laminated on the free layer, and a reference layer laminated on the insulating layer;
an antiferromagnetic insulating layer surrounding at least the sides of the free layer in each magnetic tunnel junction, and the antiferromagnetic insulating layer has a magnetic moment parallel to the direction of the write current.
2. The SOT-MRAM of claim 1, wherein the antiferromagnetic insulating layer wraps at least all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction.
3. The SOT-MRAM of claim 2, wherein the antiferromagnetic insulating layer fills a space between adjacent magnetic tunnel junctions in the plurality of memory cells.
4. The SOT-MRAM of claim 1, wherein the material of the antiferromagnetic insulating layer is any one of CoFeB oxide, coOx, feOx, niOx, crOx, mnOx, coFe2O4, or a mixture or alloy of any of several materials.
5. The SOT-MRAM of claim 1, wherein the antiferromagnetic insulating layer surrounds each magnetic tunnel junction side with a thickness of at least 0.5 nanometers.
6. A method of fabricating an SOT-MRAM, comprising:
providing a substrate;
providing a plurality of memory cells on the substrate, comprising: depositing a plurality of SOT layers for passing a write current on the substrate; forming a magnetic tunnel junction on each SOT layer, wherein the magnetic tunnel junction comprises: a free layer deposited on the SOT layer, an insulating layer laminated on the free layer, and a reference layer laminated on the insulating layer;
forming an antiferromagnetic insulating layer surrounding at least the sides of the free layer in each magnetic tunnel junction;
the magnetic moment direction of the antiferromagnetic insulating layer is adjusted so that the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current.
7. The method of manufacturing of claim 6, wherein forming an antiferromagnetic insulating layer surrounding at least the sides of the free layer in each magnetic tunnel junction comprises:
and (3) adopting a sputtering process to enable the incidence angle between sputtered ions and the surface of the substrate to be in a range of more than 0 degrees and less than 90 degrees, and growing anti-ferromagnetic insulating materials on all sides of the free layer, the insulating layer and the reference layer in each magnetic tunnel junction to form the anti-ferromagnetic insulating layer which surrounds all sides of the free layer, the insulating layer and the reference layer in each magnetic tunnel junction.
8. The method of manufacturing of claim 7, wherein forming an antiferromagnetic insulating layer surrounding at least the sides of the free layer in each magnetic tunnel junction further comprises:
and adopting a vertical sputtering process to continuously fill the antiferromagnetic insulating material or other insulating materials between the adjacent antiferromagnetic insulating layers so as to fill the space between the adjacent magnetic tunnel junctions.
9. The method of manufacturing of claim 6, wherein forming a magnetic tunnel junction on each SOT layer and forming an antiferromagnetic insulating layer surrounding at least the free layer sides in each magnetic tunnel junction comprises:
filling a dielectric material between adjacent SOT layers on the substrate to form dielectric layers;
depositing a free material layer on the SOT layer and the dielectric layer;
depositing a layer of insulating material over the free material layer;
depositing a reference material layer on the insulating material layer;
covering a layer of photoresist on the reference material layer;
performing photoetching pattern exposure, and reserving photoresist above each magnetic tunnel junction;
and oxidizing the ferromagnetic materials which are not protected by the photoresist in the reference material layer and the free material layer into antiferromagnetic materials by adopting a plasma oxidation process so as to form the magnetic tunnel junction below the reserved photoresist and form the antiferromagnetic insulating layer which fills the space between the adjacent magnetic tunnel junctions in the memory cells.
10. The method of manufacturing of claim 6, wherein the adjusting the magnetic moment direction of the antiferromagnetic insulating layer such that the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current comprises:
vacuum annealing the antiferromagnetic insulating layer with the application of an external magnetic field; wherein the annealing temperature is higher than the Kerr temperature of the antiferromagnetic insulating layer material and the direction of the external magnetic field is parallel to the direction of the write current in the SOT layer.
11. The method of manufacturing of claim 10, wherein prior to vacuum annealing the antiferromagnetic insulating layer, the method of manufacturing further comprises:
an upper electrode is formed over each magnetic tunnel junction.
CN202111206785.4A 2021-10-15 2021-10-15 SOT-MRAM and manufacturing method thereof Pending CN115996579A (en)

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