CN111740011A - Spin orbit torque magnetic random access memory unit, memory array and memory - Google Patents
Spin orbit torque magnetic random access memory unit, memory array and memory Download PDFInfo
- Publication number
- CN111740011A CN111740011A CN202010594037.7A CN202010594037A CN111740011A CN 111740011 A CN111740011 A CN 111740011A CN 202010594037 A CN202010594037 A CN 202010594037A CN 111740011 A CN111740011 A CN 111740011A
- Authority
- CN
- China
- Prior art keywords
- layer
- gate
- spin
- random access
- access memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005291 magnetic effect Effects 0.000 title claims abstract description 88
- 230000015654 memory Effects 0.000 title claims abstract description 64
- 230000005290 antiferromagnetic effect Effects 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 42
- 238000003860 storage Methods 0.000 claims abstract description 24
- 230000005415 magnetization Effects 0.000 claims abstract description 13
- 230000000694 effects Effects 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 229910005916 GeTe2 Inorganic materials 0.000 claims description 16
- 230000005294 ferromagnetic effect Effects 0.000 claims description 15
- 230000005641 tunneling Effects 0.000 claims description 15
- 239000003302 ferromagnetic material Substances 0.000 claims description 14
- 238000003491 array Methods 0.000 claims description 8
- 229910002521 CoMn Inorganic materials 0.000 claims description 7
- 229910015136 FeMn Inorganic materials 0.000 claims description 7
- 229910019041 PtMn Inorganic materials 0.000 claims description 7
- 229910003289 NiMn Inorganic materials 0.000 claims description 6
- 229910019236 CoFeB Inorganic materials 0.000 claims description 3
- 229910002546 FeCo Inorganic materials 0.000 claims description 3
- 229910003090 WSe2 Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 133
- 238000010586 diagram Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000012546 transfer Methods 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 239000002885 antiferromagnetic material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 238000005265 energy consumption Methods 0.000 description 2
- 229910001385 heavy metal Inorganic materials 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000010287 polarization Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- -1 CrCoPt Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005411 Van der Waals force Methods 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007306 turnover Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
Abstract
The present disclosure provides a spin orbit torque magnetic random access memory unit, a memory array and a memory, wherein the spin orbit torque magnetic random access memory unit comprises: a magnetic tunnel junction and a gate; the gating device is a two-dimensional material-based gating device; a magnetic tunnel junction is disposed above the gate; the magnetic tunnel junction includes an antiferromagnetic layer and a free layer, the free layer adjoining the antiferromagnetic layer; and the gate is opened, the storage unit is conducted, the current generates spin current to be injected into the free layer, and the magnetization direction of the free layer is reversed under the exchange bias effect of the free layer and the antiferromagnetic layer. The SOT-MRAM storage unit without the external field utilizes the exchange bias effect, can realize the deterministic magnetization reversal of the SOT-MRAM storage unit under the room temperature zero magnetic field by applying the magnetic tunnel junction optimized bias voltage, achieves the purpose of data writing, and realizes the SOT-MRAM storage unit with the double-end structure.
Description
Technical Field
The disclosure relates to the field of magnetic random access memories, in particular to a spin orbit torque magnetic random access memory unit, a memory array and a memory which are three-dimensionally integrated and are free of external field directional magnetization reversal.
Background
The unprecedented demand for computing power of data processing chips by the rapid development of global informatization brings huge challenges to the existing memory architecture, and continuous innovation of novel memory technology is also driven. The traditional silicon-based storage technology approaches the limit, and the barriers in the aspects of energy consumption, read-write speed, reliability, storage capacity and the like are highlighted, so that various novel memories are promoted to be rapidly developed in recent years. As one of the new memories, a Magnetic Random Access Memory (MRAM) has the advantages of high read/write speed, low power consumption, non-volatility, radiation resistance, and the like, so that the MRAM is widely concerned and deeply studied in the information field all over the world.
The increasing technical requirements of information processing on the reading and writing speed, the storage capacity, the power consumption, the reliability and the like of a memory promote the iteration of MRAM research results. The first generation of MRAM uses pulsed current to generate an oersted field as a means of driving ferromagnetic layer information writing. However, this method causes a great power consumption and inevitably interferes with adjacent memory cells, which is disadvantageous for high-density integration of the device. Therefore, the first generation MRAM technology has not been expanded in practical use on a large scale. As a second generation MRAM, a Spin Transfer Torque magnetic random access memory (Spin Transfer Torque MRAM, abbreviated as STT-MRAM) has more excellent device performance. The core of STT-MRAM is Magnetic Tunnel Junction (MTJ) with "sandwich" structure, whose basic structure is composed of upper and lower electrodes, and a reference layer, a tunneling layer and a free layer for storing information between the electrodes. The ultrathin MTJ realizes information storage through spin injection, has a read-write speed equivalent to that of a traditional Static Random Access Memory (SRAM), greatly reduces the size of the device and power consumption, and has the nonvolatile characteristic necessary for future memory devices. Therefore, during their development, researchers have also positioned STT-MRAM on high speed memory devices similar to SRAM, and have continued to make innovative developments. However, the STT-MRAM information writing process requires a large current to pass directly through the tunnel junction, which is detrimental to device stability and is accompanied by relatively high power consumption.
With respect to the shortcomings of STT-MRAM memory technology, a new generation of MRAM has emerged. In 2012, Spin-Orbit Torque magnetic random access memory (Spin-Orbit Torque MRAM, short for SOT-MRAM) technology was proposed. Although the SOT-MRAM core structure is also MTJ, there are completely different ways to write information. The spin-orbit torque SOT effect is utilized to turn over the magnetic free layer, and when information is written in, large current is not needed to pass through a tunnel junction, so that the information reading and writing separation is realized, the stability of the device can be greatly improved, and the experimental verification proves that the magnetic free layer has higher magnetization turning speed and lower turning critical current density than STT, and the power consumption is greatly reduced.
Although spin-orbit torque SOT is expected to solve the bottleneck of speed, energy consumption and barrier reliability faced by spin-transfer torque STT, SOT still has the problem to be solved urgently. Firstly, when data is written, an auxiliary in-plane static magnetic field needs to be added to the SOT-MRAM, which is not beneficial to the manufacture and miniaturization of the SOT-MRAM; secondly, the conventional three-terminal SOT-MRAM occupies a larger area than a two-terminal device such as STT-MRAM, which is not favorable for further improvement of storage capacity. Therefore, how to realize high-speed, high-reliability and low-power consumption information storage and reading of the SOT-MRAM under the condition of full-electrical driving without depending on an external magnetic field and how to improve the storage capacity of the SOT-MRAM becomes a key core problem to be solved urgently on the development path of the integrated SOT-MRAM.
Disclosure of Invention
Technical problem to be solved
The present disclosure provides a spin-orbit torque magnetic random access memory cell, a memory array and a memory to solve the above-mentioned technical problems.
(II) technical scheme
According to an aspect of the present disclosure, there is provided a spin-orbit torque magnetic random access memory cell comprising:
a gate that is a two-dimensional material-based gate;
a magnetic tunnel junction disposed above or below the gate; the magnetic tunnel junction includes an antiferromagnetic layer and a free layer, the free layer adjoining the antiferromagnetic layer;
and the gate is opened, the storage unit is conducted, the current generates spin current to be injected into the free layer, and the magnetization direction of the free layer is reversed under the exchange bias effect of the free layer and the antiferromagnetic layer.
In some embodiments of the present disclosure, the magnetic tunnel junction further comprises: the tunneling layer, the reference layer, the free layer and the antiferromagnetic layer are sequentially stacked; the gate abuts the antiferromagnetic layer or the reference layer; alternatively, the first and second electrodes may be,
the magnetic tunnel junction further includes: the device comprises a ferromagnetic layer, a tunneling layer and a reference layer, wherein the reference layer, the tunneling layer, the free layer, the antiferromagnetic layer and the ferromagnetic layer are sequentially laminated; the gate abuts the ferromagnetic layer or the reference layer.
In some embodiments of the present disclosure, the spin orbit torque magnetic random access memory cell further comprises:
a word line and a bit line, the gate and the magnetic tunnel junction being disposed between the word line and the bit line.
In some embodiments of the present disclosure, the gate comprises:
a stack unit, the stack unit being a metal-two-dimensional semiconductor-metal structure, the metal-two-dimensional semiconductor-metal structure comprising: the two-dimensional semiconductor layer and the metal layers are respectively arranged on the upper surface and the lower surface of the two-dimensional semiconductor layer;
when the two-dimensional material gate is electrified and conducted, the laminated unit comprises two Schottky diode structures which are connected in an anti-parallel mode; or
The gate includes:
m laminated units, wherein M is more than or equal to 2, each laminated unit is a metal-two-dimensional semiconductor-metal structure, and the metal-two-dimensional semiconductor-metal structure comprises: the two-dimensional semiconductor layer and the metal layers are respectively arranged on the upper surface and the lower surface of the two-dimensional semiconductor layer;
in each laminated unit, one metal-two-dimensional semiconductor interface forms ohmic contact, and the other metal-two-dimensional semiconductor interface forms Schottky contact;
the M laminated units are arranged along a first direction, the first direction is parallel to the plane of the two-dimensional semiconductor layer, an insulating layer is arranged between the side walls of two adjacent laminated units in the M laminated units, and the M laminated units are M Schottky diode structures which are reversely connected in parallel when the two-dimensional material-based gate is electrified and conducted.
In some embodiments of the present disclosure, the reference layer has a magnetic polarization in the film plane or not; the free layer has a magnetic polarization parallel or anti-parallel to the reference layer.
In some embodiments of the present disclosure, the gate material is a two-dimensional van der waals material selected from WS2 or WSe 2; the starting voltage of the gate is-1V or 1V; the opening current density of the gate is 10MA/cm 2; the thickness of the gate ranges from 2nm to 7 nm.
In some embodiments of the present disclosure, the material of the tunneling layer is MgO, Al2O3、MaAl2O4And one or more of h-BN or one or more of two-dimensional van der Waals materials h-BN; the free layer material is two-dimensional ferromagnetic material selected from Fe3GeTe2、FeCo、CrCoPt、CoFeB、CoFe2Al、Mn3Ga or two-dimensional ferromagnetic material Ni3GeTe2、VSe2、CrI3One or more of; the material of the antiferromagnetic layer is selected from Fe3GeTe2One or more of IrMn, FeMn, NiMn, CoMn, PtMn, Co/Pt, FeO, CoO, NiO and MnO; the antiferromagnetic layer is at least one layer; the material of the ferromagnetic layer is selected from Fe3GeTe2One or more of IrMn, FeMn, NiMn, CoMn, PtMn, Co/Pt, FeO, CoO, NiO and MnO; the ferromagnetic layer is at least one layer.
In some embodiments of the present disclosure, the word line material is selected from any one or more of Ta, Pt, β -W.
There is also provided, according to an aspect of the present disclosure, a spin orbit torque magnetic random access memory array, wherein the memory array comprises:
at least one level of crossbar memory arrays, each level of crossbar memory arrays comprising:
a bit line array including a plurality of bit lines arranged in parallel along a first direction;
a word line array including a plurality of word lines arranged in parallel along a second direction; wherein the first direction and the second direction have an included angle therebetween;
a plurality of memory cells disposed at intersections of the word line array and the bit line array, each of the plurality of memory cells being a memory cell as described above;
optionally, the storage array further comprises: and the transistor is connected in series on each word line of a plurality of word lines of each layer of the crossed storage array and is used for controlling the on-off of the corresponding word line.
According to an aspect of the present disclosure, there is also provided a spin orbit torque magnetic random access memory comprising a spin orbit torque magnetic random access memory array as described above.
(III) advantageous effects
According to the technical scheme, the spin-orbit torque magnetic random access memory unit, the memory array and the memory have at least one or part of the following beneficial effects:
(1) in the disclosure, the exchange bias effect of the free layer and the antiferromagnetic layer of the magnetic tunnel junction is combined with the application of the optimized bias of the magnetic tunnel junction to realize the information writing of the SOT-MRAM at room temperature without an external magnetic field, and the conversion efficiency of charge flow to spin current and the absorption rate of the magnetic material of the free layer to the spin current are increased; the magnetic tunnel junction provided by the present disclosure has the advantages of high speed, high reliability, small size and low power consumption.
(2) The two-dimensional material-based gate can provide the driving current of the selected storage unit and ensure the extremely small leakage current of the unselected part, and the two-dimensional material-based gate has the advantages of nanoscale scalability, compatibility with the COMS process, bidirectional threshold conduction characteristic, low turn-on voltage, high turn-on current density, low turn-on resistance, high nonlinearity and excellent thermal stability.
(3) The cross stacked array is adopted in the method, three-dimensional integration and large-scale production are achieved, and compared with a traditional two-dimensional storage array, the storage capacity is greatly improved.
Drawings
FIG. 1 is a schematic diagram of a memory cell according to an embodiment of the disclosure.
Fig. 2a is a schematic diagram of the band energy structure of the gate in fig. 1.
Fig. 2b is a schematic diagram of the simulated current-voltage characteristic of the gate of fig. 1.
FIG. 3 is a schematic structural diagram of a ferromagnetic material of a magnetic tunnel junction of a memory cell according to an embodiment of the present disclosure.
FIG. 4a is a schematic diagram of a ferromagnetic material in a free layer having a spin direction opposite to that of a reference layer in a memory cell according to an embodiment of the present disclosure.
FIG. 4b is a schematic diagram of the spin direction of the ferromagnetic material in the free layer of the memory cell of the embodiment of the present disclosure being the same as the reference layer.
FIG. 5 is a schematic diagram of a three-dimensional structure of a spin-orbit torque magnetic random access memory according to an embodiment of the disclosure.
[ description of main reference numerals in the drawings ] of the embodiments of the present disclosure
11-an array of bit lines;
110-bit line;
120-a gate;
130-a magnetic tunnel junction;
131-a reference layer;
132-a tunneling layer;
133-free layer;
134-an antiferromagnetic layer;
14-an array of word lines;
140-word lines;
141-sub word lines;
150-a transistor;
200-memory array.
Detailed Description
The present disclosure provides a spin orbit torque magnetic random access memory unit, a memory array and a memory, wherein the spin orbit torque magnetic random access memory unit comprises: a magnetic tunnel junction and a gate; the gating device is a two-dimensional material-based gating device; a magnetic tunnel junction is disposed above or below the gate; the magnetic tunnel junction includes an antiferromagnetic layer and a free layer, the free layer adjoining the antiferromagnetic layer; and the gate is opened, the storage unit is conducted, the current generates spin current to be injected into the free layer, and the magnetization direction of the free layer is reversed under the exchange bias effect of the free layer and the antiferromagnetic layer. The method has the advantages that the exchange bias effect is utilized without an external field, the deterministic magnetization reversal of the SOT-MRAM storage unit under the room temperature zero magnetic field can be realized by applying the MTJ optimized bias voltage, the data writing purpose is realized, and the SOT-MRAM storage unit with a double-end structure is realized.
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.
Certain embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the disclosure are shown. Indeed, various embodiments of the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements.
In a first exemplary embodiment of the present disclosure, a spin-orbit torque magnetic random access memory cell is provided. FIG. 1 is a schematic diagram of a memory cell according to an embodiment of the disclosure. As shown in FIG. 1, the spin-orbit torque MRAM cell of the present disclosure includes: word line 140, bit line 110, magnetic tunnel junction 130, and gate 120. The gate 120 and the magnetic tunnel junction 130 are disposed between the word line 140 and the bit line 110; gating device 120 is a two-dimensional material-based gating device; a magnetic tunnel junction 130 is disposed above or below the gate 120; the magnetic tunnel junction 130 includes an antiferromagnetic layer 134 and a free layer 133, the free layer 133 adjoining the antiferromagnetic layer 134. The gate 120 is turned on, the memory cell is turned on, a current generates a spin current to be injected into the free layer 133, and the magnetization direction of the free layer 133 is reversed under the exchange bias effect of the free layer 133 and the antiferromagnetic layer 134.
The spin-orbit torque magnetic random access memory cell provided in this embodiment is a two-terminal structure. Wherein the bit line 110 is connected to the gate 120, the bit line 110 is made of metal, and the gate 120 is formed of a two-dimensional material and a metal heterostructure; the magnetic tunnel junction includes: a reference layer 131, a tunneling layer 132, a free layer 133, and an antiferromagnetic layer 134, the reference layer 131, the tunneling layer 132, the free layer 133, and the antiferromagnetic layer 134 being sequentially stacked; the gate 120 abuts the antiferromagnetic layer 134. Here, the sequential stacking means that the layers are sequentially stacked in order, and other layers may be provided between the layers, and the stacking order may be from bottom to top or from top to bottom. The bottom of the antiferromagnetic layer 134 is coupled to the word line 140, and the transistor 150 of the memory cell in this embodiment is a select/gate transistor, and the other terminal of the select/gate transistor is connected to the control terminal, so that the write control of the spin-orbit torque magnetic random access memory cell can be completed.
The following describes each component of the spin-orbit torque magnetic random access memory cell of the present embodiment in detail.
The gate 120 is composed of a metal-semiconductor-metal (MSM) structure connected in parallel, when biased across, as shown in fig. 2 a. When the external bias voltage is small, one side of the Schottky barrier is in forward conduction, and the other side of the Schottky barrier is in reverse cutoff. At this time, the current-voltage characteristic is as shown in fig. 2b, the voltage is less than 1/2Vo, the current is extremely small, and the current can be regarded as an off state; when the external bias voltage is increased, the density of the current of hot carrier emission, FN tunneling and direct tunneling in the semiconductor is increased, and the threshold voltage Vo is reached, the gate is started, the spin-orbit torque magnetic random memory unit is conducted, and the read-write operation can be carried out. The components of gate 120 are described in detail below. In one embodiment, the gate includes: a stack unit, the stack unit being a metal-two-dimensional semiconductor-metal structure, the metal-two-dimensional semiconductor-metal structure comprising: the two-dimensional semiconductor layer and the metal layers are respectively arranged on the upper surface and the lower surface of the two-dimensional semiconductor layer; when the two-dimensional material gate is electrified and conducted, the laminated unit comprises two Schottky diode structures which are connected in an anti-parallel mode. In another embodiment the gate comprises: m laminated units, wherein M is more than or equal to 2, each laminated unit is a metal-two-dimensional semiconductor-metal structure, and the metal-two-dimensional semiconductor-metal structure comprises: the two-dimensional semiconductor layer and the metal layers are respectively arranged on the upper surface and the lower surface of the two-dimensional semiconductor layer; in each laminated unit, one metal-two-dimensional semiconductor interface forms ohmic contact, and the other metal-two-dimensional semiconductor interface forms Schottky contact; the M laminated units are arranged along a first direction (x direction), the first direction is parallel to the plane of the two-dimensional semiconductor layer, an insulating layer is arranged between the side walls of two adjacent laminated units in the M laminated units, and the M laminated units are M Schottky diode structures which are reversely connected in parallel when the two-dimensional material-based gate is electrified and conducted.
FIG. 3 is a schematic structural diagram of a ferromagnetic material of a magnetic tunnel junction of a memory cell according to an embodiment of the present disclosure. In the present embodiment, the reference layer 131 and the free layer 133 are made of two-dimensional van der Waals ferromagnetic material Fe3GeTe2(FGT) with a schematic diagram of the lattice structure shown as 130 in fig. 3, the free layer 133 and the reference layer 131 are connected by van der waals force, the material itself is compatible with modern integrated circuit process, and few-layer, even single-layer two-dimensional material can be obtained by chemical vapor transport, atomic layer deposition and other technical methods; the atomic layer surface is smooth, no extra dangling bond exists, the interface characteristic is more excellent, and the loss caused by scattering during data writing is reduced; other alternative materials include FeCo, CrCoPt, CoFeB, CoFe2Al、Mn3Ga or two-dimensional ferromagnetic material Ni3GeTe2、VSe2、CrI3One or more of them; the tunneling layer 132 is made of MgO, and the alternative material includes Al2O3、MaAl2O4Or one of two-dimensional van der waals materials h-BN. The antiferromagnetic layer 134 in this embodiment uses Fe having antiferromagnetic property3GeTe2，Fe3GeTe2Existing ferromagnetic/antiferromagnetic phases having an effective exchange bias field HEBDeterministic switching of spin-orbit torque MRAM cells at room temperature without an applied magnetic field can be achieved by applying the magnetic tunnel junction 130 to optimize the bias voltage. The antiferromagnetic layer 134 can also be used with other materials that have antiferromagnetic properties, including IrMn, FeMn, NiMnOne or more layers of CoMn, PtMn, Co/Pt, or one or more layers of metal oxide antiferromagnetic materials FeO, CoO, NiO, MnO. In the material Fe3GeTe2In the material Fe3GeTe2Is applied with a constant bias voltage of 1-2V which induces electrons to fill up the d derived from Fe in turnz 2、dxzAnd dyzThe sub-band of the orbit leads to the increase of the density of the edge electronic state, and further leads to the increase of the environment stable temperature of the long-range ordered-state magnetic moment structure, namely the obvious increase of the Curie temperature. The method is also suitable for modulating the ferromagnetic material with Curie temperature lower than the room temperature or the antiferromagnetic material with Neille temperature lower than the room temperature in the same external bias mode, and ensures that the ferromagnetic and antiferromagnetic of the two-dimensional material can be controllably modulated by optimizing the bias voltage at the room temperature.
FIG. 4a is a schematic diagram of a ferromagnetic material in a free layer having a spin direction opposite to that of a reference layer in a memory cell according to an embodiment of the present disclosure. As shown in FIG. 4a, when the spin-orbit torque magnetic random access memory cell performs a write operation, a bias voltage + V is applied between the bit line 110 and the word line 1401(greater than the gate turn-on voltage) when the gate 120 is turned on and current flows through the memory cell. The writing principle of the two-terminal memory cell is dominated by SOT, and when a current flows through the heavy metal layer of the word line 140, the current generates a spin current, which is injected into the combined structure of the free layer 133 and the antiferromagnetic layer 134. The material of the antiferromagnetic layer 134 is selected from Fe3GeTe2One or more of IrMn, FeMn, NiMn, CoMn, PtMn, Co/Pt, FeO, CoO, NiO and MnO. At this point, the antiferromagnetic layer 134 may couple with the adjacent free layer, thereby generating an exchange bias field in the planar direction that may provide an in-plane field to break the symmetry break instead of the externally applied magnetic field required by conventional SOT-MRAM, enabling deterministic magnetization switching in the free layer ferromagnetic material. At this time, the ferromagnetic material in the free layer 133 has a spin direction opposite to that of the reference layer 131, and the magnetic tunnel junction 130 exhibits a high resistance state, representing data "1". In another embodiment, the write principle of the two-terminal memory cell is dominated by SOT, and when current flows through the heavy metal layer of the word line 140, the current generates spin current, which is injected into the free layer 133A combined structure of an antiferromagnetic layer 134 and a ferromagnetic layer. The material of the ferromagnetic layer is selected from Fe3GeTe2One or more of IrMn, FeMn, NiMn, CoMn, PtMn, Co/Pt, FeO, CoO, NiO and MnO. It should be noted that the materials referred to in this disclosure include corresponding material systems achieved by modulation of composition, surface and interface or doping of elements.
In writing a "0", as shown in FIG. 4b, an applied voltage of-V1 is applied between the bit line 110 and the word line 140, and the current is reversed, as described above, when the device sets the spin direction in the free layer 133 to be the same as the direction of the reference layer 131 through the SOT effect and the exchange bias effect, and the magnetic tunnel junction 130 assumes a low resistance state, representing a data "0". Thereby achieving programmed storage of the binary number.
Embodiments of the present disclosure also provide a spin-orbit torque magnetic random access memory array. FIG. 5 is a schematic diagram of a spin-orbit torque magnetic random access memory according to an embodiment of the present disclosure. As shown in fig. 5, the spin orbit torque magnetic random access memory of the present disclosure includes: at least one level of crossbar memory arrays, each level of crossbar memory arrays comprising: a bit line array 11, a word line array 14, and memory cells. The bit line array 11 includes a plurality of bit lines 110 arranged in parallel along a first direction (x-direction). The word line array 14 includes a plurality of word lines 140 arranged in parallel along a second direction (y direction); wherein the first direction and the second direction have an included angle therebetween. The word line array 14 includes three word lines 140 and a transistor 150 connected in series at the end, and the transistor is connected in series on each word line 140 of the plurality of word lines of each layer of the cross memory array for controlling the on/off of the corresponding word line. Each word line 140 is used as a common word line, and a plurality of sub word lines 141 are disposed on the same side of the common word line and used for being connected to the memory cells, so as to avoid interference on the memory cells on other word lines in the same layer of the cross memory array when data is written. As shown in fig. 5, the three bit lines 110 are arranged in a parallel array at equal intervals. In practical applications, the number is not limited to three. The three word lines 140 are arranged in parallel and equidistant, with a transistor 150, in this embodiment a select/gate transistor, connected in series at the end of each word line 140. In practical applications, the number of word lines 140 is not limited to three. When the memory array is larger than one, a plurality of memory arrays are stacked in a vertical direction. The number of layers is not limited to 2, and the layers are overlapped until the resolution or the process of an electronic circuit of the spin-orbit torque magnetic random access memory reaches the upper limit of the number of layers.
Embodiments of the present disclosure also provide a spin-orbit torque magnetic random access memory including a memory cell and/or a memory array as described above.
So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Furthermore, the above definitions of the various elements and methods are not limited to the particular structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by one of ordinary skill in the art, for example:
(1) the shapes of the gate, the magnetic tunnel junction, and the antiferromagnetic layer may be replaced with simple shapes such as a rectangle, a ring, and the like.
(2) Simple movement of the location of the memory cells in the array by the gate, the two-dimensional gate can be located above or below the magnetic tunnel junction.
From the above description, those skilled in the art should have a clear understanding of the spin-orbit torque magnetic random access memory cells, memory arrays, and memories of the present disclosure.
In summary, the present disclosure provides a spin orbit torque magnetic random access memory unit, a memory array and a memory integrated in three dimensions without external field oriented magnetization switching, which have the advantages of high speed, high reliability, small size and low power consumption, and have a wide application prospect in the field of random access memories.
It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.
And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.
Unless otherwise indicated, the numerical parameters set forth in the specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the present disclosure. In particular, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Generally, the expression is meant to encompass variations of ± 10% in some embodiments, 5% in some embodiments, 1% in some embodiments, 0.5% in some embodiments by the specified amount.
Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.
The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. A spin-orbit torque magnetic random access memory cell, comprising:
a gate that is a two-dimensional material-based gate;
a magnetic tunnel junction disposed above or below the gate; the magnetic tunnel junction includes an antiferromagnetic layer and a free layer, the free layer adjoining the antiferromagnetic layer;
and the gate is opened, the storage unit is conducted, the current generates spin current to be injected into the free layer, and the magnetization direction of the free layer is reversed under the exchange bias effect of the free layer and the antiferromagnetic layer.
2. The spin-orbit torque magnetic random access memory cell of claim 1,
the magnetic tunnel junction further includes: the tunneling layer, the reference layer, the free layer and the antiferromagnetic layer are sequentially stacked; the gate abuts the antiferromagnetic layer or the reference layer; alternatively, the first and second electrodes may be,
the magnetic tunnel junction further includes: the device comprises a ferromagnetic layer, a tunneling layer and a reference layer, wherein the reference layer, the tunneling layer, the free layer, the antiferromagnetic layer and the ferromagnetic layer are sequentially laminated; the gate abuts the ferromagnetic layer or the reference layer.
3. The spin orbit torque magnetic random access memory unit of claim 1, further comprising:
a word line and a bit line, the gate and the magnetic tunnel junction being disposed between the word line and the bit line.
4. The spin orbit torque magnetic random access memory cell of claim 1, wherein the gate comprises:
a stack unit, the stack unit being a metal-two-dimensional semiconductor-metal structure, the metal-two-dimensional semiconductor-metal structure comprising: the two-dimensional semiconductor layer and the metal layers are respectively arranged on the upper surface and the lower surface of the two-dimensional semiconductor layer;
when the two-dimensional material gate is electrified and conducted, the laminated unit comprises two Schottky diode structures which are connected in an anti-parallel mode; or
The gate includes:
m laminated units, wherein M is more than or equal to 2, each laminated unit is a metal-two-dimensional semiconductor-metal structure, and the metal-two-dimensional semiconductor-metal structure comprises: the two-dimensional semiconductor layer and the metal layers are respectively arranged on the upper surface and the lower surface of the two-dimensional semiconductor layer;
in each laminated unit, one metal-two-dimensional semiconductor interface forms ohmic contact, and the other metal-two-dimensional semiconductor interface forms Schottky contact;
the M laminated units are arranged along a first direction, the first direction is parallel to the plane of the two-dimensional semiconductor layer, an insulating layer is arranged between the side walls of two adjacent laminated units in the M laminated units, and the M laminated units are M Schottky diode structures which are reversely connected in parallel when the two-dimensional material-based gate is electrified and conducted.
5. The spin-orbit torque magnetic random access memory cell of claim 2, wherein the reference layer has a magnetization direction in-plane or out-of-plane; the free layer has a magnetization direction parallel or anti-parallel to the reference layer.
6. The spin-orbit torque magnetic random access memory cell of claim 1, wherein the gate material is a two-dimensional van der waals material selected from WS2Or WSe2(ii) a The starting voltage of the gate is-1V or 1V; the opening current density of the gate is 10MA/cm2(ii) a The thickness of the gate ranges from 2nm to 7 nm.
7. The spin-orbit-torque MRAM cell of claim 2, wherein the tunneling layer is made of MgO, A12O3、MaAl2O4And one or more of h-BN or one or more of two-dimensional van der Waals materials h-BN; the free layer material is two-dimensional ferromagnetic material selected from Fe3GeTe2、FeCo、CrCoPt、CoFeB、CoFe2Al、Mn3Ga or two-dimensional ferromagnetic material Ni3GeTe2、VSe2、CrI3One or more of; the material of the antiferromagnetic layer is selected from Fe3GeTe2One or more of IrMn, FeMn, NiMn, CoMn, PtMn, Co/Pt, FeO, CoO, NiO and MnO; the antiferromagnetic layer is at least one layer; the material of the ferromagnetic layer is selected from Fe3GeTe2One or more of IrMn, FeMn, NiMn, CoMn, PtMn, Co/Pt, FeO, CoO, NiO and MnO; the ferromagnetic layer is at least one layer.
8. The spin-orbit torque magnetic random access memory cell of claim 3, wherein the word line material is selected from any one or more of Ta, Pt, β -W.
9. A spin orbit torque magnetic random access memory array, wherein the memory array comprises:
at least one level of crossbar memory arrays, each level of crossbar memory arrays comprising:
a bit line array including a plurality of bit lines arranged in parallel along a first direction;
a word line array including a plurality of word lines arranged in parallel along a second direction; wherein the first direction and the second direction have an included angle therebetween;
a plurality of memory cells disposed at intersections of the word line array and the bit line array, each of the plurality of memory cells being a memory cell according to any one of claims 1 to 8;
optionally, the storage array further comprises: and the transistor is connected in series on each word line of a plurality of word lines of each layer of the crossed storage array and is used for controlling the on-off of the corresponding word line.
10. A spin orbit torque magnetic random access memory comprising the spin orbit torque magnetic random access memory array of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010594037.7A CN111740011A (en) | 2020-06-24 | 2020-06-24 | Spin orbit torque magnetic random access memory unit, memory array and memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010594037.7A CN111740011A (en) | 2020-06-24 | 2020-06-24 | Spin orbit torque magnetic random access memory unit, memory array and memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111740011A true CN111740011A (en) | 2020-10-02 |
Family
ID=72651205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010594037.7A Pending CN111740011A (en) | 2020-06-24 | 2020-06-24 | Spin orbit torque magnetic random access memory unit, memory array and memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111740011A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111986717A (en) * | 2020-08-20 | 2020-11-24 | 中国科学院微电子研究所 | SOT-MRAM (spin on demand-random Access memory) without external magnetic field oriented spin reversal and array |
| CN112420096A (en) * | 2020-11-20 | 2021-02-26 | 复旦大学 | Spin orbit torque magnetic random access memory without MOS tube |
| CN112863566A (en) * | 2021-01-29 | 2021-05-28 | 北京航空航天大学 | Storage array, memory, preparation method and writing method |
| CN113889163A (en) * | 2021-12-07 | 2022-01-04 | 北京芯可鉴科技有限公司 | Random magnetic tunnel junction device with controllable turnover probability and application method |
| WO2022141226A1 (en) * | 2020-12-30 | 2022-07-07 | 中国科学院微电子研究所 | Multi-resistive spin electronic device, read-write circuit, and in-memory boolean logic operator |
| WO2022252099A1 (en) * | 2021-05-31 | 2022-12-08 | 华为技术有限公司 | Magnetic random access memory and control method therefor, and electronic device |
| WO2023017338A1 (en) * | 2021-08-13 | 2023-02-16 | International Business Machines Corporation | Spin-orbit-torque magnetoresistive random-access memory array |
| WO2023060627A1 (en) * | 2021-10-15 | 2023-04-20 | 中国科学院微电子研究所 | Sot-mram and manufacturing method therefor |
| US11793001B2 (en) | 2021-08-13 | 2023-10-17 | International Business Machines Corporation | Spin-orbit-torque magnetoresistive random-access memory |
| US11915734B2 (en) | 2021-08-13 | 2024-02-27 | International Business Machines Corporation | Spin-orbit-torque magnetoresistive random-access memory with integrated diode |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579238A (en) * | 2012-08-10 | 2014-02-12 | 中国科学院微电子研究所 | Memorizer device |
| US20170117027A1 (en) * | 2015-10-21 | 2017-04-27 | HGST Netherlands B.V. | Top pinned sot-mram architecture with in-stack selector |
| CN106876582A (en) * | 2017-02-21 | 2017-06-20 | 中国科学院物理研究所 | MTJ and magnetic device and electronic equipment including it |
| US20170316813A1 (en) * | 2015-05-13 | 2017-11-02 | Korea University Research And Business Foundation | Magnetic memory device |
| CN109300495A (en) * | 2018-09-18 | 2019-02-01 | 西安交通大学 | Magnetic texure and SOT-MRAM based on artificial antiferromagnetic free layer |
| US20190288185A1 (en) * | 2018-03-16 | 2019-09-19 | Tdk Corporation | Spin-orbit-torque magnetization rotational element, spin-orbit-torque magnetoresistance effect element, magnetic memory, and oscillator |
| US20200075676A1 (en) * | 2018-09-04 | 2020-03-05 | Imec Vzw | Memory selector and memory device including same |
-
2020
- 2020-06-24 CN CN202010594037.7A patent/CN111740011A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579238A (en) * | 2012-08-10 | 2014-02-12 | 中国科学院微电子研究所 | Memorizer device |
| US20170316813A1 (en) * | 2015-05-13 | 2017-11-02 | Korea University Research And Business Foundation | Magnetic memory device |
| US20170117027A1 (en) * | 2015-10-21 | 2017-04-27 | HGST Netherlands B.V. | Top pinned sot-mram architecture with in-stack selector |
| CN106876582A (en) * | 2017-02-21 | 2017-06-20 | 中国科学院物理研究所 | MTJ and magnetic device and electronic equipment including it |
| US20190288185A1 (en) * | 2018-03-16 | 2019-09-19 | Tdk Corporation | Spin-orbit-torque magnetization rotational element, spin-orbit-torque magnetoresistance effect element, magnetic memory, and oscillator |
| US20200075676A1 (en) * | 2018-09-04 | 2020-03-05 | Imec Vzw | Memory selector and memory device including same |
| CN109300495A (en) * | 2018-09-18 | 2019-02-01 | 西安交通大学 | Magnetic texure and SOT-MRAM based on artificial antiferromagnetic free layer |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111986717A (en) * | 2020-08-20 | 2020-11-24 | 中国科学院微电子研究所 | SOT-MRAM (spin on demand-random Access memory) without external magnetic field oriented spin reversal and array |
| CN112420096A (en) * | 2020-11-20 | 2021-02-26 | 复旦大学 | Spin orbit torque magnetic random access memory without MOS tube |
| WO2022141226A1 (en) * | 2020-12-30 | 2022-07-07 | 中国科学院微电子研究所 | Multi-resistive spin electronic device, read-write circuit, and in-memory boolean logic operator |
| CN112863566A (en) * | 2021-01-29 | 2021-05-28 | 北京航空航天大学 | Storage array, memory, preparation method and writing method |
| WO2022252099A1 (en) * | 2021-05-31 | 2022-12-08 | 华为技术有限公司 | Magnetic random access memory and control method therefor, and electronic device |
| WO2023017338A1 (en) * | 2021-08-13 | 2023-02-16 | International Business Machines Corporation | Spin-orbit-torque magnetoresistive random-access memory array |
| US11793001B2 (en) | 2021-08-13 | 2023-10-17 | International Business Machines Corporation | Spin-orbit-torque magnetoresistive random-access memory |
| US11915734B2 (en) | 2021-08-13 | 2024-02-27 | International Business Machines Corporation | Spin-orbit-torque magnetoresistive random-access memory with integrated diode |
| WO2023060627A1 (en) * | 2021-10-15 | 2023-04-20 | 中国科学院微电子研究所 | Sot-mram and manufacturing method therefor |
| CN113889163A (en) * | 2021-12-07 | 2022-01-04 | 北京芯可鉴科技有限公司 | Random magnetic tunnel junction device with controllable turnover probability and application method |
| CN113889163B (en) * | 2021-12-07 | 2022-03-01 | 北京芯可鉴科技有限公司 | Random magnetic tunnel junction device with controllable turnover probability and application method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111740011A (en) | Spin orbit torque magnetic random access memory unit, memory array and memory | |
| CN109300495B (en) | Magnetic structure based on artificial antiferromagnetic free layer and SOT-MRAM | |
| US9202545B2 (en) | Magnetoresistance effect element and magnetic memory | |
| EP1949466B1 (en) | A magnetoresistive tunnel junction magnetic device and its application to mram | |
| EP2385548B1 (en) | Magnetic memory element and driving method therefor | |
| KR101893908B1 (en) | Method and system for providing hybrid magnetic tunneling junction elements with improved switching | |
| US8254162B2 (en) | Method and system for providing magnetic tunneling junctions usable in spin transfer torque magnetic memories | |
| CN103794715B (en) | A kind of based on voltage-controlled magnetic memory | |
| US8519496B2 (en) | Spin-transfer torque magnetic random access memory with multi-layered storage layer | |
| CN106449970B (en) | A kind of low-power consumption magnetic memory cell | |
| CN111554809A (en) | Two-dimensional material-based gates, memory cells, arrays, and methods of operating the same | |
| JP2009252909A (en) | Magneto-resistive element, and magnetic random access memory | |
| US20230276637A1 (en) | Spin orbit torque magnetic random access memory cell, memory array, and memory | |
| EP2355142B1 (en) | Magnetic memory element and nonvolatile storage device | |
| CN107342359B (en) | Magneto-resistor element suitable for working at high temperature | |
| EP2306510B1 (en) | Magnetic memory element and its driving method and nonvolatile memory device | |
| CN112863566B (en) | Memory array, memory, preparation method and writing method | |
| CN110993782B (en) | Spin-orbit momentum moment magnetic memory based on perovskite type heterojunction substrate and sawtooth type tunneling heterojunction | |
| JP5611594B2 (en) | Recording method for nonvolatile solid-state magnetic memory and nonvolatile solid-state magnetic memory | |
| CN112514090B (en) | Magnetoresistive random access memory cell, memory and access method | |
| WO2021114571A1 (en) | Two-dimensional material-based gate, memory unit, array, and operating method thereof | |
| US20240023347A1 (en) | Memory array, memory, preparing method and writing method | |
| CN111697130B (en) | Magnetic memory cell and logic device having horizontally asymmetric magnetic free layer | |
| CN114156407A (en) | Spin splitting-ferromagnetic coupling material and application thereof | |
| CN114914357A (en) | Novel magnetic tunnel junction memory device based on bismuth selenide and nickel iodide heterojunction substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |