CN115995463A - Semiconductor device, manufacturing method of semiconductor device and electronic equipment - Google Patents

Semiconductor device, manufacturing method of semiconductor device and electronic equipment Download PDF

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CN115995463A
CN115995463A CN202211413679.8A CN202211413679A CN115995463A CN 115995463 A CN115995463 A CN 115995463A CN 202211413679 A CN202211413679 A CN 202211413679A CN 115995463 A CN115995463 A CN 115995463A
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semiconductor device
voltage
source
silicon carbide
field effect
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王威
黄汇钦
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Sirius Semiconductor Chengdu Co ltd
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Sirius Semiconductor Chengdu Co ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention provides a semiconductor device, a preparation method of the semiconductor device and electronic equipment, and relates to the technical field of semiconductors. The semiconductor device comprises a high-voltage depletion type silicon carbide junction field effect transistor, wherein the high-voltage depletion type silicon carbide junction field effect transistor comprises a first grid electrode, a first drain electrode and a first source electrode; a low voltage enhancement mode gallium nitride high electron mobility transistor comprising a second gate, a second drain, and a second source; the first grid electrode is connected with the second source electrode, the first source electrode is connected with the second drain electrode, the source electrode of the semiconductor device is the second source electrode, the grid electrode of the semiconductor device is the second grid electrode, and the drain electrode of the semiconductor device is the first drain electrode. The semiconductor device is of a cascode structure, combines the advantages of high GaN switching speed and high SiC breakdown voltage, and effectively improves the working efficiency and the working reliability of the semiconductor device.

Description

Semiconductor device, manufacturing method of semiconductor device and electronic equipment
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor device, a method for manufacturing the semiconductor device, and an electronic apparatus.
Background
The silicon carbide (SiC) power semiconductor can work in a scene of high switching frequency, has the advantages of low power consumption, long service life, high frequency, small volume, light weight and the like, and has strong development potential in the fields of rail transit, communication and photovoltaics.
Several SiC power devices have been commercialized, such as Junction Field-Effect Transistor (JFET), metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and the like. SiC JFETs have higher channel mobility and lower manufacturing process requirements than SiC MOSFETs, which do not contain the preparation of gate oxides. But the normal working reliability of the SiC JFET is low and the safety risk is high.
At present, normally-off operation of the SiC JFET can be realized through a cascode configuration, wherein a low-voltage Si MOSFET is connected between a gate and a power supply of the high-voltage SiC JFET, but the relatively slow switching speed and limited operating temperature of the Si MOSFET device prevent functional implementation of the SiC JFET, thereby affecting the working efficiency and the working reliability of the semiconductor device.
Disclosure of Invention
The invention provides a semiconductor device, a preparation method of the semiconductor device and electronic equipment, so as to improve the working efficiency and the working reliability of the semiconductor device.
The present invention provides a semiconductor device including:
a high voltage depletion silicon carbide junction field effect transistor comprising a first gate, a first drain and a first source;
a low voltage enhancement mode gallium nitride high electron mobility transistor comprising a second gate, a second drain, and a second source;
the first grid electrode is connected with the second source electrode, the first source electrode is connected with the second drain electrode, the source electrode of the semiconductor device is the second source electrode, the grid electrode of the semiconductor device is the second grid electrode, and the drain electrode of the semiconductor device is the first drain electrode.
According to the semiconductor device provided by the invention, the high-voltage depletion type silicon carbide junction field effect transistor comprises a first gate region and a first source region, wherein the first gate is connected with the first gate region, the first source is connected with the first source region, and a first abrupt junction is arranged between the first gate region and the first source region.
According to the semiconductor device provided by the invention, the working mode of the semiconductor device comprises a first forward blocking mode, the low-voltage enhanced gallium nitride high electron mobility transistor is disconnected in the first forward blocking mode, the high-voltage depletion type silicon carbide junction field effect transistor is conducted, and the drain-source voltage of the semiconductor device is the voltage born by the low-voltage enhanced gallium nitride high electron mobility transistor.
According to the semiconductor device provided by the invention, the working mode of the semiconductor device comprises a second forward blocking mode, and in the second forward blocking mode, the low-voltage enhanced gallium nitride high-electron mobility transistor and the high-voltage depletion type silicon carbide junction field effect transistor are disconnected, and the drain-source voltage of the semiconductor device is the voltage born by the low-voltage enhanced gallium nitride high-electron mobility transistor and the high-voltage depletion type silicon carbide junction field effect transistor.
According to the semiconductor device provided by the invention, the working mode of the semiconductor device comprises a first forward conduction mode, and in the first forward conduction mode, both the low-voltage enhanced gallium nitride high-electron mobility transistor and the high-voltage depletion silicon carbide junction field effect transistor are conducted.
According to the present invention, there is provided a semiconductor device further comprising: the first grid electrode is connected with the second source electrode through the first metal connecting structure, and the first source electrode is connected with the second drain electrode through the second metal connecting structure.
The invention also provides a preparation method of the semiconductor device, which comprises the following steps:
sequentially growing a GaN layer, an AlGaN layer and a P-GaN layer in a first area of the SiC substrate;
forming a p-type junction end extension region, a p-type gate contact region, an n-type drift region and an n-type source contact region in a second region of the SiC substrate through photoetching and ion implantation;
etching is carried out in the first area and the second area to respectively form a low-voltage enhanced gallium nitride high electron mobility transistor and a high-voltage depletion silicon carbide junction field effect transistor;
and connecting the first grid electrode of the high-voltage depletion type silicon carbide junction type field effect transistor and the second source electrode of the low-voltage enhancement type gallium nitride high electron mobility transistor, and connecting the first source electrode of the high-voltage depletion type silicon carbide junction type field effect transistor and the second drain electrode of the low-voltage enhancement type gallium nitride high electron mobility transistor to obtain the semiconductor device.
According to the preparation method of the semiconductor device provided by the invention, a first abrupt junction is arranged between the p-type gate contact region and the n-type source contact region.
According to the method for manufacturing a semiconductor device provided by the invention, the connecting the first grid electrode of the high-voltage depletion type silicon carbide junction field effect transistor and the second source electrode of the low-voltage enhancement type gallium nitride high electron mobility transistor, and the connecting the first source electrode of the high-voltage depletion type silicon carbide junction field effect transistor and the second drain electrode of the low-voltage enhancement type gallium nitride high electron mobility transistor comprise the following steps:
and forming a first metal connecting structure and a second metal connecting structure through metal deposition, wherein the first grid electrode and the second source electrode are connected through the first metal connecting structure, and the first source electrode and the second drain electrode are connected through the second metal connecting structure.
The invention also provides an electronic device comprising a semiconductor device as claimed in any one of the preceding claims.
According to the semiconductor device, the preparation method of the semiconductor device and the electronic equipment, through structural design, the high-voltage depletion type silicon carbide junction field effect transistor and the low-voltage enhancement type gallium nitride high electron mobility transistor are integrated in one device, so that the semiconductor device with the common-source common-gate structure is obtained, and the advantages of high GaN switching speed and high SiC breakdown voltage are combined, so that the working efficiency and the working reliability of the semiconductor device can be effectively improved.
Drawings
In order to more clearly illustrate the invention or the technical solutions of the prior art, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a semiconductor device according to the present invention;
fig. 2 is a schematic perspective view of a semiconductor device according to the present invention;
FIG. 3 is a schematic diagram showing a second perspective structure of the semiconductor device according to the present invention;
FIG. 4 is a third schematic perspective view of the semiconductor device according to the present invention;
fig. 5 is a schematic view showing a three-dimensional structure of a semiconductor device according to the present invention;
fig. 6 is a top view of a semiconductor device provided by the present invention;
fig. 7 is a schematic flow chart of a method for manufacturing a semiconductor device according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the embodiments of the present invention, it should be noted that the terms "center," "longitudinal," "transverse," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate or are based on the orientation or positional relationship shown in the drawings, merely to facilitate description of the embodiments of the present invention and to simplify the description, and do not indicate or imply that the devices or elements being referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In describing embodiments of the present invention, it should be noted that, unless explicitly stated and limited otherwise, the terms "coupled," "coupled," and "connected" should be construed broadly, and may be either a fixed connection, a removable connection, or an integral connection, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in embodiments of the present invention will be understood in detail by those of ordinary skill in the art.
In embodiments of the invention, unless expressly specified and limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
A semiconductor device of an embodiment of the present invention is described below with reference to fig. 1 to 6.
The high electron mobility transistor (High Electron Mobility Transistor, HEMT) is a heterojunction field effect transistor with a higher mobility.
The semiconductor device provided by the embodiment of the invention comprises a high-voltage depletion type silicon carbide junction field effect transistor (D-mode SiC JFET) and a low-voltage enhancement type gallium nitride high electron mobility transistor (E-mode GaN HEMT).
The high-voltage depletion type silicon carbide junction field effect transistor comprises a first grid electrode, a first drain electrode and a first source electrode.
The low voltage enhancement mode gallium nitride high electron mobility transistor includes a second gate, a second drain, and a second source.
In this embodiment, the first gate of the high-voltage depletion type silicon carbide junction field effect transistor and the second source of the low-voltage enhancement type gallium nitride high electron mobility transistor are connected, and the source of the semiconductor device in which the high-voltage depletion type silicon carbide junction field effect transistor and the low-voltage enhancement type gallium nitride high electron mobility transistor are integrated is the second source.
The first source of the high voltage depletion silicon carbide junction field effect transistor is connected to the second drain of the low voltage enhancement gallium nitride high electron mobility transistor.
The grid electrode of the semiconductor device integrated by the high-voltage depletion type silicon carbide junction field effect transistor and the low-voltage enhancement type gallium nitride high-electron mobility transistor is a second grid electrode, and the drain electrode is a first drain electrode.
For example, as shown in fig. 1, e-GaN represents the low-voltage enhancement gallium nitride high electron mobility transistor side, and SiC JFET represents the high-voltage depletion silicon carbide junction field effect transistor side.
G JFET 、D JFET And S is JFET The first grid electrode, the first drain electrode and the first source electrode respectively correspond to the high-voltage depletion type silicon carbide junction type field effect transistor.
G GaN 、D GaN And S is GaN The second grid electrode, the second drain electrode and the second source electrode of the low-voltage enhanced gallium nitride high electron mobility transistor are respectively corresponding.
First grid G JFET And a second source S GaN Connected to a first source S JFET And a second drain electrode D GaN The source electrode of the semiconductor device is a second source electrode S GaN The grid electrode of the semiconductor device is a second grid electrode G GaN The drain electrode of the semiconductor device is a first drain electrode D JFET A Cascode structure (i.e., a Cascode type) semiconductor device is formed.
According to the semiconductor device provided by the embodiment of the invention, through structural design, the high-voltage depletion type silicon carbide junction field effect transistor and the low-voltage enhancement type gallium nitride high electron mobility transistor are integrated in one device, so that the semiconductor device with the common-source common-gate structure is obtained, and the advantages of high GaN switching speed and high SiC breakdown voltage are combined, so that the working efficiency and the working reliability of the semiconductor device can be effectively improved.
In some embodiments, a high voltage depletion silicon carbide junction field effect transistor includes a first gate region and a first source region, the first gate being connected to the first gate region, the first source being connected to the first source region, a first abrupt junction being provided between the first gate region and the first source region.
The first gate region is connected to the first gate, and the first gate region is a P-doped silicon carbide region in a high voltage depletion silicon carbide junction field effect transistor, for example, the first gate region may be a p+ SiC region as shown in fig. 6.
A first source region is connected to the first source, the first source region being an N-doped silicon carbide region in a high voltage depletion silicon carbide junction field effect transistor, for example, the first source region being an N + SiC region as shown in fig. 6.
It will be appreciated that the current density increases sharply as the junction between the gate and the channel becomes more abrupt due to saturation of the drain.
In this embodiment, a first abrupt junction is provided between the first gate region and the first source region, and the high-voltage depletion type silicon carbide junction field effect transistor becomes a junction field effect transistor having an abrupt junction between the gate and the channel, which can increase the drain current density and reduce the on-resistance.
The abrupt junction is where the impurity concentration is abrupt from the concentration of acceptor impurities to the concentration of donor impurities at the interface, and the graded junction is where the impurity concentration gradually varies from the acceptor impurity region to the donor impurity region.
According to the space charge distribution condition and the thickness difference of the transition region, the thickness of the abrupt junction is only a few lattice constants, and the thickness of the graded junction can reach a few carrier diffusion lengths.
The breakdown voltage (breakdown voltage, BV) of a junction field effect transistor is determined by the degree to which the barrier of the drain bias to the channel region is reduced. For graded junctions, the gate region of low doping concentration near the channel is affected by the drain bias, which tends to lower the barrier, so narrow channels need to be shielded from high voltages.
For abrupt junctions, a wider channel may block high voltages, a gate region of low doping concentration is narrow, and a first abrupt junction formed between a first gate region and a first source region may increase current density without decreasing breakdown voltage.
The following describes the mode of operation of a high voltage depletion silicon carbide junction field effect transistor and low voltage enhancement gallium nitride high electron mobility transistor integrated cascode semiconductor device.
The operating modes of the semiconductor device may include a first forward blocking mode, a second forward blocking mode, and a first forward conduction mode.
In some embodiments, in a first forward blocking mode of the semiconductor device, the low voltage enhancement mode gallium nitride high electron mobility transistor is turned off, the high voltage depletion mode silicon carbide junction field effect transistor is turned on, and the drain-source voltage of the semiconductor device is the voltage to which the low voltage enhancement mode gallium nitride high electron mobility transistor is subjected.
In this embodiment, the low-voltage enhancement gallium nitride high electron mobility transistor is turned off, the high-voltage depletion silicon carbide junction field effect transistor is turned on, the voltage Vds between the drain and the source (i.e., drain-source voltage) of the semiconductor device satisfies 0< Vds < -vth_jfet, and the voltage vgs=0 between the gate and the source of the semiconductor device.
Wherein, VTH_JFET is the threshold of the turn-on voltage of the high-voltage depletion type silicon carbide junction field effect transistor.
The low-voltage enhancement-mode gan high-electron mobility transistor as a switch is in an off state, and the driving voltage Vgs corresponds to bit 0, and the low-voltage enhancement-mode gan high-electron mobility transistor as a switch has no current, and therefore, the semiconductor device current id=0.
The high-voltage depletion type silicon carbide junction field effect transistor is in an on state, -Vgs_JFET= -Vds_GaN < Vds < -VTH_GaN.
Wherein vgs_jfet is the voltage between the first gate and the first source of the high voltage depletion silicon carbide junction field effect transistor, vds_gan is the voltage between the second drain and the second source of the low voltage enhancement gallium nitride high electron mobility transistor, vth_gan is the turn-on voltage threshold of the low voltage enhancement gallium nitride high electron mobility transistor.
The voltage Vds between the drain and the source of the semiconductor device is the voltage that the low-voltage enhancement gallium nitride high electron mobility transistor in the switch tube receives, i.e. vds_gan is equal to Vds.
In some embodiments, in a second forward blocking mode of the semiconductor device, the low-voltage enhancement mode gallium nitride high electron mobility transistor and the high-voltage depletion mode silicon carbide junction field effect transistor are both off, and the drain-source voltage of the semiconductor device is the voltage to which the low-voltage enhancement mode gallium nitride high electron mobility transistor and the high-voltage depletion mode silicon carbide junction field effect transistor are subjected.
In this embodiment, both the low-voltage enhancement gallium nitride high electron mobility transistor and the high-voltage depletion silicon carbide junction field effect transistor are turned off, the voltage Vds between the drain and the source of the semiconductor device satisfies-vth_jfet < Vds, and the voltage vgs=0 between the gate and the source of the semiconductor device.
Wherein, VTH_JFET is the threshold of the turn-on voltage of the high-voltage depletion type silicon carbide junction field effect transistor.
The voltage Vds between the drain and source of the semiconductor device is continuously rising, keeping the-vth_jfet < Vds, the high voltage depletion silicon carbide junction field effect transistor in an off state, and its driving voltage is lower than the threshold voltage.
The voltage Vds between the drain and the source of the semiconductor device is commonly borne by a low-voltage enhancement gallium nitride high electron mobility transistor and a high-voltage depletion silicon carbide junction field effect transistor.
In some embodiments, in a first forward conduction mode of the semiconductor device, both the low voltage enhancement mode gallium nitride high electron mobility transistor and the high voltage depletion mode silicon carbide junction field effect transistor are on.
In this embodiment, the driving voltage of the semiconductor device, that is, the voltage Vgs between the gate and the source of the semiconductor device is higher than the turn-on voltage threshold vth_gan of the low-voltage enhanced gallium nitride high electron mobility transistor, both the low-voltage enhanced gallium nitride high electron mobility transistor and the high-voltage depletion type silicon carbide junction field effect transistor can be turned on.
In some embodiments, the semiconductor device may further include a first metal connection structure and a second metal connection structure.
The first grid electrode and the second source electrode are connected through a first metal connecting structure, and the first source electrode and the second drain electrode are connected through a second metal connecting structure.
In this embodiment, the connection is made by providing a first metal connection structure when connecting the first gate of the high voltage depletion silicon carbide junction field effect transistor and the second source of the low voltage enhancement gallium nitride high electron mobility transistor.
When the first source electrode of the high-voltage depletion type silicon carbide junction field effect transistor and the second drain electrode of the low-voltage enhancement type gallium nitride high electron mobility transistor are connected, the connection is performed by arranging a second metal connection structure.
In actual implementation, the first metal connection structure and the second metal connection structure may be deposited by metal deposition at corresponding locations between the high voltage depletion silicon carbide junction field effect transistor and the low voltage enhancement gallium nitride high electron mobility transistor.
It should be noted that, metal may not be deposited between the first gate and the first source of the high-voltage depletion type silicon carbide junction field effect transistor so as not to cause a short circuit.
It can be understood that in the structural design of the semiconductor device, design parameters such as length, width, height, doping concentration and the like of the device can be controlled to improve the performance of the semiconductor device.
The embodiment of the invention also provides a preparation method of the semiconductor device, which can be used for preparing the semiconductor device.
As shown in fig. 7, the method for manufacturing a semiconductor device according to the embodiment of the present invention includes:
step 710, sequentially growing a GaN layer, an AlGaN layer and a P-GaN layer in a first region of the SiC substrate.
As shown in fig. 2, a GaN layer, an AlGaN layer and a P-GaN layer are grown in sequence from a SiC substrate upwards, wherein the AlGaN layer is a barrier layer, the GaN layer is a buffer layer, the GaN layer and the AlGaN layer have certain lattice mismatch, the size of the lattice mismatch is related to the Al composition, and the stress of the barrier layer can be reduced by adjusting the Al composition, so that the reliability of the device is improved.
In this step, a GaN layer, an AlGaN layer, and a P-GaN layer are grown in a first region of the SiC substrate for subsequent etching to obtain a low voltage enhancement gallium nitride high electron mobility transistor.
And step 720, forming a p-type junction end extension region, a p-type gate contact region, an n-type drift region and an n-type source contact region in a second region of the SiC substrate through photoetching and ion implantation.
Wherein the second region is a region on the SiC substrate where the GaN layer, the AlGaN layer, and the P-GaN layer are not grown.
In this embodiment, the p-type junction termination extension region, the p-type gate contact region, the n-type drift region, and the n-type source contact region are formed by photolithography and ion implantation.
As shown in fig. 3, the P-type junction extension region is a region corresponding to P-SiC, the P-type gate contact region is a region corresponding to p+sic, the N-type drift region is a region corresponding to N-SiC, and the N-type source contact region is a region corresponding to n+sic.
The p-type gate contact region and the n-type source contact region are used for forming a first gate and a first source of the high-voltage depletion type silicon carbide junction field effect transistor.
And 730, etching the first region and the second region to respectively form a low-voltage enhanced gallium nitride high electron mobility transistor and a high-voltage depletion silicon carbide junction field effect transistor.
Etching is carried out in the first area and the second area, a groove structure is formed through dry etching, a low-voltage enhanced gallium nitride high-electron mobility transistor is etched in the first area, and a high-voltage depletion type silicon carbide junction field effect transistor is etched in the second area.
In actual implementation, as shown in fig. 4, when etching is performed on the first region and the second region, etching is performed on a connection region of the low-voltage enhanced gallium nitride high electron mobility transistor and the high-voltage depletion silicon carbide junction field effect transistor, so that subsequent connection is facilitated.
Wherein SiO between the P-type gate contact region (region corresponding to P+SiC) and the N-type source contact region (region corresponding to N+SiC) 2 Is a masking film.
Step 740, connecting the first gate of the high-voltage depletion type silicon carbide junction field effect transistor and the second source of the low-voltage enhancement type gallium nitride high electron mobility transistor, and connecting the first source of the high-voltage depletion type silicon carbide junction field effect transistor and the second drain of the low-voltage enhancement type gallium nitride high electron mobility transistor to obtain the semiconductor device.
A first source is formed in a region corresponding to n+sic close to the first region in the second region (i.e., an N-type source contact region), a first gate is formed in a region corresponding to p+sic (i.e., a P-type gate contact region), and a first drain is formed in a region corresponding to n+sic distant from the first region in the second region.
In this embodiment, the low-voltage enhancement gallium nitride high-electron mobility transistor including the second gate electrode, the second drain electrode, and the second source electrode is obtained by etching at a portion of the first region.
As shown in FIG. 5, a first gate G JFET And a second source S GaN Connected to a first source S JFET And a second drain electrode D GaN The source electrode (corresponding to S shown in FIG. 5) of the semiconductor device is connected to the second source electrode S GaN The gate of the semiconductor device (corresponding to G shown in FIG. 5) is the second gate G GaN The drain electrode (corresponding to D shown in FIG. 5) of the semiconductor device is the first drain electrode D JFET A Cascode structure (i.e., a Cascode type) semiconductor device is formed.
According to the preparation method of the semiconductor device, the high-voltage depletion type silicon carbide junction field effect transistor and the low-voltage enhancement type gallium nitride high electron mobility transistor are integrated into one device through structural design, so that the semiconductor device with the common-source common-gate structure is obtained, and the advantages of high GaN switching speed and high SiC breakdown voltage are combined, so that the working efficiency and the working reliability of the semiconductor device can be effectively improved.
In some embodiments, a first abrupt junction is provided between the p-type gate contact region and the n-type source contact region.
The high-voltage depletion type silicon carbide junction field effect transistor comprises a first gate region and a first source region, wherein the first gate is connected with the first gate region, and the first source is connected with the first source region.
The first gate region is a P-doped silicon carbide region, i.e., a P-type gate contact region, in a high voltage depletion silicon carbide junction field effect transistor.
The first source region is an N-doped silicon carbide region, i.e., an N-type source contact region, in a high voltage depletion silicon carbide junction field effect transistor.
In this embodiment, a first abrupt junction is formed between the p-type gate contact region and the n-type source contact region, the concentration of acceptor impurities in the p-type gate contact region is abruptly changed from the concentration of donor impurities in the n-type source contact region, and the high-voltage depletion type silicon carbide junction field effect transistor becomes a junction field effect transistor having an abrupt junction between the gate and the channel, so that the drain current density can be increased and the on-resistance can be reduced.
In some embodiments, step 740, connecting the first gate of the high voltage depletion mode silicon carbide junction field effect transistor and the second source of the low voltage enhancement mode gallium nitride high electron mobility transistor, and connecting the first source of the high voltage depletion mode silicon carbide junction field effect transistor and the second drain of the low voltage enhancement mode gallium nitride high electron mobility transistor may comprise:
and forming a first metal connecting structure and a second metal connecting structure through metal deposition, wherein the first grid electrode and the second source electrode are connected through the first metal connecting structure, and the first source electrode and the second drain electrode are connected through the second metal connecting structure.
In this embodiment, a first metal connection is deposited between a first gate of the high voltage depletion silicon carbide junction field effect transistor and a second source of the low voltage enhancement gallium nitride high electron mobility transistor, connecting the first gate and the second source.
A second metal connection structure is deposited between the first source of the high-voltage depletion silicon carbide junction field effect transistor and the second drain of the low-voltage enhancement gallium nitride high electron mobility transistor to connect the first source and the second drain.
It should be noted that, metal may not be deposited between the first gate and the first source of the high-voltage depletion type silicon carbide junction field effect transistor so as not to cause a short circuit.
The embodiment of the invention also provides electronic equipment comprising the semiconductor device.
The semiconductor device of the electronic equipment is a device with a common-source and common-gate structure of a high-voltage depletion type silicon carbide junction field effect transistor and a low-voltage enhancement type gallium nitride high-electron mobility transistor set, combines the advantages of high GaN switching speed and high SiC breakdown voltage, and can effectively improve the working efficiency and the working reliability of the semiconductor device.
The electronic device may be a terminal, or may be other devices than a terminal. By way of example, the electronic device may be a mobile phone, tablet computer, notebook computer, palm computer, vehicle-mounted electronic device, mobile internet appliance (Mobile Internet Device, MID), augmented reality (augmented reality, AR)/Virtual Reality (VR) device, robot, wearable device, ultra-mobile personal computer, UMPC, netbook or personal digital assistant (personal digital assistant, PDA), etc., but may also be a server, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (TV), teller machine or self-service machine, etc., and the embodiments of the present invention are not limited in particular.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A semiconductor device, comprising:
a high voltage depletion silicon carbide junction field effect transistor comprising a first gate, a first drain and a first source;
a low voltage enhancement mode gallium nitride high electron mobility transistor comprising a second gate, a second drain, and a second source;
the first grid electrode is connected with the second source electrode, the first source electrode is connected with the second drain electrode, the source electrode of the semiconductor device is the second source electrode, the grid electrode of the semiconductor device is the second grid electrode, and the drain electrode of the semiconductor device is the first drain electrode.
2. The semiconductor device of claim 1, wherein the high voltage depletion mode silicon carbide junction field effect transistor comprises a first gate region and a first source region, the first gate being connected to the first gate region, the first source being connected to the first source region, a first abrupt junction being provided between the first gate region and the first source region.
3. The semiconductor device of claim 1, wherein an operating mode of the semiconductor device comprises a first forward blocking mode in which the low-voltage enhancement mode gallium nitride high electron mobility transistor is off and the high-voltage depletion mode silicon carbide junction field effect transistor is on, and wherein a drain-source voltage of the semiconductor device is a voltage to which the low-voltage enhancement mode gallium nitride high electron mobility transistor is subjected.
4. The semiconductor device of claim 1, wherein an operating mode of the semiconductor device comprises a second forward blocking mode in which the low voltage enhancement mode gallium nitride high electron mobility transistor and the high voltage depletion mode silicon carbide junction field effect transistor are both off, and a drain-source voltage of the semiconductor device is a voltage to which the low voltage enhancement mode gallium nitride high electron mobility transistor and the high voltage depletion mode silicon carbide junction field effect transistor are subjected.
5. The semiconductor device of claim 1, wherein an operating mode of the semiconductor device comprises a first forward conduction mode in which both the low voltage enhancement gallium nitride high electron mobility transistor and the high voltage depletion silicon carbide junction field effect transistor are on.
6. The semiconductor device according to any one of claims 1 to 5, further comprising: the first grid electrode is connected with the second source electrode through the first metal connecting structure, and the first source electrode is connected with the second drain electrode through the second metal connecting structure.
7. A method for manufacturing the semiconductor device according to any one of claims 1 to 6, comprising:
sequentially growing a GaN layer, an AlGaN layer and a P-GaN layer in a first area of the SiC substrate;
forming a p-type junction end extension region, a p-type gate contact region, an n-type drift region and an n-type source contact region in a second region of the SiC substrate through photoetching and ion implantation;
etching is carried out in the first area and the second area to respectively form a low-voltage enhanced gallium nitride high electron mobility transistor and a high-voltage depletion silicon carbide junction field effect transistor;
and connecting the first grid electrode of the high-voltage depletion type silicon carbide junction type field effect transistor and the second source electrode of the low-voltage enhancement type gallium nitride high electron mobility transistor, and connecting the first source electrode of the high-voltage depletion type silicon carbide junction type field effect transistor and the second drain electrode of the low-voltage enhancement type gallium nitride high electron mobility transistor to obtain the semiconductor device.
8. The method of manufacturing a semiconductor device according to claim 7, wherein a first abrupt junction is provided between the p-type gate contact region and the n-type source contact region.
9. The method of manufacturing a semiconductor device according to claim 7 or 8, wherein the connecting the first gate of the high-voltage depletion mode silicon carbide junction field effect transistor and the second source of the low-voltage enhancement mode gallium nitride high electron mobility transistor and connecting the first source of the high-voltage depletion mode silicon carbide junction field effect transistor and the second drain of the low-voltage enhancement mode gallium nitride high electron mobility transistor comprises:
and forming a first metal connecting structure and a second metal connecting structure through metal deposition, wherein the first grid electrode and the second source electrode are connected through the first metal connecting structure, and the first source electrode and the second drain electrode are connected through the second metal connecting structure.
10. An electronic device comprising the semiconductor device according to any one of claims 1 to 6.
CN202211413679.8A 2022-11-11 2022-11-11 Semiconductor device, manufacturing method of semiconductor device and electronic equipment Pending CN115995463A (en)

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