CN115995254A

CN115995254A - Complete nonvolatile Boolean logic circuit based on 1T1R array and control method thereof

Info

Publication number: CN115995254A
Application number: CN202211513659.8A
Authority: CN
Inventors: 王兴晟; 宋玉洁; 马颖昊; 缪向水
Original assignee: Huazhong University of Science and Technology
Current assignee: Huazhong University of Science and Technology
Priority date: 2022-11-29
Filing date: 2022-11-29
Publication date: 2023-04-21
Also published as: WO2024113438A1

Abstract

The invention discloses a complete nonvolatile Boolean logic circuit based on a 1T1R array and a control method thereof, which belong to the technical field of microelectronic devices and are used for carrying out logic operation on an input logic value P and/or a logic value Q; wherein, memristor M ₁ The input resistance state of (2) is determined by the logic input Q, and the input voltage is fixed at-V ₀ Memristor M ₂ Is fixed to V ₁ The input voltage C on the word line WL is determined by the type of logic operation and the logic value Q, P; the input voltage D on the source control terminal is determined by the logic operation type, the logic value P and the voltage C, and the memristor M ₂ The resistance state of (2) is used as the output of the calculation result; the invention fully utilizes the switching characteristics of the transistors in the 1T1R structure on the logic algorithm, and can control the steps for realizing the complete Boolean logic function to two steps by dynamically configuring the word line WL and the input voltage on the source control end, thereby improving the nonvolatile Boolean logic operation efficiency with fewer operation steps and a fixed circuit topological structure.

Description

Complete nonvolatile Boolean logic circuit based on 1T1R array and control method thereof

Technical Field

The invention belongs to the technical field of microelectronic devices, and particularly relates to a complete nonvolatile Boolean logic circuit based on a 1T1R array and a control method thereof.

Background

Modern computers are based primarily on von neumann architecture. In this architecture, data is obtained from a storage unit, transferred to a calculation unit, and transferred to a unit to be stored after calculation is completed. Today, the operating speeds of both processors and memories have reached a fairly high level, and the bus transfer connecting these two parts has become a bottleneck for further speed improvement, with frequent data transfers taking up a significant portion of the time and power consumption in the data processing process. The advent of the big data age, computers faced more computationally intensive tasks, aggravated the severity of this bottleneck problem, limited the development of modern computers, referred to as storage walls. In-memory computing is a very potential solution. Similar to human brain, in-memory computing aims at realizing coexistence of storage and computing in the same physical structure, so that energy consumption and clock cycle can be greatly reduced, parallel operation is realized, and development and application space is huge.

Memristors are used as a novel nonvolatile memory device, and become powerful candidate devices of an in-memory computing architecture due to the characteristic that the memristors can still maintain a resistance state after power is removed. The logic implementation based on the memristor is mainly divided into three types, wherein in the first implementation method, the input and the output are both expressed in the form of the resistance state of the memristor, the scheme is favorable for logic cascade but uses more devices, and the number of the devices and the operation complexity are both increased along with the increase of the calculation complexity; in the second type of implementation method, the input is added at two ends of the memristor in a voltage form, the output is expressed in a resistance form, the number of devices used in the scheme is greatly reduced, the number of operation steps is also less, but a logic cascade must introduce a digital-to-analog conversion process, and a complex peripheral circuit is required for supporting; in the third type of implementation method, the input is voltage applied to one end of the memristor and the initial resistance of the memristor respectively, the output is expressed in the memristor resistance state form, the number of devices used in the method is small, the number of operation steps is small, the logic linkage is easy, but the logic calculation is destructive and serial, the integrity of input information is not protected, and the parallelism of calculation is improved. At present, most schemes are based on array demonstration composed of simple memristors, and the structure has the advantages of small area and high integration level, but is extremely easy to generate electric leakage, so that calculation errors or unsuccessful calculation are caused, and the realization of parallel processing of large-scale data is not facilitated. Therefore, it is necessary to propose a realization scheme with a fixed circuit topology and complete logic, which can easily realize logic linkage without damaging the integrity of input data while using the fewest possible operation steps, increase the parallelism of data calculation, reduce the probability of occurrence of electric leakage, increase the calculation accuracy, and output the calculation result of a digital domain on the premise of saving resources as much as possible.

Disclosure of Invention

Aiming at the defects or improvement demands of the prior art, the invention provides a complete nonvolatile Boolean logic circuit based on a 1T1R array and a control method thereof, which are used for solving the technical problem that the prior art cannot improve the nonvolatile Boolean logic operation efficiency with a small operation step number and a fixed circuit topology structure.

In order to achieve the above object, the present invention provides a complete nonvolatile boolean logic operation circuit based on a 1T1R array, for performing logic operation on an input logic value P and/or an input logic value Q;

the logic circuit includes: control unit, memristor M ₁ Memristor M ₂ A first transistor, a second transistor, and a resistor;

memristor M ₁ Positive electrode of (a) and bit line BL ₀ The negative electrode is connected with the drain electrode end of the first transistor; memristor M ₂ Positive electrode of (a) and bit line BL ₁ The negative electrode is connected with the drain electrode end of the second transistor; the gates of the first transistor and the second transistor are connected to the same word line WL, and the sources are connected to the same source line SL; the sources of the first transistor and the second transistor are led out through a source line SL and then connected with a first end of a resistor, and a second end of the resistor is used as a source control end; the first transistor and the second transistor are the same; memristor M ₁ And memristor M ₂ The same, and the initial state is the high resistance state;

the control unit is used for performing logic operation through the bit line BL ₀ Memristor M ₁ Applying voltage-V ₀ Through bit line BL ₁ Memristor M ₂ Applying a voltage V ₁ Applying a voltage C on the word line WL, applying a voltage D on the source control terminal, and reading the memristor M ₂ The resistance state of (2) is the logic operation result;

wherein, when the logic circuit executes the operation related to the logic value Q, the control unit is further used for driving the memristor M before the logic operation ₁ Setting the resistance state corresponding to the logic value Q; the operations related to the logical value Q include an operation of performing a logical operation on the logical value P and the logical value Q and an operation of performing a logical operation on only the logical value Q;

V ₀ and V ₁ Simultaneously satisfies: v (V) _set /2≤V ₀ <V _set ，V _set /2≤V ₁ <V _set And V is ₀ +V ₁ ≥V；V _set Is memristor M ₁ Or memristor M ₂ A threshold value for switching from a high resistance state to a low resistance state; v is memristor M ₁ Or memristor M ₂ The upper limit of the fluctuation range of the threshold voltage variation;

the value of the voltage C is determined by the logic operation type and the logic value Q, P, and the value of the voltage D is determined by the logic operation type, the logic value P and the voltage C.

Further preferably, V ₀ Take the value of

V ₁ The value is +.>

Further preferably, the memristor M described above ₁ And memristor M ₂ Both include a high resistance state and a low resistance state; the high resistance state corresponds to a logic value of "0" and the low resistance state corresponds to a logic value of "1".

Further preferably, when logically operatingWhen the type is true logical operation, the value of the voltage C is V _on The value of the voltage D is 0V;

when the type of the logic operation is false logic operation, the value of the voltage C is 0V, and the value of the voltage D is 0V;

when the type of logical operation is P logical operation: if the logic value P is 1, the voltage C takes on the value V _on At this time, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value P is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is a Q logical operation: if the logic value Q is 1, the voltage C takes on the value V _on The method comprises the steps of carrying out a first treatment on the surface of the If the logic value Q is 0, the value of the voltage C is 0V; the value of the voltage D is 0V;

when the type of logical operation is a non-P logical operation: if the logic value P is 1, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V; if the logic value P is 0, the voltage C takes on the value V _on At this time, the voltage D takes on a value of-2V ₂ ；

When the type of logical operation is a non-Q logical operation: if the logic value Q is 1, the voltage C takes on the value V _on At this time, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value Q is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

When the type of logical operation is an AND logical operation: if the logical operation result of the expression QP 0 is 1, the value of the voltage C is V _on The method comprises the steps of carrying out a first treatment on the surface of the If the logical operation result of the expression QP 0 is 0, the value of the voltage C is 0V; the value of the voltage D is 0V;

when the type of logical operation is a nand logical operation: if an expression is selected

The logical operation result of (1) is that the voltage C takes the value of V _on At this time, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the expression +.>

If the logic operation result of (a) is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is an or logical operation: in the case that the logical operation result of the selection expression Q1:P is 1, the voltage C takes on a value of V _on At this time, if the logic value P takes on 1, the voltage D takes on-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value P is 0, the value of the voltage D is 0V; under the condition that the logical operation result of the selection expression Q1:P is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is a nor logical operation: if an expression is selected

The logical operation result of (1) is that the voltage C takes the value of V _on At this time, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If expression Q is selected? />

P is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

When the type of logical operation is a materialized logical operation: in selecting an expression

In the case of 1 logical operation result, the voltage C takes on the value V _on At this time, if the logic value P is 1, the voltage D is 0V; if the logic value P is 0, the voltage D is-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the In the selection expression +.>

When the logical operation result of (a) is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is a negative parenchymal implication logical operation: if the logical operation result of the selection expression Q0:P is 1, the value of the voltage C is V _on At this time, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logical operation result of the expression Q0:P is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the logic is operated onThe type is the anti-parenchymal implication logical operation: if the logical operation result of the expression QP 1 is 1, the value of the voltage C is V _on At this time, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logical operation result of the expression QP 1 is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is an anti-negative parenchymal implication logical operation: if an expression is selected

The logical operation result of (1) is that the voltage C takes the value of V _on The method comprises the steps of carrying out a first treatment on the surface of the If the expression +.>

If the logic operation result of (a) is 0, the value of the voltage C is 0V; the value of the voltage D is 0V;

when the type of logical operation is an exclusive or logical operation: in selecting an expression

In the case of 1 logical operation result, the voltage C takes on the value V _on At this time, if the logic value P takes on 1, the voltage D takes on-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value P is 0, the value of the voltage D is 0V; in the selection expression +.>

when the type of logical operation is an exclusive nor logical operation: in selecting an expression

wherein V is _on A voltage operating in a linear region for the first transistor or the second transistor; the first transistor and the second transistor are NMOS transistors; v (V) ₂ ＝V-V ₁ 。

Further preferably, V ₂ Take the value of

Further preferably, the resistance of the resistor is between the magnitude of the memristor M ₁ Or memristor M ₂ Between the high resistance and the low resistance; the resistance value of the resistor is

Wherein R is _H Is memristor M ₁ Or memristor M ₂ High resistance state resistance value R _L Is memristor M ₁ Or memristor M ₂ Low resistance state resistance value of (a).

Further preferably, the complete non-volatile boolean logic circuit further comprises: a reading circuit; wherein the reading circuit includes: a transmission gate connected to the first end of the resistor, and a comparator connected to the output end of the transmission gate for reading the memristor M ₂ Is a resistance state of (a).

In a second aspect, the present invention provides a control method of a complete non-volatile boolean logic circuit, applied to a control unit in the complete non-volatile boolean logic circuit provided in the first aspect of the present invention, comprising the following steps:

s1, memristor M ₁ And memristor M ₂ All initialize to a high resistance state;

s2, judging whether the current operation is the operation related to the logic value Q, if so, using the memristor M ₁ Setting the resistance state corresponding to the logic value Q; wherein the operations related to the logical value Q include an operation of performing a logical operation on the logical value P and the logical value Q and an operation of performing a logical operation on only the logical value Q;

s3, through bit line BL ₀ Memristor M ₁ Applying a voltage _- V ₀ Through bit line BL ₁ Memristor M ₂ Applying a voltage V ₁ Applying a voltage C on the word line WL, applying a voltage D on the source control terminal, and reading the memristor M ₂ The resistance state of (2) is the logic operation result;

wherein V is ₀ And V ₁ Simultaneously satisfies: v (V) _set /2≤V ₀ <V _set ，V _set /2≤V ₁ <V _set And V is ₀ +V ₁ ≥V；V _set Is memristor M ₁ Or memristor M ₂ A threshold value for switching from a high resistance state to a low resistance state; v is memristor M ₁ Or memristor M ₂ The upper limit of the fluctuation range of the threshold voltage variation;

Further preferably, when the type of logical operation is a true logical operation, the voltage C takes a value of V _on The value of the voltage D is 0V;

When the type of logical operation is a non-Q logical operation: if the logic value Q is1, the voltage C takes on the value V _on At this time, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value Q is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the logic operationThe type of (1) is a substance implication logic operation: in selecting an expression

When the type of logical operation is an anti-parenchymal implication logical operation: if the logical operation result of the expression QP 1 is 1, the value of the voltage C is V _on At this time, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logical operation result of the expression QP 1 is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

In a third aspect, the present invention provides a bitwise logic cascading method based on the complete nonvolatile boolean logic circuit, which includes:

and taking the result of the previous logic operation obtained by the operation according to the control method of the second aspect as a new input logic value Q, and operating again according to the control method of the second aspect, thereby realizing bitwise logic cascading.

In a fourth aspect, the present invention provides a complete non-volatile boolean logic parallel operation circuit, which includes a plurality of complete non-volatile boolean logic operation circuits provided in the first aspect of the present invention;

memory of each complete nonvolatile Boolean logic operation circuitResistor M ₁ The positive electrodes of (a) are all connected to the same bit line BL ₀ Memristor M ₂ The positive electrodes of (a) are all connected to the same bit line BL ₁ And the logic operation method is used for realizing a plurality of logic operations in parallel in the same logic calculation pulse period.

In general, through the above technical solutions conceived by the present invention, the following beneficial effects can be obtained:

1. The invention provides a complete nonvolatile Boolean logic operation circuit based on a 1T1R array, which is used for carrying out logic operation on an input logic value P and/or a logic value Q; the logic circuit mainly comprises a memristor, a transistor and a resistor, wherein the memristor M ₁ The input resistance state of (2) is determined according to the logic input Q, and the input voltage is fixed at-V ₀ ，M ₂ Is fixed to V ₁ The input voltage C on the word line WL is determined by the type of logic operation and the logic value Q, P; the input voltage D on the source control terminal is determined by the logic operation type, the logic value P and the voltage C, and the memristor M ₂ The resistance state of (2) is used as the output of the calculation result; the invention fully utilizes the switching characteristics of the transistors in the 1T1R structure on the logic algorithm, and can control the steps for realizing the complete Boolean logic function to two steps by dynamically configuring the input voltages on the word line WL and the source control end of the circuit, thereby improving the nonvolatile Boolean logic operation efficiency with fewer operation steps and a fixed circuit topology structure.

2. When the real-time output result is required to be obtained, the complete nonvolatile Boolean logic operation circuit does not need to increase the reading step of the traditional scheme, can realize the current on the sampling constant value resistor by starting the transmission gate switch, can synchronously obtain the calculation result of the digital domain by comparing the current with the fixed reference voltage value, and is beneficial to the realization of the construction of a digital-analog hybrid system.

3. The complete nonvolatile Boolean logic operation circuit provided by the invention has the advantage that the memristor M is arranged in the operation process of logic calculation ₁ The resistance state of the device is not changed, and the whole operation process is non-destructive, so that the integrity of input information is protected.

4. The invention provides a bitwise logic cascading method based on the complete nonvolatile Boolean logic circuit, which can directly take the result obtained by the previous logic calculation as the input of the next logic operation, has simple and feasible logic cascading, and is beneficial to realizing more complex logic functions.

5. The invention provides a complete nonvolatile Boolean logic parallel operation circuit, which comprises a plurality of complete nonvolatile Boolean logic operation circuits, and memristors M of the complete nonvolatile Boolean logic operation circuits ₁ The positive electrodes of (a) are all connected to the same bit line BL ₀ Memristor M ₂ The positive electrodes of (a) are all connected to the same bit line BL ₁ On bit line BL ₀ Fixed input voltage-V ₀ Bit line BL ₁ Fixed input voltage V ₁ Only the voltages C and D input on the word lines WL and the source control terminal of each row are controlled respectively, so that a plurality of logic operations can be realized in parallel in the same logic calculation pulse period. The invention has the advantages that the number of required operation steps is small, the problem of misoperation or unsuccessful operation caused by leakage current in large-scale parallel processing can be completely avoided by adopting the 1T1R array, and because the BL end excitation is fixed, a plurality of logic operations can be realized simultaneously in one clock period, the calculation parallelism and efficiency are greatly improved, and the advantage of calculating by using a nonvolatile device is increased.

Drawings

FIG. 1 is a schematic diagram of a complete nonvolatile Boolean logic circuit based on a 1T1R array according to the present invention;

FIG. 2 is a schematic diagram of a memristor-based 1T1R structure used in a complete non-volatile Boolean logic circuit and a 100-cycle test chart of I-V characteristics thereof; wherein, (a) is a 1T1R structural schematic diagram; (b) an I-V characteristic 100 cycle test chart of a 1T1R structure;

FIG. 3 is a schematic diagram of a complete nonvolatile Boolean logic circuit with a read circuit according to the present invention;

FIG. 4 is a schematic diagram of a complete non-volatile Boolean logic parallel operation circuit provided by the invention;

FIG. 5 is a simulation result of the four-bit input bit-wise exclusive OR logic calculation and voltage relationships configured by WL and SL terminals according to the input;

FIG. 6 shows the memristor M as the save output result for each row provided by the present invention ₂ A schematic diagram of a change result of the resistance state in the logic calculation process;

FIG. 7 is a schematic diagram of a memristor M for each row output according to the present disclosure ₂ Schematic diagram of change result of voltage drop at two ends in logic calculation process;

fig. 8 is a schematic diagram of a digital domain calculation result output in a high-low level form according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.

To achieve the above object, in a first aspect, as shown in fig. 1, the present invention provides a complete nonvolatile boolean logic operation circuit based on a 1T1R array, for performing a logic operation on an input logic value P and/or an input logic value Q;

memristor M ₁ Positive electrode of (a) and bit line BL ₀ The negative electrode is connected with the drain electrode end of the first transistor; memristor M ₂ Positive electrode of (a) and bit line BL ₁ The negative electrode is connected with the drain electrode end of the second transistor; the gates of the first transistor and the second transistor are connected to the same word line WL, and the sources are connected to the same source line SL; the sources of the first transistor and the second transistor are led out through a source line SL and then connected with a first end of a resistor, and a second end of the resistor is used as a source control end; the first transistor and the second transistor are the same; memristor M ₁ And memristor M ₂ Identical, andthe initial states are all high-resistance states;

it should be noted that the excitation signals adopted in the logic operation process are all voltage pulse signals; to meet the requirement of logic operation, V ₀ And V ₁ The following should be satisfied at the same time: v (V) _set /2≤V ₀ <V _set ，V _set /2≤V ₁ <V _set And V is ₀ +V ₁ ≥V；V _set Is memristor M ₁ Or memristor M ₂ A threshold value for switching from a high resistance state to a low resistance state; v is memristor M ₁ Or memristor M ₂ The upper limit of the fluctuation range of the threshold voltage variation; in an alternative embodiment, v=e _set +3RMS _set E _set Is V (V) _set Is the average value of (2); RMS (root mean square) _set Is V (V) _set Is a mean square error of (c). Specifically, V ₁ The voltage amplitude is between V _set And V is equal to _set Between/2 can be V ₁ Insufficient to change the memristor in the original high-resistance state to the low-resistance state; meanwhile, when voltage drops larger than or equal to the voltage V are added to the two ends of the memristor, the memristor can be ensured to generate resistance state change; because the BL end has almost no voltage drop loss, the SL end has more voltage loss, and according to the simulation test result, V ₀ Preferably the value of (a)

V ₁ Preferably +.>

Taking an NMOS transistor at a 0.18 process node as an example, fig. 2 shows a schematic diagram of a 1T1R structure based on memristors used in the complete nonvolatile boolean logic operation circuit and an I-V characteristic 100-cycle test chart; wherein, the figure (a) is a 1T1R structure schematic diagram; FIG. b is a graph showing 100 cycles of I-V characteristics of a 1T1R structure.

Specifically, when 2.5V is applied to the grid electrode of the transistor, the source electrode and the substrate are connected with GND, the positive electrode of the memristor is applied with forward voltage, and the resistance value of the memristor is set to a low resistance state; when a voltage of 3.3V is applied to the gate of the transistor, a negative voltage V is applied to the positive electrode of the memristor _reset When the source electrode and the substrate are connected with GND, the resistance value of the memristor is set to a high resistance state; the memristor can be switched between a high-resistance state and a low-resistance state by controlling the voltages of the gate terminal and the memristor terminal of the transistor. The high resistance state of the memristor corresponds to a logic value of 0, and the low resistance state of the memristor corresponds to a logic value of 1.

Preferably, in the logic circuit provided by the invention, the switching ratio of the memristor is in the range of [10, 500], and the large switching ratio can enable the low resistance state, the high resistance state and the resistance value of the constant value resistor R of the memristor to be obviously distinguished, so that the logic calculation based on the voltage division relation is facilitated.

Further, the resistance of the resistor is between that of the memristor M ₁ Or memristor M ₂ Between the high resistance and the low resistance; in some alternative embodiments, the fixed resistor takes on a value of

The circuit mainly plays a role in dividing voltage which can distinguish the high resistance value and the low resistance value of the memristor. Considering that the memristor has a certain fluctuation range in both the high-resistance state and the low-resistance state, the selection of the constant-value resistor R can be slightly larger than +.>

As a result, better guarantees are provided for the reliability of the circuit.

Further, in an alternative embodiment, as shown in fig. 3, the complete non-volatile boolean logic circuit further includes: a reading circuit; wherein the reading circuit includes: a transmission gate connected to the first end of the resistor, and a comparator connected to the output end of the transmission gate for reading the memristor M ₂ Is a resistance state of (a). The invention provides a logic calculation reading circuit, which can acquire the output result of a digital domain in real time by sampling the node voltage and current of a constant value resistor end in logic calculation pulse and adding a comparator into the circuit. Specifically, by BL ₀ For M ₁ Applying a constant operating voltage pulse amplitude a= -V ₀ By BL ₁ For M ₂ Applying constant operating voltage pulse amplitude b=v ₁ The on and off states of the transistor are controlled by the voltage C on the control terminal WL, the voltage D is applied to one end of the given value resistor of the SL terminal, the corresponding logic calculation operation is completed together, and the calculation result is stored in the output memristor M in the form of a resistance state ₂ In (a) and (b); meanwhile, in the reading operation process, whether a digital output result is obtained is selected by controlling the enabling end of the transmission gate, the reference voltage of the comparator is a fixed voltage value in all types of logic calculation, and all pins in the empty state float. The input voltage of the comparator is the source line voltage, the memristor lower electrode is connected through the transistor, and the voltage V is applied through the word line WL _on The voltage drop of the node is required to be reduced to be more than or equal to V/3 memristor before the node becomes resistance according to the memristor state inversion principle so as to change from high resistance to low resistance, so that the reference voltage can be fixedly set to be-V ₂ And/2, when the input voltage of the comparator is smaller than-V ₂ And (2) when the output level of the comparator is turned over, the rising edge is sampled by a trigger of the external digital circuit D to obtain a digital domain result. The reference voltage can also be fixed to be V ₂ 2 because memristor M after becoming low-resistance ₂ Memristor M which pulls the sampling node potential high and maintains high resistance ₂ Without this effect, thus set as V ₂ The two state changes of the memristor can be distinguished as well by/2.

The invention provides a complete nonvolatile Boolean logic implementation method based on a memristor, which only needs 2 steps of operations to complete 16 logic calculations, meets the requirements of easy realization of logic linkage and protection of the integrity of input information in the calculation process, and is specifically shown in a table 1:

when the type of logical operation is TRUE logical operation (TRUE), the voltage C at the WL input is a fixed voltage V no matter what input P, Q is _on The voltage D input by the SL terminal is a fixed voltage pulse amplitude value 0, and the memristor M ₁ The resistance state of (2) is determined according to the input Q;

when the type of logic operation is FALSE logic operation (FALSE), the voltage C at WL input is 0V at a fixed voltage, the voltage D at SL input is 0V at a fixed voltage, and the memristor M is no matter what input P, Q ₁ The resistance state of (2) is determined according to the input Q;

when the type of logical operation is P logical operation (COPYP), V is selected with the result of the selection expression P _on Or 0V is applied to the WL terminal (when the expression results in 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL configures 0V, SL is 0V, if WL configures V _on The SL end is a fixed voltage pulse amplitude of-2V ₂ . Specifically, if the logic value P is 1, the voltage C takes on the value V _on At this time, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value P is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is Q logical operation (COPY Q): selecting V with the result of selecting expression Q _on Or 0V is applied to the WL terminal (when the expression results in 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL configures 0V, SL is 0V, if WL configures V _on The SL end is provided with a fixed voltage pulse amplitude value of 0 and a memristor M ₁ Depending on the Q input. Specifically, if the logic value Q is 1, the voltage C takes on the value V _on The method comprises the steps of carrying out a first treatment on the surface of the If the logic value Q is 0, the value of the voltage C is 0V; the value of the voltage D is 0V;

when the type of logical operation is a non-P logical operation (NOT P): to select the expression

Result of (2) selecting V _on Or 0V is applied to the WL terminal (when the expression results in 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL configures 0V, SL is 0V, if WL configures V _on The SL end is fixed pulse amplitude-2V ₂ . Specifically, if the logic value P is 1, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V; if the logic value P is 0, the voltage C takes on the value V _on At this time, the voltage D takes on a value of-2V ₂ ；

When the type of logical operation is a non-Q logical operation (NOT Q): selecting V with the result of selecting expression Q _on Or 0V is applied to the WL terminal (when the expression results in 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL configures 0V, SL is 0V, if WL configures V _on The SL end is a fixed voltage pulse amplitude of-2V ₂ Memristor M ₁ Depending on the input Q. Specifically, if the logic value Q is 1, the voltage C takes on the value V _on At this time, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value Q is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is an AND logical operation (AND): selecting V with the result of selecting expression QP 0 _on Or 0V is applied to the WL terminal (when the expression results in 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL configures 0V, SL is 0V, if WL configures V _on The SL end is provided with a fixed voltage pulse amplitude value of 0 and a memristor M ₁ Depending on the input Q. Specifically, if the logical operation result of the expression QP:0 is 1, the voltage C takes on the value V _on The method comprises the steps of carrying out a first treatment on the surface of the If the logical operation result of the expression QP 0 is 0, the value of the voltage C is 0V; the value of the voltage D is 0V;

when the type of logical operation is a NAND logical operation (NAND): to select the expression

Result of (2) selecting V _on Or 0V is applied to the WL terminal (when the expression results in 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL configures 0V, SL is 0V, if WL configures V _on The SL end is a fixed voltage pulse amplitude of-2V ₂ Memristor M ₁ Depending on the input Q. Specifically, if the expression +.>

when the type of logical operation is an OR logical Operation (OR): selecting V with the result of selecting the expression Q1:P _on Or 0V is applied to the WL terminal (when the expression results in 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL configures 0V, SL is 0V, if WL configures V _on Selecting voltage pulse amplitude-2V according to input P ₂ Or 0V applied at the SL end (2V is selected when p=1) ₂ Select 0V when p=0), memristor M ₁ Depending on the input Q. Specifically, in the case where the logical operation result of the selection expression Q1:P is 1, the voltage C takes on a value of V _on At this time, if the logic value P takes on 1, the voltage D takes on-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value P is 0, the value of the voltage D is 0V; under the condition that the logical operation result of the selection expression Q1:P is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

When the type of logical operation is a NOR Operation (NOR): to select the expression

Result of (2) selecting V _on Or 0V is applied to the WL terminal (when the expression results in 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL configures 0V, SL is 0V, e.g. WL configuration V _on The SL end is a fixed voltage pulse amplitude of-2V ₂ Memristor M ₁ Depending on the input Q. Specifically, if the expression +.>

If the logic operation result of (a) is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V; />

When the type of logical operation is a materialized logical operation (IMP): to select the expression

Result of (2) selecting V _on Or 0V is applied to the WL terminal (when the expression results in 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL configures 0V, SL is 0V, if WL configures V _on Selecting the voltage pulse amplitude 0 or-2V according to the input P ₂ Applied to the SL end (0V for p=1 and-2V for p=0) ₂ ) Memristor M ₁ Depending on the input Q. Specifically, in the selection expression +.>

when the type of logical operation is negative parenchymal implication logical operation (NIMP): selecting V with the result of selecting the expression Q0:P _on Or 0V is applied toWL end (when expression result is 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL configures 0V, SL is 0V, if WL configures V _on The SL end is a fixed voltage pulse amplitude of-2V ₂ Memristor M ₁ Depending on the input Q. Specifically, if the logical operation result of the expression Q0:P is 1, the voltage C takes on the value V _on At this time, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logical operation result of the expression Q0:P is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is an anti-parenchymal implication logical operation (RIMP): selecting V with the result of selecting expression QP 1 _on Or 0V is applied to the WL terminal (when the expression results in 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL configures 0V, SL is 0V, if WL configures V _on The SL end is a fixed voltage pulse amplitude of-2V ₂ Memristor M ₁ Depending on the input Q. Specifically, if the logical operation result of the expression QP 1 is 1, the voltage C takes on the value V _on At this time, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logical operation result of the expression QP 1 is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is an anti-negative parenchymal implication logical operation (RNIMP): to select the expression

Result of (2) selecting V _on Or 0V is applied to the WL terminal (when the expression results in 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL configures 0V, SL is 0V, if WL configures V _on The SL end is provided with a fixed voltage pulse amplitude value of 0 and a memristor M ₁ Depending on the input Q. Specifically, if the expression +.>

The logical operation result of (1) is that the voltage C takes the value of V _on The method comprises the steps of carrying out a first treatment on the surface of the If an expression is selected

when the type of logical operation is an exclusive-or logical operation (XOR): to select the expression

Result of (2) selecting V _on Or 0 is applied to the WL terminal (when the expression results in 1, V is selected _on The method comprises the steps of carrying out a first treatment on the surface of the When the expression result is 0, 0V is selected); if WL is set to 0V, SL must be 0V, if WL is set to V _on Selecting a voltage pulse amplitude of-2V according to the input P ₂ Or 0V applied at the SL end (2V is selected when p=1) ₂ Select 0V when p=0), memristor M ₁ The resistance state of (2) is determined according to the input Q; specifically, in the selection expression +. >

when the type of logical operation is an exclusive nor (XNOR): to select the expression

Result of (2) selecting V _on Or 0 is applied at the WL terminal; if WL configures 0V, SL is 0V, if WL configures V _on Selecting the voltage pulse amplitude of 0V or-2V according to the input P ₂ Applied at the SL end (selected-2V when p=0 ₂ P=1, 0V is selected), the resistance state of memristor M1 depends on the input Q. Specifically, in the selection expression +.>

The logical operation result of (a) isIn the case of 1, the voltage C takes on the value V _on At this time, if the logic value P is 1, the voltage D is 0V; if the logic value P is 0, the voltage D is-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the In the selection expression +.>

When the logical operation result of (a) is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V; />

Wherein V is _on The voltage of the first transistor or the second transistor in the linear region is used, and at the moment, the source and the drain of the transistor are connected, and the equivalent is a variable resistor; the first transistor and the second transistor are NMOS transistors. Taking a transistor at a 0.18 process node as an example, V _on The value was 3.3V. V (V) ₂ ＝V-V ₁ ，V ₂ Is of the value range of memristor V _set Is proportional to the voltage range, preferably takes on the value of

TABLE 1

s2, judging whether the current operation is the operation related to the logic value Q, if so, using the memristor M ₁ Setting the resistance state corresponding to the logic value Q; wherein the operation related to the logical value Q comprises logically operating the logical value P and the logical value QAn operation of calculation and an operation of performing a logical operation only on the logical value Q;

s3, through bit line BL ₀ Memristor M ₁ Applying voltage-V ₀ Through bit line BL ₁ Memristor M ₂ Applying a voltage V ₁ Applying a voltage C on the word line WL, applying a voltage D on the source control terminal, and reading the memristor M ₂ The resistance state of (2) is the logic operation result;

wherein V is ₀ And V ₁ Simultaneously satisfies: v (V) _set /2≤V ₀ <V _set ，V _set /2≤V ₁ <V _set And V is ₀ +V ₁ ≥V；V _set Is memristor M ₁ Or memristor M ₂ A threshold value for switching from a high resistance state to a low resistance state; v=e _set +3RMS _set Is memristor M ₁ Or memristor M ₂ The upper limit of the fluctuation range of the threshold voltage variation; e (E) _set Is V (V) _set Is the average value of (2); RMS (root mean square) _set Is V (V) _set Mean square error of (a);

The related technical solution is the same as the complete nonvolatile boolean logic operation circuit provided in the first aspect of the present invention, and details are not repeated here.

In summary, the logic circuit composed of the memristor, the transistor, the fixed value resistor and the configurable comparator provided by the invention realizes 16 complete logic calculations by configuring different operation voltages at the control end and synchronously obtains the calculation result of the digital domain. The invention aims to provide a complete nonvolatile Boolean logic circuit based on a memristor (1T 1R array) and a control method thereof, which are capable of improving the calculation parallelism and efficiency, increasing the calculation reliability, reducing the calculation error caused by electric leakage in the memristor array, and ensuring the integrity of input information in the calculation process while using the least possible operation steps and fixed circuit topology. Therefore, the scheme can be used as a general logic implementation method.

The related technical scheme is the same as the control method of the complete nonvolatile Boolean logic circuit, and the description is omitted here.

memristor M of each complete nonvolatile Boolean logic operation circuit ₁ The positive electrodes of (a) are all connected to the same bit line BL ₀ Memristor M ₂ The positive electrodes of (a) are all connected to the same bit line BL ₁ And the logic operation method is used for processing a plurality of logic operations in parallel in the same logic calculation pulse period.

Specifically, fig. 4 is a schematic diagram of a complete non-volatile boolean logic parallel operation circuit based on the complete non-volatile boolean logic operation circuit shown in fig. 1, in which a cross structure of 4 WLs and 2 BLs is shown.

In order to further illustrate the complete non-volatile boolean logic parallel operation circuit provided by the invention, in an alternative embodiment, the Vset of the hafnium oxide memristor compatible with the CMOS process is selected for mean value statistics to obtain V _set Mean E of (2) _set 0.6V, mean square error RMS _set 0.05V, so v=0.75v,

the pulse width of the operation pulse is set to 100ns, the selected transistor is mn33 NMOS in 0.18 μm process library, and the transistor works in the voltage V of the linear region _on The value was 3.3V. Simulation results of the four-bit input bitwise exclusive OR logic calculation and the voltage relationships of the WL and SL terminals according to the input configuration are provided as shown in FIG. 5: p=0011, q=0101, P-Q logicThe calculation result should be 0110, the first row of the optional array represents the lowest bit, the fourth row represents the highest bit, and the simulation calculation is performed to determine whether the voltage drop at two ends of the second memristor in each row is as expected, for example, the calculation result is 1, which means that the voltage drop at two ends of the second memristor needs to be greater than V _set The resistance state is overturned; the calculation result is 0, meaning that the voltage drop across the second memristor needs to be less than V _set WL turn-off can be used in a 1T1R array to isolate the row, the voltage drop across the second memristor is approximately 0, and simulation results are expected.

Further, as shown in FIG. 6, each row is a memristor M for storing output results ₂ The result of the change in resistance state during the logic computation (pulsing); FIG. 7 shows the output memristor M for each row ₂ The result of the change in voltage drop across the logic computation (pulsing) is also described. Fig. 8 shows the digital domain calculation result output in the form of high and low levels.

When p=0 and q=0 are input, M ₁ Setting to a high resistance state, and connecting the BL0 end operation pulse amplitude to-V ₀ BL1 end operation pulse amplitude connects V ₁ WL terminal is connected with 0V, the amplitude of the SL terminal operation pulse is connected with 0V, at this time M ₂ Voltage V at two ends _M2 About 0, M ₂ The high resistance state is kept unchanged, a logic value 0 is output, and the comparator outputs a low level;

when p=0 and q=1 are input, M ₁ Setting to a low resistance state, and connecting the BL0 end operation pulse amplitude to-V ₀ BL1 end operation pulse amplitude connects V ₁ The WL-side access transistor operates at 3.3v in the linear region and the sl-side operation pulse amplitude is 0, at this time M ₂ Voltage V at two ends _M2 Greater than V _set ，M ₂ The low resistance state is changed, a logic value 1 is output, and a comparator outputs a high level;

when p=1 and q=0 are input, M ₁ Setting to a high resistance state, and connecting the BL0 end operation pulse amplitude to-V ₀ BL1 end operation pulse amplitude connects V ₁ WL-side access transistor operates at voltage 3.3V in the linear region and sl-side operation pulse amplitude is-2V ₂ At this time M ₂ Voltage V at two ends _M2 Greater than V _set ，M ₂ Transition to low resistance stateOutputting a logic value of 1, and outputting a high level by the comparator;

when p=1 and q=1 are input, M ₁ Setting to a low resistance state, and connecting the BL0 end operation pulse amplitude to-V ₀ BL1 end operation pulse amplitude connects V ₁ WL terminal is connected with 0V, SL terminal operation pulse amplitude is connected with 0, M ₂ Voltage V at two ends _M2 Less than V _set ，M ₂ The high resistance state is kept unchanged, a logic value of 0 is output, and the comparator outputs a low level.

Similarly, other basic boolean logic functions may be implemented in accordance with the methods described above.

In summary, the invention discloses a complete nonvolatile boolean logic circuit based on a 1T1R array, which consists of two memristors, two enhanced NMOS transistors, a constant value resistor, a transmission gate switch and a comparator, fully utilizes the switching characteristics of the transistors in the 1T1R structure on a logic algorithm, controls the logic iteration step to two steps by dynamically configuring the control pins on the word line and the source line of the circuit, selectively turns on the transmission gate switch during the logic operation to realize sampling the current on the constant value resistor, compares with a fixed reference voltage value to obtain the output result of a digital domain, and realizes 16 kinds of reconfigurable boolean logic functions based on 16 kinds of excitation configuration schemes and limited power supply amplitude types; wherein the positive pole of the memristor and the bit line (BL ₀ 、BL ₁ ) The source terminals of the transistors in the same row are connected together and are connected to an SL pin (source control end) through a fixed resistor, and the node connected with the source line is selectively connected to a comparator. Memristor M ₁ The input resistance state of (2) is determined according to the logic input Q, and the memristor M ₂ As the output of the calculation result. In the logic calculation process, the voltage pulse amplitude loaded on the BL end is fixed, and the upper limit V=E of the change fluctuation range of the threshold voltage of the memristor _set +3RMS _set The method comprises the steps of carrying out a first treatment on the surface of the Wherein E is _set Is V (V) _set Is the average value of (2); RMS (root mean square) _set Is V (V) _set Is a mean square error of (c). Input memristor M ₁ The input voltage on the upper electrode is-V ₀ (V ₀ Is a memristor V _set Is proportional to the voltage range of (2) and is required to satisfy V ₀ +V ₁ Not less than V), output memristor M ₂ The input voltage on the upper electrode is V ₁ (V ₁ Is of the value range of memristor V _set The voltage ranges are proportional to each other and satisfy V ₀ +V ₁ Not less than V), the voltage at WL terminal is equal to two voltages { V) according to the logic type and input Q, P _on Selecting between 0V; the voltage of the SL terminal is 2 voltages {0V, -2V according to the logic type, the voltage value of WL and the input P ₂ Selection between (V) ₂ ＝V-V ₁ The value range is the same as that of the memristor V _set Proportional to the voltage range of (a); when the real-time output result is required to be obtained, the reading step of the traditional scheme is not required to be added, and the digital calculation result is synchronously obtained after the logic calculation is completed by starting the transmission gate switch, so that the construction of the digital-analog hybrid system is facilitated. Compared with the existing logic calculation scheme, the method has the advantages that the number of operation steps is small, the problem of misoperation or unsuccessful operation caused by leakage current in large-scale parallel processing can be completely avoided by adopting the 1T1R array, because BL end excitation is fixed, a plurality of logic operations can be realized simultaneously in one clock period, the calculation parallelism and efficiency are greatly improved, and the advantage of calculating by using nonvolatile devices is increased. The scheme has logic completeness. The logic implementation method adopted by the scheme is non-destructive, and is beneficial to protecting the integrity of input information. The scheme has simple and feasible logic linkage stage and is beneficial to realizing more complex logic function application.

It will be readily appreciated by those skilled in the art that the foregoing description is merely a preferred embodiment of the invention and is not intended to limit the invention, but any modifications, equivalents, improvements or alternatives falling within the spirit and principles of the invention are intended to be included within the scope of the invention.

Claims

1. A complete non-volatile boolean logic operation circuit based on a 1T1R array for performing logic operations on an input logic value P and/or an input logic value Q, comprising: control deviceSystem unit, memristor M ₁ Memristor M ₂ A first transistor, a second transistor, and a resistor;

the memristor M ₁ Positive electrode of (a) and bit line BL ₀ The negative electrode is connected with the drain electrode end of the first transistor; the memristor M ₂ Positive electrode of (a) and bit line BL ₁ The negative electrode is connected with the drain electrode end of the second transistor; the gates of the first transistor and the second transistor are connected to the same word line WL, and the sources of the first transistor and the second transistor are connected to the same source line SL; the sources of the first transistor and the second transistor are led out through the source line SL and then connected with the first end of the resistor, and the second end of the resistor is used as a source control end; the first transistor and the first transistor are the same; the memristor M ₁ And the memristor M ₂ The same, and the initial state is the high resistance state;

the control unit is used for passing through the bit line BL during logic operation ₀ For the memristor M ₁ Applying voltage-V ₀ Through the bit line BL ₁ For the memristor M ₂ Applying a voltage V ₁ Applying a voltage C on the word line WL, applying a voltage D on the source control terminal, and reading the memristor M ₂ The resistance state of (2) is the logic operation result;

wherein, when the logic operation circuit executes the operation related to the logic value Q, the control unit is further used for connecting the memristor M before logic operation ₁ Setting the resistance state corresponding to the logic value Q; the operations related to the logical value Q include an operation of performing a logical operation on the logical value P and the logical value Q and an operation of performing a logical operation on only the logical value Q;

V ₀ and V ₁ Simultaneously satisfies: v (V) _set /2≤V ₀ <V _set ，V _set /2≤V ₁ <V _set And V is ₀ +V ₁ ≥V；V _set For the memristor M ₁ Or the memristor M ₂ A threshold value for switching from a high resistance state to a low resistance state; v is the memristor M ₁ Or the memristor M ₂ The upper limit of the fluctuation range of the threshold voltage variation;

the value of the voltage C is determined by the type of the logical operation and the logical value Q, P, and the value of the voltage D is determined by the type of the logical operation, the logical value P and the voltage C.

2. The perfect nonvolatile boolean logic operation circuit of claim 1, wherein V ₀ Take the value of

V ₁ The value is +.>

3. The perfect nonvolatile Boolean logic operation circuit of claim 1 wherein,

when the type of the logical operation is a true logical operation, the voltage C takes a value of V _on The value of the voltage D is 0V;

when the type of the logic operation is a false logic operation, the value of the voltage C is 0V, and the value of the voltage D is 0V;

when the type of logical operation is P logical operation: if the logic value P is 1, the voltage C takes on the value V _on At this time, the voltage D takes a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value P is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is a non-P logical operation: if the logic value P is 1, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V; if the logic value P is 0, the voltage C takes on the value V _on At this time, theThe value of the voltage D is-2V ₂ ；

When the type of logical operation is a non-Q logical operation: if the logic value Q is 1, the voltage C takes on the value V _on At this time, the voltage D takes a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value Q is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is an AND logical operation: if the logical operation result of the expression QP 0 is 1, the value of the voltage C is V _on The method comprises the steps of carrying out a first treatment on the surface of the If the logical operation result of the selection expression QP:0 is 0, the value of the voltage C is 0V; the value of the voltage D is 0V;

The logical operation result of (1) is that the voltage C takes the value V _on At this time, the voltage D takes a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the selection expression +.>

when the type of logical operation is an or logical operation: in the case that the logical operation result of the selection expression Q1:P is 1, the voltage C takes on a value of V _on At this time, if the logic value P takes on a value of 1, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value P is 0, the value of the voltage D is 0V; under the condition that the logical operation result of the selection expression Q1:P is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of the logical operation is a materialized logical operation: in selecting an expression

In the case that the logical operation result of (2) is 1, the voltage C takes on a value of V _on At this time, if the logic value P is 1, the voltage D is 0V; if the logic value P is 0, the voltage D is-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the In the selection expression +.>

When the logic operation result of (a) is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is a negative parenchymal implication logical operation: if the logical operation result of the selection expression Q0:P is 1, the value of the voltage C is V _on At this time, the voltage D takes a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logical operation result of the selection expression Q0:P is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of the logical operation is an anti-parenchymal implication logical operation: if the logical operation result of the expression QP 1 is 1, the value of the voltage C is V _on At this time, the voltage D takes a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logical operation result of the selection expression QP 1 is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of the logical operation is an anti-negative parenchymal implication logical operation: if an expression is selected

The logical operation result of (1) is that the voltage C takes the value V _on The method comprises the steps of carrying out a first treatment on the surface of the If the selection expression +.>

The logic operation result of (2) is 0, and the value of the voltage C is 0V; the value of the voltage D is 0V;

In the case that the logical operation result of (2) is 1, the voltage C takes on a value of V _on At this time, if the logic value P takes on a value of 1, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value P is 0, the value of the voltage D is 0V; in the selection expression +. >

wherein V is _on A voltage operating in a linear region for the first transistor or the second transistor; the first transistor and the second transistorThe transistors are NMOS transistors; v (V) ₂ ＝V-V ₁ 。

4. The perfect nonvolatile boolean logic operation circuit of claim 1, wherein V ₂ Take the value of

5. The perfect nonvolatile boolean logic operation circuit of claim 1, wherein the resistance is of a value between the memristor M ₁ Or the memristor M ₂ Between the high resistance and the low resistance; the resistance value of the resistor is

Wherein R is _H For the memristor M ₁ Or the memristor M ₂ High resistance state resistance value R _L For the memristor M ₁ Or the memristor M ₂ Low resistance state resistance value of (a).

6. The perfect nonvolatile boolean logic operation circuit of any one of claims 1-5, further comprising: a reading circuit; wherein the reading circuit includes: a transmission gate connected with the first end of the resistor, and a comparator connected with the output end of the transmission gate for reading the memristor M ₂ Is a resistance state of (a).

7. A control method of a complete non-volatile boolean logic circuit for performing a logical operation on an input logical value P and/or an input logical value Q, characterized by a control unit applied in a complete non-volatile boolean logic circuit according to any of the claims 1-6, comprising the steps of:

s1, connecting the memristor M ₁ And the memristor M ₂ All initialize to a high resistance state;

s2, judgingWhether the current operation is the operation related to the logic value Q, if so, the memristor M is selected ₁ Setting the resistance state corresponding to the logic value Q; wherein the operations related to the logical value Q include an operation of performing a logical operation on the logical value P and the logical value Q and an operation of performing a logical operation on only the logical value Q;

S3, passing through the bit line BL ₀ For the memristor M ₁ Applying voltage-V ₀ Through the bit line BL ₁ For the memristor M ₂ Applying a voltage V ₁ Applying the voltage C on the word line WL, applying the voltage D on the source control terminal, and reading the memristor M ₂ The resistance state of (2) is the logic operation result;

wherein V is ₀ And V ₁ Simultaneously satisfies: v (V) _set /2≤V ₀ <V _set ，V _set /2≤V ₁ <V _set And V is ₀ +V ₁ ≥V；V _set For the memristor M ₁ Or the memristor M ₂ A threshold value for switching from a high resistance state to a low resistance state; v=e _set +3RMS _set For the memristor M ₁ Or the memristor M ₂ The upper limit of the fluctuation range of the threshold voltage variation; e (E) _set Is V (V) _set Is the average value of (2); RMS (root mean square) _set Is V (V) _set Mean square error of (a);

8. The method for controlling a complete non-volatile boolean logic circuit according to claim 7, characterized in that,

When the type of the logical operationFor the P logical operation: if the logic value P is 1, the voltage C takes on the value V _on At this time, the voltage D takes a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value P is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

when the type of logical operation is a non-P logical operation: if the logic value P is 1, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V; if the logic value P is 0, the voltage C takes on the value V _on At this time, the voltage D takes a value of-2V ₂ ；

when the logic is operated onThe type of calculation is OR logic operation: in the case that the logical operation result of the selection expression Q1:P is 1, the voltage C takes on a value of V _on At this time, if the logic value P takes on a value of 1, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value P is 0, the value of the voltage D is 0V; under the condition that the logical operation result of the selection expression Q1:P is 0, the value of the voltage C is 0V, and at the moment, the value of the voltage D is 0V;

In the case that the logical operation result of (2) is 1, the voltage C takes on a value of V _on At this time, if the logic value P takes on a value of 1, the voltage D takes on a value of-2V ₂ The method comprises the steps of carrying out a first treatment on the surface of the If the logic value P is 0, the value of the voltage D is 0V; in the selection expression +.>

9. The bitwise logic cascading method based on the complete nonvolatile Boolean logic circuit is characterized by comprising the following steps of:

the previous logic operation result obtained by operating according to the control method of claim 7 or 8 is used as a new input logic value Q, and the control method of claim 7 or 8 is operated again, so that the bitwise logic cascade is realized.

10. A complete non-volatile boolean logic parallel operation circuit, characterized in that it comprises a plurality of complete non-volatile boolean logic operation circuits according to any of claims 1-6;

memristor M of each complete nonvolatile Boolean logic operation circuit ₁ The positive electrodes of (a) are all connected to the same bit line BL ₀ Memristor M ₂ The positive electrodes of (a) are all connected to the same bit line BL ₁ And the logic operation method is used for realizing a plurality of logic operations in parallel in the same logic calculation pulse period.