WO2024113438A1 - Complete non-volatile boolean logic circuit based on 1t1r array, and control method therefor - Google Patents
Complete non-volatile boolean logic circuit based on 1t1r array, and control method therefor Download PDFInfo
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- the present invention belongs to the technical field of microelectronic devices, and more specifically, relates to a complete non-volatile Boolean logic circuit based on a 1T1R array and a control method thereof.
- Modern computers are mainly based on the von Neumann architecture.
- data is obtained from the storage unit, transferred to the computing unit, and then transferred to the storage unit after the calculation is completed.
- the bus transmission connecting the two parts has become a bottleneck for further speed increase. Frequent data transmission occupies most of the time and power consumption in the data processing process.
- computers are facing more computing-intensive tasks, which has aggravated the severity of this bottleneck problem and restricted the development of modern computers. It is called the memory wall.
- In-memory computing is a very promising solution. Similar to the human brain, in-memory computing aims to achieve the coexistence of storage and computing in the same physical structure, which can greatly reduce energy consumption and clock cycles, realize parallel computing, and has huge research and development and application space.
- memristor As a new type of non-volatile memory device, memristor has become a strong candidate for in-memory computing architecture because of its characteristic of being able to maintain its resistance state after power is removed.
- the logic implementation based on memristor can be divided into three categories.
- both input and output are represented in the form of resistance state of memristor.
- This type of scheme is conducive to logical cascading, but the number of devices used is large, and with the increase of computational complexity, the number of devices used and the complexity of operation are increasing;
- the input is added to the two ends of the memristor in the form of voltage, and the output is represented in the form of resistance state.
- the number of devices used in this type of scheme is greatly reduced, and the number of operation steps is also small, but the logic cascade must introduce the process of digital-to-analog conversion, which requires complex peripheral circuits for support;
- the input is the voltage applied to one end of the memristor and the initial resistance value of the memristor, and the output is represented in the form of resistance state of the memristor.
- This type of method uses a small number of devices, a small number of operation steps, and is easy to cascade logic, but this type of logic calculation is destructive and serial, which is not conducive to protecting the integrity of input information and improving the parallelism of calculation. At present, most schemes are demonstrated based on arrays composed of pure memristors.
- the present invention provides a complete non-volatile Boolean logic circuit based on a 1T1R array and a control method thereof, so as to solve the technical problem that the prior art cannot improve the efficiency of non-volatile Boolean logic operations with a small number of operation steps and a fixed circuit topology structure.
- the present invention provides a complete non-volatile Boolean logic operation circuit based on a 1T1R array, which is used to perform a logic operation on an input logic value P and/or an input logic value Q;
- the above logic circuit includes: a control unit, a memristor M 1 , a memristor M 2 , a first transistor, a second transistor and a resistor;
- the positive electrode of the memristor M1 is connected to the bit line BL0 , and the negative electrode is connected to the drain terminal of the first transistor;
- the positive electrode of the memristor M2 is connected to the bit line BL1 , and the negative electrode is connected to the drain terminal of the second transistor;
- the gates of the first transistor and the second transistor are connected to the same word line WL, and the sources are connected to the same source line SL;
- the sources of the first transistor and the second transistor are connected to the first end of the resistor after being led out through the source line SL, and the second end of the resistor serves as the source control end;
- the first transistor and the second transistor are the same;
- the memristor M1 and the memristor M2 are the same, and both are in a high-impedance state in the initial state;
- the control unit is used to apply a voltage -V 0 to the memristor M 1 through the bit line BL 0 , apply a voltage V 1 to the memristor M 2 through the bit line BL 1 , apply a voltage C to the word line WL, apply a voltage D to the source control terminal, and read the resistance state of the memristor M 2 , which is the result of the logic operation;
- the control unit when the logic circuit performs an operation related to the logic value Q, the control unit is further used to set the memristor M1 to a resistance state corresponding to the logic value Q before performing the logic operation;
- the operation related to the logic value Q includes an operation of performing a logic operation on the logic value P and the logic value Q and an operation of performing a logic operation only on the logic value Q;
- V 0 and V 1 simultaneously satisfy: V set /2 ⁇ V 0 ⁇ V set , V set /2 ⁇ V 1 ⁇ V set , and V 0 +V 1 ⁇ V;
- V set is the threshold at which the memristor M 1 or the memristor M 2 changes from a high resistance state to a low resistance state;
- V is the upper limit of the fluctuation range of the threshold voltage of the memristor M 1 or the memristor M 2 ;
- the value of voltage C is determined by the logic operation type and the logic values Q and P, and the value of voltage D is determined by the logic operation type, the logic value P and voltage C.
- V 0 is V 1 is
- the memristor M1 and the memristor M2 both include a high resistance state and a low resistance state; the high resistance state corresponds to a logic value "0", and the low resistance state corresponds to a logic value "1".
- the voltage C takes a value of V on
- the voltage D takes a value of 0V
- the voltage C takes a value of 0V and the voltage D takes a value of 0V;
- the type of logic operation is non-P logic operation: if the logic value P is 1, the voltage C takes a value of 0V, at which time, the voltage D takes a value of 0V; if the logic value P is 0, the voltage C takes a value of V on , at which time, the voltage D takes a value of -2V 2 ;
- the type of logic operation is an OR logic operation: when the logic operation result of the selection expression Q? 1:P is 1, the voltage C takes the value of V on . At this time, if the logic value P takes the value of 1, the voltage D takes the value of -2V 2 ; if the logic value P takes the value of 0, the voltage D takes the value of 0V; when the logic operation result of the selection expression Q? 1:P is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V;
- the type of logical operation is the inverse substantive implication logical operation: if the logical operation result of the expression Q? P:1 is 1, the voltage C takes the value of V on , at which time, the voltage D takes the value of -2V 2 ; if the logical operation result of the expression Q? P:1 is 0, the voltage C takes the value of 0V, at which time, the voltage D takes the value of 0V;
- V2 is
- the resistance value of the resistor is between the high resistance value and the low resistance value of the memristor M1 or the memristor M2 ; the resistance value of the resistor is Wherein RH is the high-resistance resistance value of the memristor M1 or the memristor M2 , and RL is the low-resistance resistance value of the memristor M1 or the memristor M2 .
- the above-mentioned complete non-volatile Boolean logic circuit also includes: a reading circuit; wherein the reading circuit includes: a transmission gate circuit connected to the first end of the resistor, and a comparator connected to the output end of the transmission gate circuit, for reading the resistance state of the memristor M2 .
- the present invention provides a control method for a complete non-volatile Boolean logic circuit, which is applied to a control unit in the complete non-volatile Boolean logic circuit provided in the first aspect of the present invention, and comprises the following steps:
- V 0 and V 1 simultaneously satisfy: V set /2 ⁇ V 0 ⁇ V set , V set /2 ⁇ V 1 ⁇ V set , and V 0 +V 1 ⁇ V;
- V set is the threshold at which the memristor M 1 or the memristor M 2 changes from a high resistance state to a low resistance state;
- V is the upper limit of the fluctuation range of the threshold voltage of the memristor M 1 or the memristor M 2 ;
- the value of voltage C is determined by the logic operation type and the logic values Q and P, and the value of voltage D is determined by the logic operation type, the logic value P and voltage C.
- the voltage C takes a value of V on
- the voltage D takes a value of 0V
- the voltage C takes a value of 0V and the voltage D takes a value of 0V;
- the type of logic operation is non-P logic operation: if the logic value P is 1, the voltage C takes a value of 0V, at which time, the voltage D takes a value of 0V; if the logic value P is 0, the voltage C takes a value of V on , at which time, the voltage D takes a value of -2V 2 ;
- the type of logic operation is an OR logic operation: when the logic operation result of the selection expression Q? 1:P is 1, the voltage C takes the value of V on . At this time, if the logic value P takes the value of 1, the voltage D takes the value of -2V 2 ; if the logic value P takes the value of 0, the voltage D takes the value of 0V; when the logic operation result of the selection expression Q? 1:P is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V;
- the type of logical operation is the inverse substantive implication logical operation: if the logical operation result of the expression Q? P:1 is 1, the voltage C takes the value of V on , at which time, the voltage D takes the value of -2V 2 ; if the logical operation result of the expression Q? P:1 is 0, the voltage C takes the value of 0V, at which time, the voltage D takes the value of 0V;
- the present invention provides a bit-by-bit logic cascading method based on the above-mentioned complete non-volatile Boolean logic circuit, comprising:
- the previous logic operation result obtained by operating according to the control method described in the second aspect is used as a new input logic value Q, and the control method described in the second aspect is re-operated to achieve bit-by-bit logic cascading.
- the present invention provides a complete non-volatile Boolean logic parallel operation circuit, comprising a plurality of complete non-volatile Boolean logic operation circuits provided in the first aspect of the present invention;
- the positive electrodes of the memristors M1 of each complete nonvolatile Boolean logic operation circuit are connected to the same bit line BL0 , and the positive electrodes of the memristors M2 are connected to the same bit line BL1 , so as to realize multiple logic operations in parallel within the same logic calculation pulse cycle.
- the present invention provides a complete non-volatile Boolean logic operation circuit based on a 1T1R array, which is used for performing a logic operation on an input logic value P and/or a logic value Q;
- the logic circuit is mainly composed of a memristor, a transistor and a resistor, the input resistance state of the memristor M1 is determined according to the logic input Q, the input voltage is fixed at -V0 , the input voltage of M2 is fixed at V1 , the input voltage C on the word line WL is determined by the logic operation type and the logic values Q and P;
- the input voltage D on the source control terminal is determined by the logic operation type, the logic value P and the voltage C, and the resistance state of the memristor M2 is used as the output of the calculation result;
- the present invention fully utilizes the switching characteristics of the transistors in the 1T1R structure in the logic algorithm, and by dynamically configuring the input voltages on the word line WL and the source control terminal of the circuit, the
- the complete non-volatile Boolean logic operation circuit provided by the present invention does not need to add the reading step of the traditional solution when real-time output results are required.
- the transmission gate switch By turning on the transmission gate switch, the current on the sampled fixed resistor can be compared with the fixed reference voltage value to synchronously obtain the calculation result in the digital domain, which is conducive to the construction of a digital-analog hybrid system.
- the resistance state of the memristor M1 does not change during the operation of the logic calculation, and the entire operation process is non-destructive, which is conducive to protecting the integrity of the input information.
- the present invention provides a bit-by-bit logic cascade method based on the above-mentioned complete non-volatile Boolean logic circuit, which can directly use the result obtained from the previous step of logic calculation as the input of the next step of logic operation.
- the logic cascade is simple and easy, which helps to realize more complex logic functions.
- the present invention provides a complete non-volatile Boolean logic parallel operation circuit, comprising a plurality of the above-mentioned complete non-volatile Boolean logic operation circuits, wherein the positive electrodes of the memristors M1 of the complete non-volatile Boolean logic operation circuits are all connected to the same bit line BL0 , and the positive electrodes of the memristors M2 are all connected to the same bit line BL1 , the bit line BL0 has a fixed input voltage of -V0 , and the bit line BL1 has a fixed input voltage of V1 , and it is only necessary to control the voltage C and the voltage D input to each row word line WL and the source control terminal respectively, so that multiple logic operations can be realized in parallel within the same logic calculation pulse cycle.
- the present invention requires fewer operation steps, and the use of a 1T1R array can completely avoid the problem of misoperation or unsuccessful operation caused by leakage current during large-scale parallel processing. Because the BL terminal excitation is fixed, multiple logic operations can be realized simultaneously within one clock cycle, which greatly improves the calculation parallelism and efficiency, and increases the advantage of using non-volatile devices for calculation.
- FIG1 is a schematic diagram of the structure of a complete non-volatile Boolean logic operation circuit based on a 1T1R array provided by the present invention
- FIG2 is a schematic diagram of a 1T1R structure based on a memristor used in a complete non-volatile Boolean logic operation circuit provided by the present invention and a 100-cycle test diagram of its I-V characteristics; wherein (a) is a schematic diagram of the 1T1R structure; (b) is a 100-cycle test diagram of the I-V characteristics of the 1T1R structure;
- FIG3 is a schematic diagram of the structure of a complete non-volatile Boolean logic operation circuit with a read circuit provided by the present invention
- FIG4 is a schematic diagram of a complete non-volatile Boolean logic parallel operation circuit provided by the present invention.
- FIG5 is a simulation result of a bitwise XOR logic calculation of a four-bit input provided by the present invention and a voltage relationship between WL and SL terminals configured according to the input;
- FIG6 is a schematic diagram showing the change of the resistance state of each row of memristors M2 used for storing output results during the logic calculation process provided by the present invention
- FIG7 is a schematic diagram showing the change of the voltage drop across the two ends of each row of output memristors M2 provided by the present invention during the logic calculation process;
- FIG8 is a schematic diagram of a digital domain calculation result output in the form of high and low levels provided by the present invention.
- the present invention provides a complete non-volatile Boolean logic operation circuit based on a 1T1R array, which is used to perform a logic operation on an input logic value P and/or an input logic value Q;
- the above logic circuit includes: a control unit, a memristor M 1 , a memristor M 2 , a first transistor, a second transistor and a resistor;
- the positive electrode of the memristor M1 is connected to the bit line BL0 , and the negative electrode is connected to the drain terminal of the first transistor;
- the positive electrode of the memristor M2 is connected to the bit line BL1 , and the negative electrode is connected to the drain terminal of the second transistor;
- the gates of the first transistor and the second transistor are connected to the same word line WL, and the sources are connected to the same source line SL;
- the sources of the first transistor and the second transistor are connected to the first end of the resistor after being led out through the source line SL, and the second end of the resistor serves as the source control end;
- the first transistor and the second transistor are the same;
- the memristor M1 and the memristor M2 are the same, and both are in a high-impedance state in the initial state;
- the control unit is used to apply a voltage -V 0 to the memristor M 1 through the bit line BL 0 , apply a voltage V 1 to the memristor M 2 through the bit line BL 1 , apply a voltage C to the word line WL, apply a voltage D to the source control terminal, and read the resistance state of the memristor M 2 , which is the result of the logic operation;
- the control unit when the logic circuit performs an operation related to the logic value Q, the control unit is further used to set the memristor M1 to a resistance state corresponding to the logic value Q before performing the logic operation;
- the operation related to the logic value Q includes an operation of performing a logic operation on the logic value P and the logic value Q and an operation of performing a logic operation only on the logic value Q;
- V0 and V1 should simultaneously satisfy: Vset / 2 ⁇ V0 ⁇ Vset , Vset / 2 ⁇ V1 ⁇ Vset , and V0 + V1 ⁇ V ;
- Vset is the threshold at which the memristor M1 or the memristor M2 changes from a high-resistance state to a low-resistance state;
- V is the upper limit of the fluctuation range of the threshold voltage change of the memristor M1 or the memristor M2 ;
- RMSset is the mean square error of Vset .
- the voltage amplitude of V1 is between Vset and Vset /2, which can make V1 insufficient to change the memristor originally in a high-resistance state to a low-resistance state; at the same time, when a voltage drop greater than or equal to the voltage V is added across the memristor, it can ensure that the resistance state of the memristor changes; because there is almost no voltage drop loss at the BL end and more voltage loss at the SL end, according to the simulation test results, the value of V0 is preferably The value of V1 is preferably
- the value of voltage C is determined by the logic operation type and the logic values Q and P, and the value of voltage D is determined by the logic operation type, the logic value P and voltage C.
- Figure 2 it is a schematic diagram of the 1T1R structure based on the memristor used in the above-mentioned complete non-volatile Boolean logic operation circuit and its I-V characteristic 100 cycle test diagram; among them, Figure (a) is a schematic diagram of the 1T1R structure; Figure (b) is a 100 cycle test diagram of the I-V characteristics of the 1T1R structure.
- the resistance of the memristor is set to a low resistance state
- a voltage of 3.3V is applied to the gate of the transistor
- a negative voltage V reset is applied to the positive electrode of the memristor
- the source and the substrate are connected to GND
- the resistance of the memristor is set to a high resistance state
- the memristor can be switched between a high resistance state and a low resistance state.
- the high resistance state of the memristor corresponds to a logic value "0”
- the low resistance state of the memristor corresponds to a logic value "1".
- the switching ratio of the memristor device is in the range of [10, 500].
- the large switching ratio can make the resistance of the low resistance state, high resistance state and fixed resistance R of the memristor clearly distinguishable, which is conducive to completing logical calculations based on the voltage division relationship.
- the resistance value of the resistor is between the high resistance value and the low resistance value of the memristor M1 or the memristor M2 ; in some optional implementations, the fixed value resistor is In this circuit, it mainly plays the role of voltage division to distinguish the high and low resistance values of the memristor. Considering that the high and low resistance states of the memristor have a certain fluctuation range, the fixed value resistor R can be selected to be slightly larger than The result provides better guarantee for the reliability of the circuit.
- the above-mentioned complete non-volatile Boolean logic circuit further includes: a reading circuit; wherein the reading circuit includes: a transmission gate circuit connected to the first end of the resistor, and a comparator connected to the output end of the transmission gate circuit, for reading the resistance state of the memristor M 2.
- the present invention provides a logic calculation reading circuit, which can obtain the output result of the digital domain in real time by sampling the node voltage and current of the fixed value resistor end in the logic calculation pulse, and adding the comparator to the circuit.
- the on and off states of the transistor are controlled by the voltage C on the control end WL
- a voltage D is applied to one end of the fixed value resistor through the SL end
- the corresponding logic calculation operation is completed together, and the calculation result is stored in the output memristor M 2 in the form of a resistance state
- the transmission gate enable end is controlled to select whether to obtain a digital output result
- the comparator reference voltage is a fixed voltage value in all types of logic calculations, and each pin is floating in the idle state.
- the input voltage of the comparator is the source line voltage, which is connected to the lower electrode of the memristor through the transistor.
- the row transistor that applies the voltage V on through the word line WL works in the linear region, and the voltage drop on it is very small and can be ignored.
- the reference voltage can be fixed to -V 2 /2.
- the reference voltage can also be fixed to V 2 /2, because the memristor M 2 that becomes low resistance will pull up the potential of the sampling node, while the memristor M 2 that maintains high resistance does not have this effect. Therefore, setting it to V 2 /2 can also distinguish the two state changes of the memristor.
- the present invention provides a complete non-volatile Boolean logic implementation method based on memristor, which can complete 16 kinds of logic calculations in only two steps, and can meet the requirements of easy implementation of logic cascade and protection of the integrity of input information during the calculation process. Specifically, as shown in Table 1:
- V on or 0V is selected to be applied to the WL terminal according to the result of the expression P (when the expression result is 1, V on is selected; when the expression result is 0, 0V is selected); if WL is configured with 0V, SL is 0V; if WL is configured with V on , the SL terminal is a fixed voltage pulse amplitude of -2V 2 .
- the logic value P is 1, the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the logic value P is 0, the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
- Q logic operation select V on or 0V to be applied to the WL terminal according to the result of the expression Q (when the expression result is 1, select V on ; when the expression result is 0, select 0V); if WL is configured with 0V, SL is 0V; if WL is configured with V on , the SL terminal is a fixed voltage pulse with an amplitude of 0, and the resistance state of the memristor M1 is determined according to the input Q. Specifically, if the logic value Q is 1, the voltage C takes the value of V on ; if the logic value Q is 0, the voltage C takes the value of 0V; the voltage D takes the value of 0V;
- the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the logic value Q is 0, the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
- the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the expression is selected The logical operation result is 0, then the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
- select the expression selects V on or 0V to be applied to the WL terminal (when the expression result is 1, select V on ; when the expression result is 0, select 0V); if WL is configured with 0V, SL is 0V. If WL is configured with V on , the SL terminal is a fixed voltage pulse with an amplitude of -2V 2 , and the resistance state of the memristor M 1 depends on the input Q.
- the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the expression is selected The logical operation result is 0, then the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
- IMP intrinsic implication logical operation
- the voltage D takes the value 0V; if the logical value P takes the value 0, the voltage D takes the value -2V 2 ; when selecting the expression When the result of the logical operation is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V.
- NIMP negative essential implication logic operation
- RIMP inverse substantial implication logic operation
- the type of logical operation is the reverse negative implication logical operation (RNIMP): select the expression The result of the expression selects V on or 0V to be applied to the WL terminal (when the expression result is 1, select V on ; when the expression result is 0, select 0V); if WL is configured with 0V, SL is 0V, if WL is configured with V on , the SL terminal is a fixed voltage pulse with an amplitude of 0, and the resistance state of the memristor M1 depends on the input Q. Specifically, if the expression is selected The logical operation result is 1, then the voltage C takes the value V on ; if the expression is selected The logical operation result is 0, then the voltage C takes the value of 0V; the voltage D takes the value of 0V;
- the voltage D takes the value -2V 2 ; if the logical value P takes the value 0, the voltage D takes the value 0V.
- the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V.
- the voltage D takes the value 0V; if the logical value P takes the value 0, the voltage D takes the value -2V 2 ; when selecting the expression When the result of the logical operation is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V.
- V on is the voltage of the first transistor or the second transistor when it is operating in the linear region.
- the source and drain of the transistor are connected, which is equivalent to a variable resistor.
- the first transistor and the second transistor are both NMOS transistors. Taking the transistor at the 0.18 process node as an example, the value of V on is 3.3V.
- V 2 VV 1
- the value range of V 2 is proportional to the voltage range of the memristor V set , and the preferred value is
- the present invention provides a control method for a complete non-volatile Boolean logic circuit, which is applied to a control unit in the complete non-volatile Boolean logic circuit provided in the first aspect of the present invention, and comprises the following steps:
- V 0 and V 1 simultaneously satisfy: V set /2 ⁇ V 0 ⁇ V set , V set /2 ⁇ V 1 ⁇ V set , and V 0 +V 1 ⁇ V;
- V set is the threshold at which the memristor M 1 or the memristor M 2 changes from a high resistance state to a low resistance state;
- E set is the mean value of V set ;
- RMS set is the mean square error of V set ;
- the value of voltage C is determined by the logic operation type and the logic values Q and P, and the value of voltage D is determined by the logic operation type, the logic value P and voltage C.
- the logic circuit composed of a memristor, a transistor, a fixed resistor and a configurable comparator realizes 16 complete logic calculations in two steps by configuring different operating voltages at the control end, and obtains the calculation results of the digital domain synchronously.
- the object of the present invention is to provide a complete non-volatile Boolean logic circuit based on a memristor (1T1R array) and a control method thereof, which improves the parallelism and efficiency of calculations, increases the reliability of calculations, reduces the calculation errors caused by leakage in the memristor array, and the calculation scheme is easy to realize logical cascading and protects the integrity of input information during the calculation process. Therefore, this scheme can be used as a general logic implementation method.
- the present invention provides a bit-by-bit logic cascading method based on the above-mentioned complete non-volatile Boolean logic circuit, comprising:
- the previous logic operation result obtained by operating according to the control method described in the second aspect is used as a new input logic value Q, and the control method described in the second aspect is re-operated to achieve bit-by-bit logic cascading.
- the present invention provides a complete non-volatile Boolean logic parallel operation circuit, comprising a plurality of complete non-volatile Boolean logic operation circuits provided in the first aspect of the present invention;
- the positive electrodes of the memristors M1 of each complete nonvolatile Boolean logic operation circuit are connected to the same bit line BL0 , and the positive electrodes of the memristors M2 are connected to the same bit line BL1 , for processing multiple logic operations in parallel within the same logic calculation pulse cycle.
- FIG4 is a schematic diagram of a complete non-volatile Boolean logic parallel operation circuit based on the complete non-volatile Boolean logic operation circuit shown in FIG1 , and the figure shows a cross structure of 4 WLs and 2 BLs.
- the pulse width of the operation pulse is set to 100ns, and the selected transistor is the mn33NMOS in the 0.18 ⁇ m process library.
- the voltage V on of the linear region is 3.3V.
- the simulation calculates whether the voltage drop across the second memristor in each row is as expected. For example, if the calculation result is 1, it means that the voltage drop across the second memristor needs to be greater than V set , and the resistance state is flipped; if the calculation result is 0, it means that the voltage drop across the second memristor needs to be less than V set . In the 1T1R array, WL can be turned off to isolate this row, and the voltage drop across the second memristor is approximately 0. The simulation results are in line with expectations.
- FIG6 shows the change result of the resistance state of each row of memristors M2 used to store output results during the logic calculation (pulse application);
- FIG7 shows the change result of the voltage drop across each row of output memristors M2 during the logic calculation (pulse application).
- FIG8 shows the digital domain calculation results output in the form of high and low levels.
- the present invention discloses a complete non-volatile Boolean logic circuit based on a 1T1R array.
- the logic circuit is composed of two memristors, two enhanced NMOS transistors, a fixed resistor, a transmission gate switch and a comparator.
- the switching characteristics of the transistors in the 1T1R structure are fully utilized in the logic algorithm.
- the control pins on the word line and the source line of the circuit are dynamically configured to control the logic iteration step to two steps.
- 16 reconfigurable Boolean logic functions can be realized; wherein, the positive electrode of the memristor is connected to the bit line (BL 0 , BL 1 ), the negative electrode of the memristor is connected to the drain end of the transistor, the connection of the transistor adopts the common gate and common source line mode, the source ends of the transistors in the same row are connected together and connected to the SL pin (source control end) through the fixed resistor, and the node where the fixed resistor is connected to the source line can be selectively connected to the comparator.
- the input resistance state of memristor M1 is determined by the logic input Q, and the resistance state of memristor M2 is used as the output of the calculation result.
- V E set +3RMS set ;
- E set is the mean value of V set ;
- RMS set is the mean square error of V set .
- the digital calculation results are obtained synchronously after the logic calculation is completed, which is conducive to the construction of a digital-analog hybrid system.
- this scheme adopts fewer operation steps.
- the use of 1T1R array can completely avoid the problem of misoperation or unsuccessful operation caused by leakage current during large-scale parallel processing.
- the BL end excitation is fixed, multiple logic operations can be realized simultaneously in one clock cycle, which greatly improves the parallelism and efficiency of calculation and increases the advantage of using non-volatile devices for calculation.
- This scheme has logical completeness.
- the logic implementation method adopted by this scheme is non-destructive, which is conducive to protecting the integrity of input information.
- the logic cascading of this scheme is simple and easy, which helps to realize more complex logic function applications.
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Abstract
The present invention belongs to the technical field of microelectronic devices. Disclosed are a complete non-volatile Boolean logic circuit based on a 1T1R array, and a control method therefor, which are used for performing a logic operation on an input logic value P and/or logic value Q. An input resistance state of a memristor M1 is determined by means of a logic input Q, and an input voltage thereof is fixed at -V0. An input voltage of a memristor M2 is fixed at V1. An input voltage C on a wordline WL is determined by means of the type of the logic operation and the logic values Q and P. An input voltage D on a source control end is determined by means of the type of the logic operation, the logic value P and the voltage C. A resistance state of the memristor M2 is used as an output of a computation result. In the present invention, the switch characteristic of a transistor in a 1T1R structure is fully utilized in terms of a logic algorithm, and the steps of realizing a complete Boolean logic function can be controlled to have two steps by dynamically configuring input voltages on a wordline WL and a source control end, such that the non-volatile Boolean logic operation efficiency can be improved with fewer operation steps and a fixed circuit topological structure.
Description
本发明属于微电子器件技术领域，更具体地，涉及一种基于1T1R阵列的完备非易失布尔逻辑电路及其控制方法。The present invention belongs to the technical field of microelectronic devices, and more specifically, relates to a complete non-volatile Boolean logic circuit based on a 1T1R array and a control method thereof.
现代计算机主要基于冯·诺依曼体系结构。在这种体系结构中，数据从存储单元中获数据，传输到计算单元，计算完成后再将数据传输到要存储单元。如今，处理器和存储器的运行速度均已达到了相当高的水平，连接这两部分的总线传输成为了速度进一步提高的瓶颈，频繁的数据传输占据了数据处理过程中大部分的时间和功耗。大数据时代的到来，计算机面临着更多计算密集型的任务，加剧了这一瓶颈问题的严重性，限制了现代计算机的发展，将其称为存储墙。存内计算是一种非常有潜力的解决方法。与人脑相类似，存内计算旨在实现存储与计算在同个物理结构中共存，可以大幅度减少能耗和时钟周期，实现并行运算，研发和应用空间巨大。Modern computers are mainly based on the von Neumann architecture. In this architecture, data is obtained from the storage unit, transferred to the computing unit, and then transferred to the storage unit after the calculation is completed. Nowadays, the operating speed of the processor and memory has reached a very high level. The bus transmission connecting the two parts has become a bottleneck for further speed increase. Frequent data transmission occupies most of the time and power consumption in the data processing process. With the advent of the big data era, computers are facing more computing-intensive tasks, which has aggravated the severity of this bottleneck problem and restricted the development of modern computers. It is called the memory wall. In-memory computing is a very promising solution. Similar to the human brain, in-memory computing aims to achieve the coexistence of storage and computing in the same physical structure, which can greatly reduce energy consumption and clock cycles, realize parallel computing, and has huge research and development and application space.
忆阻器作为一种新型的非易失存储器件，因其在撤电后仍能保持电阻状态这一特性，成为存内计算架构的有力候选器件。基于忆阻器的逻辑实现主要分为三类，第一类实现方法中输入和输出均以忆阻器的阻态的形式表示，这类方案有利于进行逻辑联级但使用的器件数较多，并且随着计算复杂度的增加所使用的器件数与操作复杂度都在增加；第二类实现方法中输入以电压形式加在忆阻器两端，输出以阻态形式表示，这类方案所使用的器件数大大减少，操作步数也较少，但逻辑联级必须引入数模转换的过程，需要复杂的外围电路作支撑；第三类实现方法中，输入分别为忆阻器一端所加电压和忆阻器的初始阻值，输出以忆阻器阻态形式表示，这类方法所用器件数少，操作步数较少，逻辑联级容易，但这类逻辑计算为破坏式且为串行式计算，不利于保护输入信息的完整性、提高计算的并行性。目前大多数方案是基于单纯忆阻器组成的阵列演示的，这种结构虽然具备面积小、集成度高的优势，但极易产生漏电问题，导致计算错误或者计算不成功，不利于实现大规模数据的并 行处理，同时，绝大多数方案需要额外加一个读步骤，将电阻状态的计算结果转化为与传统数字电路保持一致的数字信号，以实现异构计算系统的构建。因此，有必要提出一种电路拓扑结构固定的、逻辑完备的实现方案，在使用尽可能少的操作步数的同时，易实现逻辑联级且不破坏输入数据的完整性，增加数据计算的并行性，减少漏电出现的概率增加计算准确率，输出不仅以非易失的电阻状态保存下来，还能在尽量节省资源的前提下得到数字域的计算结果。As a new type of non-volatile memory device, memristor has become a strong candidate for in-memory computing architecture because of its characteristic of being able to maintain its resistance state after power is removed. The logic implementation based on memristor can be divided into three categories. In the first type of implementation method, both input and output are represented in the form of resistance state of memristor. This type of scheme is conducive to logical cascading, but the number of devices used is large, and with the increase of computational complexity, the number of devices used and the complexity of operation are increasing; in the second type of implementation method, the input is added to the two ends of the memristor in the form of voltage, and the output is represented in the form of resistance state. The number of devices used in this type of scheme is greatly reduced, and the number of operation steps is also small, but the logic cascade must introduce the process of digital-to-analog conversion, which requires complex peripheral circuits for support; in the third type of implementation method, the input is the voltage applied to one end of the memristor and the initial resistance value of the memristor, and the output is represented in the form of resistance state of the memristor. This type of method uses a small number of devices, a small number of operation steps, and is easy to cascade logic, but this type of logic calculation is destructive and serial, which is not conducive to protecting the integrity of input information and improving the parallelism of calculation. At present, most schemes are demonstrated based on arrays composed of pure memristors. Although this structure has the advantages of small area and high integration, it is very easy to cause leakage problems, resulting in calculation errors or unsuccessful calculations, which is not conducive to the parallel processing of large-scale data. At the same time, most schemes require an additional read step to convert the calculation results of the resistance state into digital signals consistent with traditional digital circuits to realize the construction of heterogeneous computing systems. Therefore, it is necessary to propose an implementation scheme with a fixed circuit topology and complete logic. While using as few operation steps as possible, it is easy to realize logical cascading without destroying the integrity of the input data, increase the parallelism of data calculation, reduce the probability of leakage, and increase the calculation accuracy. The output is not only saved in a non-volatile resistance state, but also the calculation results in the digital domain can be obtained while saving resources as much as possible.
【发明内容】[Summary of the invention]
针对现有技术的以上缺陷或改进需求，本发明提供了一种基于1T1R阵列的完备非易失布尔逻辑电路及其控制方法，用以解决现有技术无法以少的操作步数和固定电路拓扑结构提高非易失布尔逻辑运算效率的技术问题。In view of the above defects or improvement needs of the prior art, the present invention provides a complete non-volatile Boolean logic circuit based on a 1T1R array and a control method thereof, so as to solve the technical problem that the prior art cannot improve the efficiency of non-volatile Boolean logic operations with a small number of operation steps and a fixed circuit topology structure.
为了实现上述目的，本发明提供了一种基于1T1R阵列的完备非易失布尔逻辑运算电路，用于对输入的逻辑值P和/或输入的逻辑值Q进行逻辑运算；In order to achieve the above object, the present invention provides a complete non-volatile Boolean logic operation circuit based on a 1T1R array, which is used to perform a logic operation on an input logic value P and/or an input logic value Q;
上述逻辑电路包括：控制单元、忆阻器M
1、忆阻器M
2、第一晶体管、第二晶体管和电阻；
The above logic circuit includes: a control unit, a memristor M 1 , a memristor M 2 , a first transistor, a second transistor and a resistor;
忆阻器M
1的正极与位线BL
0相连，负极与第一晶体管的漏极端相连；忆阻器M
2的正极与位线BL
1相连，负极与第二晶体管的漏极端相连；第一晶体管和第二晶体管的栅极连接在同一条字线WL上，源极连接在同一条源线SL上；第一晶体管和第二晶体管的源极通过源线SL引出后与电阻的第一端相连，电阻的第二端作为源控制端；第一晶体管和第二晶体管相同；忆阻器M
1和忆阻器M
2相同，且初始状态均为高阻态；
The positive electrode of the memristor M1 is connected to the bit line BL0 , and the negative electrode is connected to the drain terminal of the first transistor; the positive electrode of the memristor M2 is connected to the bit line BL1 , and the negative electrode is connected to the drain terminal of the second transistor; the gates of the first transistor and the second transistor are connected to the same word line WL, and the sources are connected to the same source line SL; the sources of the first transistor and the second transistor are connected to the first end of the resistor after being led out through the source line SL, and the second end of the resistor serves as the source control end; the first transistor and the second transistor are the same; the memristor M1 and the memristor M2 are the same, and both are in a high-impedance state in the initial state;
控制单元用于在进行逻辑运算时，通过位线BL
0对忆阻器M
1施加电压-V
0，通过位线BL
1对忆阻器M
2施加电压V
1，在字线WL上施加电压C，在源控制端上施加电压D，并读取忆阻器M
2的阻态，即为逻辑运算结果；
The control unit is used to apply a voltage -V 0 to the memristor M 1 through the bit line BL 0 , apply a voltage V 1 to the memristor M 2 through the bit line BL 1 , apply a voltage C to the word line WL, apply a voltage D to the source control terminal, and read the resistance state of the memristor M 2 , which is the result of the logic operation;
其中，当逻辑电路执行与逻辑值Q有关的操作时，控制单元还用于在进行逻辑运算之前，将忆阻器M
1置为逻辑值Q所对应的阻态；与逻辑值Q有关的操作包括对逻辑值P和逻辑值Q进行逻辑运算的操作和仅对逻辑值Q进行逻辑运算的操作；
Wherein, when the logic circuit performs an operation related to the logic value Q, the control unit is further used to set the memristor M1 to a resistance state corresponding to the logic value Q before performing the logic operation; the operation related to the logic value Q includes an operation of performing a logic operation on the logic value P and the logic value Q and an operation of performing a logic operation only on the logic value Q;
V
0和V
1同时满足：V
set/2≤V
0<V
set，V
set/2≤V
1<V
set，且V
0+V
1≥V；V
set为忆阻器M
1或忆阻器M
2由高阻态转变为低阻态的阈值；V为忆阻器M
1或忆阻器M
2阈值电压变化波动范围的上限；
V 0 and V 1 simultaneously satisfy: V set /2≤V 0 <V set , V set /2≤V 1 <V set , and V 0 +V 1 ≥V; V set is the threshold at which the memristor M 1 or the memristor M 2 changes from a high resistance state to a low resistance state; V is the upper limit of the fluctuation range of the threshold voltage of the memristor M 1 or the memristor M 2 ;
电压C的取值由逻辑运算类型和逻辑值Q、P决定，电压D的取值由逻辑运算类型、逻辑值P以及电压C决定。The value of voltage C is determined by the logic operation type and the logic values Q and P, and the value of voltage D is determined by the logic operation type, the logic value P and voltage C.
进一步优选地，V
0取值为
V
1取值为
Further preferably, V 0 is V 1 is
进一步优选地，上述忆阻器M
1和忆阻器M
2均包括高阻态和低阻态；高阻态对应逻辑值“0”，低阻态对应逻辑值“1”。
Further preferably, the memristor M1 and the memristor M2 both include a high resistance state and a low resistance state; the high resistance state corresponds to a logic value "0", and the low resistance state corresponds to a logic value "1".
进一步优选地，当逻辑运算的类型为真逻辑运算时，电压C取值为V
on，电压D取值为0V；
Further preferably, when the type of logic operation is a true logic operation, the voltage C takes a value of V on , and the voltage D takes a value of 0V;
当逻辑运算的类型为假逻辑运算时，电压C取值为0V，电压D取值为0V；When the type of logic operation is false logic operation, the voltage C takes a value of 0V and the voltage D takes a value of 0V;
当逻辑运算的类型为P逻辑运算时：若逻辑值P为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若逻辑值P为0，则电压C取值为0V，此时，电压D取值为0V；
When the type of logic operation is P logic operation: if the logic value P is 1, the voltage C takes the value V on , at this time, the voltage D takes the value -2V 2 ; if the logic value P is 0, the voltage C takes the value 0V, at this time, the voltage D takes the value 0V;
当逻辑运算的类型为Q逻辑运算时：若逻辑值Q为1，则电压C取值为V
on；若逻辑值Q为0，则电压C取值为0V；电压D取值为0V；
When the type of logic operation is Q logic operation: if the logic value Q is 1, the voltage C takes the value V on ; if the logic value Q is 0, the voltage C takes the value 0V; the voltage D takes the value 0V;
当逻辑运算的类型为非P逻辑运算时：若逻辑值P为1，则电压C取值为0V，此时，电压D取值为0V；若逻辑值P为0，则电压C取值为V
on，此时，电压D取值为-2V
2；
When the type of logic operation is non-P logic operation: if the logic value P is 1, the voltage C takes a value of 0V, at which time, the voltage D takes a value of 0V; if the logic value P is 0, the voltage C takes a value of V on , at which time, the voltage D takes a value of -2V 2 ;
当逻辑运算的类型为非Q逻辑运算时：若逻辑值Q为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若逻辑值Q为0，则电压C取值为0V，此时，电压D取值为0V；
When the type of logic operation is non-Q logic operation: if the logic value Q is 1, the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the logic value Q is 0, the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为与逻辑运算时：若选择表达式Q？P:0的逻辑运算结果为1，则电压C取值为V
on；若选择表达式Q？P:0的逻辑运算结果为0，则电压C取值为0V；电压D取值为0V；
When the type of logic operation is AND logic operation: if the logic operation result of the expression Q? P:0 is 1, the voltage C takes the value of V on ; if the logic operation result of the expression Q? P:0 is 0, the voltage C takes the value of 0V; the voltage D takes the value of 0V;
当逻辑运算的类型为与非逻辑运算时：若选择表达式
的逻辑运算结果为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若选择表达式
的逻辑运算结 果为0，则电压C取值为0V，此时，电压D取值为0V；
When the logical operation type is AND-NOT logical operation: If you select Expression The logical operation result is 1, then the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the expression is selected The logical operation result is 0, then the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为或逻辑运算时：在选择表达式Q？1:P的逻辑运算结果为1的情况下，电压C取值为V
on，此时，若逻辑值P取值为1，则电压D取值为-2V
2；若逻辑值P取值为0，则电压D取值为0V；在选择表达式Q？1:P的逻辑运算结果为0的情况下，电压C取值为0V，此时，电压D取值为0V；
When the type of logic operation is an OR logic operation: when the logic operation result of the selection expression Q? 1:P is 1, the voltage C takes the value of V on . At this time, if the logic value P takes the value of 1, the voltage D takes the value of -2V 2 ; if the logic value P takes the value of 0, the voltage D takes the value of 0V; when the logic operation result of the selection expression Q? 1:P is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V;
当逻辑运算的类型为或非逻辑运算时：若选择表达式
的逻辑运算结果为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若选择表达式
的逻辑运算结果为0，则电压C取值为0V，此时，电压D取值为0V；
When the logical operation type is OR or NOT logical operation: If you select Expression The logical operation result is 1, then the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the expression is selected The logical operation result is 0, then the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为实质蕴涵逻辑运算时：在选择表达式
的逻辑运算结果为1的情况下，电压C取值为V
on，此时，若逻辑值P取值为1，则电压D取值为0V；若逻辑值P取值为0，则电压D取值为-2V
2；在选择表达式
的逻辑运算结果为0的情况下，电压C取值为0V，此时，电压D取值为0V；
When the type of logical operation is a substantial implication logical operation: In the selection expression When the logical operation result is 1, the voltage C takes the value V on . At this time, if the logical value P takes the value 1, the voltage D takes the value 0V; if the logical value P takes the value 0, the voltage D takes the value -2V 2 ; when selecting the expression When the result of the logical operation is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V.
当逻辑运算的类型为负实质蕴涵逻辑运算时：若选择表达式Q？0:P的逻辑运算结果为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若选择表达式Q？0:P的逻辑运算结果为0，则电压C取值为0V，此时，电压D取值为0V；
When the type of logical operation is a negative substantial implied logical operation: if the logical operation result of the expression Q? 0:P is 1, the voltage C takes a value of V on , and at this time, the voltage D takes a value of -2V 2 ; if the logical operation result of the expression Q? 0:P is 0, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;
当逻辑运算的类型为反实质蕴涵逻辑运算时：若选择表达式Q？P:1的逻辑运算结果为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若选择表达式Q？P:1的逻辑运算结果为0，则电压C取值为0V，此时，电压D取值为0V；
When the type of logical operation is the inverse substantive implication logical operation: if the logical operation result of the expression Q? P:1 is 1, the voltage C takes the value of V on , at which time, the voltage D takes the value of -2V 2 ; if the logical operation result of the expression Q? P:1 is 0, the voltage C takes the value of 0V, at which time, the voltage D takes the value of 0V;
当逻辑运算的类型为反负实质蕴涵逻辑运算时：若选择表达式
的逻辑运算结果为1，则电压C取值为V
on；若选择表达式
的逻辑运算结果为0，则电压C取值为0V；电压D取值为0V；
When the type of logical operation is a negative implied logical operation: If you select the expression The logical operation result is 1, then the voltage C takes the value V on ; if the expression is selected The logical operation result is 0, then the voltage C takes the value of 0V; the voltage D takes the value of 0V;
当逻辑运算的类型为异或逻辑运算时：在选择表达式
的逻辑运算结果为1的情况下，电压C取值为V
on，此时，若逻辑值P取值为1，则电压D取值为-2V
2；若逻辑值P取值为0，则电压D取值为0V；在选择表达式
的逻辑运算结果为0的情况下，电压C取值为0V，此时，电压D取值为0V；
When the logical operation type is XOR logical operation: When selecting an expression When the logical operation result is 1, the voltage C takes the value V on . At this time, if the logical value P takes the value 1, the voltage D takes the value -2V 2 ; if the logical value P takes the value 0, the voltage D takes the value 0V. When selecting the expression When the result of the logical operation is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V.
当逻辑运算的类型为同或逻辑运算时：在选择表达式
的逻辑运算结果为1的情况下，电压C取值为V
on，此时，若逻辑值P取值为1，则电压D取值为0V； 若逻辑值P取值为0，则电压D取值为-2V
2；在选择表达式
的逻辑运算结果为0的情况下，电压C取值为0V，此时，电压D取值为0V；
When the logical operation type is X or Y logical operation: When selecting an expression When the result of the logical operation is 1, the voltage C takes the value V on . At this time, if the logical value P takes the value 1, the voltage D takes the value 0V; if the logical value P takes the value 0, the voltage D takes the value -2V 2 ; when selecting the expression When the result of the logical operation is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V.
其中，V
on为第一晶体管或第二晶体管工作在线性区的电压；第一晶体管和第二晶体管均为NMOS晶体管；V
2＝V-V
1。
Wherein, V on is the voltage when the first transistor or the second transistor operates in the linear region; the first transistor and the second transistor are both NMOS transistors; and V 2 =VV 1 .
进一步优选地，V
2取值为
Further preferably, V2 is
进一步优选地，电阻的阻值大小介于忆阻器M
1或忆阻器M
2的高阻态阻值与低阻态阻值之间；电阻的阻值为
其中R
H为忆阻器M
1或忆阻器M
2的高阻态电阻值，R
L为忆阻器M
1或忆阻器M
2的低阻态电阻值。
Further preferably, the resistance value of the resistor is between the high resistance value and the low resistance value of the memristor M1 or the memristor M2 ; the resistance value of the resistor is Wherein RH is the high-resistance resistance value of the memristor M1 or the memristor M2 , and RL is the low-resistance resistance value of the memristor M1 or the memristor M2 .
进一步优选地，上述完备非易失布尔逻辑电路还包括：读取电路；其中，读取电路包括：与电阻的第一端相连的传输门电路，以及与传输门电路的输出端相连的比较器，用于读取忆阻器M
2的阻态。
Further preferably, the above-mentioned complete non-volatile Boolean logic circuit also includes: a reading circuit; wherein the reading circuit includes: a transmission gate circuit connected to the first end of the resistor, and a comparator connected to the output end of the transmission gate circuit, for reading the resistance state of the memristor M2 .
第二方面，本发明提供了一种完备非易失布尔逻辑电路的控制方法，应用于本发明第一方面所提供的完备非易失布尔逻辑电路中的控制单元，包括以下步骤：In a second aspect, the present invention provides a control method for a complete non-volatile Boolean logic circuit, which is applied to a control unit in the complete non-volatile Boolean logic circuit provided in the first aspect of the present invention, and comprises the following steps:
S1、将忆阻器M
1和忆阻器M
2均初始化为高阻态；
S1, initializing both memristor M1 and memristor M2 to a high impedance state;
S2、判断当前操作是否为与逻辑值Q有关的操作，若是，则将忆阻器M
1置为逻辑值Q所对应的阻态；其中，与逻辑值Q有关的操作包括对逻辑值P和逻辑值Q进行逻辑运算的操作和仅对逻辑值Q进行逻辑运算的操作；
S2, determining whether the current operation is an operation related to the logic value Q, and if so, setting the memristor M1 to a resistance state corresponding to the logic value Q; wherein the operation related to the logic value Q includes an operation of performing a logic operation on the logic value P and the logic value Q and an operation of performing a logic operation only on the logic value Q;
S3、通过位线BL
0对忆阻器M
1施加电压-V
0，通过位线BL
1对忆阻器M
2施加电压V
1，在字线WL上施加电压C，在源控制端上施加电压D，并读取忆阻器M
2的阻态，即为逻辑运算结果；
S3, applying a voltage -V 0 to the memristor M 1 through the bit line BL 0 , applying a voltage V 1 to the memristor M 2 through the bit line BL 1 , applying a voltage C to the word line WL, applying a voltage D to the source control terminal, and reading the resistance state of the memristor M 2 , which is the result of the logic operation;
其中，V
0和V
1同时满足：V
set/2≤V
0<V
set，V
set/2≤V
1<V
set，且V
0+V
1≥V；V
set为忆阻器M
1或忆阻器M
2由高阻态转变为低阻态的阈值；V为忆阻器M
1或忆阻器M
2阈值电压变化波动范围的上限；
Wherein, V 0 and V 1 simultaneously satisfy: V set /2≤V 0 <V set , V set /2≤V 1 <V set , and V 0 +V 1 ≥V; V set is the threshold at which the memristor M 1 or the memristor M 2 changes from a high resistance state to a low resistance state; V is the upper limit of the fluctuation range of the threshold voltage of the memristor M 1 or the memristor M 2 ;
电压C的取值由逻辑运算类型和逻辑值Q、P决定，电压D的取值由逻辑运算类型、逻辑值P以及电压C决定。The value of voltage C is determined by the logic operation type and the logic values Q and P, and the value of voltage D is determined by the logic operation type, the logic value P and voltage C.
进一步优选地，当逻辑运算的类型为真逻辑运算时，电压C取值为V
on，电压D取值为0V；
Further preferably, when the type of logic operation is a true logic operation, the voltage C takes a value of V on , and the voltage D takes a value of 0V;
当逻辑运算的类型为假逻辑运算时，电压C取值为0V，电压D取值为0V；When the type of logic operation is false logic operation, the voltage C takes a value of 0V and the voltage D takes a value of 0V;
当逻辑运算的类型为P逻辑运算时：若逻辑值P为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若逻辑值P为0，则电压C取值为0V，此时，电压D取值为0V；
When the type of logic operation is P logic operation: if the logic value P is 1, the voltage C takes the value V on , at this time, the voltage D takes the value -2V 2 ; if the logic value P is 0, the voltage C takes the value 0V, at this time, the voltage D takes the value 0V;
当逻辑运算的类型为Q逻辑运算时：若逻辑值Q为1，则电压C取值为V
on；若逻辑值Q为0，则电压C取值为0V；电压D取值为0V；
When the type of logic operation is Q logic operation: if the logic value Q is 1, the voltage C takes the value V on ; if the logic value Q is 0, the voltage C takes the value 0V; the voltage D takes the value 0V;
当逻辑运算的类型为非P逻辑运算时：若逻辑值P为1，则电压C取值为0V，此时，电压D取值为0V；若逻辑值P为0，则电压C取值为V
on，此时，电压D取值为-2V
2；
When the type of logic operation is non-P logic operation: if the logic value P is 1, the voltage C takes a value of 0V, at which time, the voltage D takes a value of 0V; if the logic value P is 0, the voltage C takes a value of V on , at which time, the voltage D takes a value of -2V 2 ;
当逻辑运算的类型为非Q逻辑运算时：若逻辑值Q为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若逻辑值Q为0，则电压C取值为0V，此时，电压D取值为0V；
When the type of logic operation is non-Q logic operation: if the logic value Q is 1, the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the logic value Q is 0, the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为与逻辑运算时：若选择表达式Q？P:0的逻辑运算结果为1，则电压C取值为V
on；若选择表达式Q？P:0的逻辑运算结果为0，则电压C取值为0V；电压D取值为0V；
When the type of logic operation is AND logic operation: if the logic operation result of the expression Q? P:0 is 1, the voltage C takes the value of V on ; if the logic operation result of the expression Q? P:0 is 0, the voltage C takes the value of 0V; the voltage D takes the value of 0V;
当逻辑运算的类型为与非逻辑运算时：若选择表达式
的逻辑运算结果为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若选择表达式
的逻辑运算结果为0，则电压C取值为0V，此时，电压D取值为0V；
When the logical operation type is AND-NOT logical operation: If you select Expression The logical operation result is 1, then the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the expression is selected The logical operation result is 0, then the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为或逻辑运算时：在选择表达式Q？1:P的逻辑运算结果为1的情况下，电压C取值为V
on，此时，若逻辑值P取值为1，则电压D取值为-2V
2；若逻辑值P取值为0，则电压D取值为0V；在选择表达式Q？1:P的逻辑运算结果为0的情况下，电压C取值为0V，此时，电压D取值为0V；
When the type of logic operation is an OR logic operation: when the logic operation result of the selection expression Q? 1:P is 1, the voltage C takes the value of V on . At this time, if the logic value P takes the value of 1, the voltage D takes the value of -2V 2 ; if the logic value P takes the value of 0, the voltage D takes the value of 0V; when the logic operation result of the selection expression Q? 1:P is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V;
当逻辑运算的类型为或非逻辑运算时：若选择表达式
的逻辑运算结果为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若选择表达式
的逻辑运算结果为0，则电压C取值为0V，此时，电压D取值为0V；
When the logical operation type is OR or NOT logical operation: If you select Expression The logical operation result is 1, then the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the expression is selected The logical operation result is 0, then the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为实质蕴涵逻辑运算时：在选择表达式
的逻辑运算结果为1的情况下，电压C取值为V
on，此时，若逻辑值P取值为1，则电压D取值为 0V；若逻辑值P取值为0，则电压D取值为-2V
2；在选择表达式
的逻辑运算结果为0的情况下，电压C取值为0V，此时，电压D取值为0V；
When the type of logical operation is a substantial implication logical operation: In the selection expression When the logical operation result is 1, the voltage C takes the value V on . At this time, if the logical value P takes the value 1, the voltage D takes the value 0V; if the logical value P takes the value 0, the voltage D takes the value -2V 2 ; when selecting the expression When the result of the logical operation is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V.
当逻辑运算的类型为负实质蕴涵逻辑运算时：若选择表达式Q？0:P的逻辑运算结果为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若选择表达式Q？0:P的逻辑运算结果为0，则电压C取值为0V，此时，电压D取值为0V；
When the type of logical operation is a negative substantial implied logical operation: if the logical operation result of the expression Q? 0:P is 1, the voltage C takes a value of V on , and at this time, the voltage D takes a value of -2V 2 ; if the logical operation result of the expression Q? 0:P is 0, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;
当逻辑运算的类型为反实质蕴涵逻辑运算时：若选择表达式Q？P:1的逻辑运算结果为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若选择表达式Q？P:1的逻辑运算结果为0，则电压C取值为0V，此时，电压D取值为0V；
When the type of logical operation is the inverse substantive implication logical operation: if the logical operation result of the expression Q? P:1 is 1, the voltage C takes the value of V on , at which time, the voltage D takes the value of -2V 2 ; if the logical operation result of the expression Q? P:1 is 0, the voltage C takes the value of 0V, at which time, the voltage D takes the value of 0V;
当逻辑运算的类型为反负实质蕴涵逻辑运算时：若选择表达式
的逻辑运算结果为1，则电压C取值为V
on；若选择表达式
的逻辑运算结果为0，则电压C取值为0V；电压D取值为0V；
When the type of logical operation is a negative implied logical operation: If you select the expression The logical operation result is 1, then the voltage C takes the value V on ; if the expression is selected The logical operation result is 0, then the voltage C takes the value of 0V; the voltage D takes the value of 0V;
当逻辑运算的类型为异或逻辑运算时：在选择表达式
的逻辑运算结果为1的情况下，电压C取值为V
on，此时，若逻辑值P取值为1，则电压D取值为-2V
2；若逻辑值P取值为0，则电压D取值为0V；在选择表达式
的逻辑运算结果为0的情况下，电压C取值为0V，此时，电压D取值为0V；
When the logical operation type is XOR logical operation: When selecting an expression When the logical operation result is 1, the voltage C takes the value V on . At this time, if the logical value P takes the value 1, the voltage D takes the value -2V 2 ; if the logical value P takes the value 0, the voltage D takes the value 0V. When selecting the expression When the result of the logical operation is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V.
当逻辑运算的类型为同或逻辑运算时：在选择表达式
的逻辑运算结果为1的情况下，电压C取值为V
on，此时，若逻辑值P取值为1，则电压D取值为0V；若逻辑值P取值为0，则电压D取值为-2V
2；在选择表达式
的逻辑运算结果为0的情况下，电压C取值为0V，此时，电压D取值为0V；
When the logical operation type is X or Y logical operation: When selecting an expression When the logical operation result is 1, the voltage C takes the value V on . At this time, if the logical value P takes the value 1, the voltage D takes the value 0V; if the logical value P takes the value 0, the voltage D takes the value -2V 2 ; when selecting the expression When the result of the logical operation is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V;
其中，V
on为第一晶体管或第二晶体管工作在线性区的电压；第一晶体管和第二晶体管均为NMOS晶体管；V
2＝V-V
1。
Wherein, V on is the voltage when the first transistor or the second transistor operates in the linear region; the first transistor and the second transistor are both NMOS transistors; and V 2 =VV 1 .
第三方面，本发明提供了一种基于上述完备非易失布尔逻辑电路的逐位逻辑级联方法，包括：In a third aspect, the present invention provides a bit-by-bit logic cascading method based on the above-mentioned complete non-volatile Boolean logic circuit, comprising:
将按照第二方面所述控制方法操作所得的前一步逻辑运算结果作为新的输入逻辑值Q，重新按照第二方面所述的控制方法进行操作，从而实现逐位逻辑级联。The previous logic operation result obtained by operating according to the control method described in the second aspect is used as a new input logic value Q, and the control method described in the second aspect is re-operated to achieve bit-by-bit logic cascading.
第四方面，本发明提出了一种完备非易失布尔逻辑并行运算电路，包括多个本发明第一方面所提供的完备非易失布尔逻辑运算电路；In a fourth aspect, the present invention provides a complete non-volatile Boolean logic parallel operation circuit, comprising a plurality of complete non-volatile Boolean logic operation circuits provided in the first aspect of the present invention;
各完备非易失布尔逻辑运算电路的忆阻器M
1的正极均连接在同一条位线BL
0上，忆阻器M
2的正极均连接在同一条位线BL
1上，用于在同一个逻辑计算脉冲周期内，并行实现多个逻辑运算。
The positive electrodes of the memristors M1 of each complete nonvolatile Boolean logic operation circuit are connected to the same bit line BL0 , and the positive electrodes of the memristors M2 are connected to the same bit line BL1 , so as to realize multiple logic operations in parallel within the same logic calculation pulse cycle.
总体而言，通过本发明所构思的以上技术方案，能够取得以下有益效果：In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects:
1、本发明提供了一种基于1T1R阵列的完备非易失布尔逻辑运算电路，用于对输入的逻辑值P和/或逻辑值Q进行逻辑运算；该逻辑电路主要由忆阻器、晶体管和电阻构成，忆阻器M
1的输入阻态根据逻辑输入Q来决定，输入电压固定为-V
0，M
2的输入电压固定为V
1，字线WL上的输入电压C由逻辑运算类型和逻辑值Q、P决定；源控制端上的输入电压D由逻辑运算类型、逻辑值P以及电压C决定，忆阻器M
2的阻态作为计算结果的输出；本发明在逻辑算法上充分利用了1T1R结构中晶体管的开关特性，通过动态的对该电路字线WL和源控制端上的输入电压进行配置，即可将实现完备的布尔逻辑功能的步骤控制到两步，能够以较少的操作步数和固定电路拓扑结构提高非易失布尔逻辑运算效率。
1. The present invention provides a complete non-volatile Boolean logic operation circuit based on a 1T1R array, which is used for performing a logic operation on an input logic value P and/or a logic value Q; the logic circuit is mainly composed of a memristor, a transistor and a resistor, the input resistance state of the memristor M1 is determined according to the logic input Q, the input voltage is fixed at -V0 , the input voltage of M2 is fixed at V1 , the input voltage C on the word line WL is determined by the logic operation type and the logic values Q and P; the input voltage D on the source control terminal is determined by the logic operation type, the logic value P and the voltage C, and the resistance state of the memristor M2 is used as the output of the calculation result; the present invention fully utilizes the switching characteristics of the transistors in the 1T1R structure in the logic algorithm, and by dynamically configuring the input voltages on the word line WL and the source control terminal of the circuit, the steps for realizing a complete Boolean logic function can be controlled to two steps, and the efficiency of non-volatile Boolean logic operation can be improved with fewer operation steps and a fixed circuit topology.
2、本发明所提供的完备非易失布尔逻辑运算电路，当需要得到实时输出结果时，不需要增加传统方案的读步骤，通过开启传输门开关，可以实现采样定值电阻上的电流，与固定参考电压值进行比较，即可同步得到数字域的计算结果，有利于实现数模混合系统的搭建。2. The complete non-volatile Boolean logic operation circuit provided by the present invention does not need to add the reading step of the traditional solution when real-time output results are required. By turning on the transmission gate switch, the current on the sampled fixed resistor can be compared with the fixed reference voltage value to synchronously obtain the calculation result in the digital domain, which is conducive to the construction of a digital-analog hybrid system.
3、本发明所提供的完备非易失布尔逻辑运算电路，在逻辑计算的操作过程中，忆阻器M
1的阻态不发生改变，整个操作过程为非破坏式，有利于保护输入信息的完整性。
3. In the complete non-volatile Boolean logic operation circuit provided by the present invention, the resistance state of the memristor M1 does not change during the operation of the logic calculation, and the entire operation process is non-destructive, which is conducive to protecting the integrity of the input information.
4、本发明提供了一种基于上述完备非易失布尔逻辑电路的逐位逻辑级联方法，可以将前一步逻辑计算得到的结果直接作为后一步逻辑操作的输入，逻辑级联简单易行，有助于实现更加复杂的逻辑功能。4. The present invention provides a bit-by-bit logic cascade method based on the above-mentioned complete non-volatile Boolean logic circuit, which can directly use the result obtained from the previous step of logic calculation as the input of the next step of logic operation. The logic cascade is simple and easy, which helps to realize more complex logic functions.
5、本发明提供了一种完备非易失布尔逻辑并行运算电路，包括多个上述完备非易失布尔逻辑运算电路，各完备非易失布尔逻辑运算电路的忆阻器M
1的正极均连接在同一条位线BL
0上，忆阻器M
2的正极均连接在同一条位线BL
1上，位线BL
0固定输入电压-V
0，位线BL
1固定输入电压V
1，只需分别控制各行字线WL和源控制端上 输入的电压C和电压D，即可在同一个逻辑计算脉冲周期内，并行实现多个逻辑运算。本发明所需的操作步数较少，采用1T1R阵列可以完全避开大规模并行处理时的漏电流导致的误操作或者操作不成功问题，因为BL端激励固定，可以实现在一个时钟周期内可以同时实现多个逻辑运算，大幅度提高了计算并行度和效率，增加了利用非易失器件做计算的优势。
5. The present invention provides a complete non-volatile Boolean logic parallel operation circuit, comprising a plurality of the above-mentioned complete non-volatile Boolean logic operation circuits, wherein the positive electrodes of the memristors M1 of the complete non-volatile Boolean logic operation circuits are all connected to the same bit line BL0 , and the positive electrodes of the memristors M2 are all connected to the same bit line BL1 , the bit line BL0 has a fixed input voltage of -V0 , and the bit line BL1 has a fixed input voltage of V1 , and it is only necessary to control the voltage C and the voltage D input to each row word line WL and the source control terminal respectively, so that multiple logic operations can be realized in parallel within the same logic calculation pulse cycle. The present invention requires fewer operation steps, and the use of a 1T1R array can completely avoid the problem of misoperation or unsuccessful operation caused by leakage current during large-scale parallel processing. Because the BL terminal excitation is fixed, multiple logic operations can be realized simultaneously within one clock cycle, which greatly improves the calculation parallelism and efficiency, and increases the advantage of using non-volatile devices for calculation.
图1为本发明提供的基于1T1R阵列的完备非易失布尔逻辑运算电路的结构示意图；FIG1 is a schematic diagram of the structure of a complete non-volatile Boolean logic operation circuit based on a 1T1R array provided by the present invention;
图2为本发明提供完备非易失布尔逻辑运算电路中所用的基于忆阻器的1T1R结构示意图及其I-V特性100次循环测试图；其中，(a)为1T1R结构示意图；(b)为1T1R结构的I-V特性100次循环测试图；FIG2 is a schematic diagram of a 1T1R structure based on a memristor used in a complete non-volatile Boolean logic operation circuit provided by the present invention and a 100-cycle test diagram of its I-V characteristics; wherein (a) is a schematic diagram of the 1T1R structure; (b) is a 100-cycle test diagram of the I-V characteristics of the 1T1R structure;
图3为本发明提供的带读取电路的完备非易失布尔逻辑运算电路的结构示意图；FIG3 is a schematic diagram of the structure of a complete non-volatile Boolean logic operation circuit with a read circuit provided by the present invention;
图4为本发明提供的完备非易失布尔逻辑并行运算电路示意图；FIG4 is a schematic diagram of a complete non-volatile Boolean logic parallel operation circuit provided by the present invention;
图5为本发明提供的四位输入按位异或逻辑计算的仿真结果以及WL和SL端根据输入所配置的电压关系；FIG5 is a simulation result of a bitwise XOR logic calculation of a four-bit input provided by the present invention and a voltage relationship between WL and SL terminals configured according to the input;
图6为本发明提供的每一行作为保存输出结果的忆阻器M
2在逻辑计算过程中电阻状态的变化结果示意图；
FIG6 is a schematic diagram showing the change of the resistance state of each row of memristors M2 used for storing output results during the logic calculation process provided by the present invention;
图7为本发明提供的每一行输出忆阻器M
2在逻辑计算过程中两端电压降的变化结果示意图；
FIG7 is a schematic diagram showing the change of the voltage drop across the two ends of each row of output memristors M2 provided by the present invention during the logic calculation process;
图8为本发明提供的以高低电平形式输出的数字域计算结果示意图。FIG8 is a schematic diagram of a digital domain calculation result output in the form of high and low levels provided by the present invention.
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。此外，下面所描述的本发明各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
为了实现上述目的，第一方面，如图1所示，本发明提供了一种基于1T1R阵列的完备非易失布尔逻辑运算电路，用于对输入的逻辑值P和/或输入的逻辑值Q进行逻辑运算；In order to achieve the above-mentioned object, in a first aspect, as shown in FIG1 , the present invention provides a complete non-volatile Boolean logic operation circuit based on a 1T1R array, which is used to perform a logic operation on an input logic value P and/or an input logic value Q;
上述逻辑电路包括：控制单元、忆阻器M
1、忆阻器M
2、第一晶体管、第二晶体管和电阻；
The above logic circuit includes: a control unit, a memristor M 1 , a memristor M 2 , a first transistor, a second transistor and a resistor;
忆阻器M
1的正极与位线BL
0相连，负极与第一晶体管的漏极端相连；忆阻器M
2的正极与位线BL
1相连，负极与第二晶体管的漏极端相连；第一晶体管和第二晶体管的栅极连接在同一条字线WL上，源极连接在同一条源线SL上；第一晶体管和第二晶体管的源极通过源线SL引出后与电阻的第一端相连，电阻的第二端作为源控制端；第一晶体管和第二晶体管相同；忆阻器M
1和忆阻器M
2相同，且初始状态均为高阻态；
The positive electrode of the memristor M1 is connected to the bit line BL0 , and the negative electrode is connected to the drain terminal of the first transistor; the positive electrode of the memristor M2 is connected to the bit line BL1 , and the negative electrode is connected to the drain terminal of the second transistor; the gates of the first transistor and the second transistor are connected to the same word line WL, and the sources are connected to the same source line SL; the sources of the first transistor and the second transistor are connected to the first end of the resistor after being led out through the source line SL, and the second end of the resistor serves as the source control end; the first transistor and the second transistor are the same; the memristor M1 and the memristor M2 are the same, and both are in a high-impedance state in the initial state;
控制单元用于在进行逻辑运算时，通过位线BL
0对忆阻器M
1施加电压-V
0，通过位线BL
1对忆阻器M
2施加电压V
1，在字线WL上施加电压C，在源控制端上施加电压D，并读取忆阻器M
2的阻态，即为逻辑运算结果；
The control unit is used to apply a voltage -V 0 to the memristor M 1 through the bit line BL 0 , apply a voltage V 1 to the memristor M 2 through the bit line BL 1 , apply a voltage C to the word line WL, apply a voltage D to the source control terminal, and read the resistance state of the memristor M 2 , which is the result of the logic operation;
其中，当逻辑电路执行与逻辑值Q有关的操作时，控制单元还用于在进行逻辑运算之前，将忆阻器M
1置为逻辑值Q所对应的阻态；与逻辑值Q有关的操作包括对逻辑值P和逻辑值Q进行逻辑运算的操作和仅对逻辑值Q进行逻辑运算的操作；
Wherein, when the logic circuit performs an operation related to the logic value Q, the control unit is further used to set the memristor M1 to a resistance state corresponding to the logic value Q before performing the logic operation; the operation related to the logic value Q includes an operation of performing a logic operation on the logic value P and the logic value Q and an operation of performing a logic operation only on the logic value Q;
需要说明的是，逻辑操作过程中采用的激励信号均为电压脉冲信号；为满足逻辑运算要求，V
0和V
1应同时满足：V
set/2≤V
0<V
set，V
set/2≤V
1<V
set，且V
0+V
1≥V；V
set为忆阻器M
1或忆阻器M
2由高阻态转变为低阻态的阈值；V为忆阻器M
1或忆阻器M
2阈值电压变化波动范围的上限；在一种可选实施例下，V＝E
set+3RMS
setE
set为V
set的均值；RMS
set为V
set的均方差。具体地，V
1电压幅值介于V
set与V
set/2之间可以使得V
1不足以使原处于高阻态的忆阻器向低阻态变化；同时，当忆阻器两端加上大于或等于电压V的压降时，能够确保忆阻器发生阻态变化；因为BL端几乎没有压降损失，SL端电压损失较多，根据仿真测试结果，V
0的取值优选为
V
1的取值优选为
It should be noted that the excitation signals used in the logic operation process are all voltage pulse signals; to meet the logic operation requirements, V0 and V1 should simultaneously satisfy: Vset / 2≤V0 < Vset , Vset / 2≤V1 < Vset , and V0 + V1≥V ; Vset is the threshold at which the memristor M1 or the memristor M2 changes from a high-resistance state to a low-resistance state; V is the upper limit of the fluctuation range of the threshold voltage change of the memristor M1 or the memristor M2 ; in an optional embodiment, V= Eset +3RMSset Eset is the mean of Vset ; RMSset is the mean square error of Vset . Specifically, the voltage amplitude of V1 is between Vset and Vset /2, which can make V1 insufficient to change the memristor originally in a high-resistance state to a low-resistance state; at the same time, when a voltage drop greater than or equal to the voltage V is added across the memristor, it can ensure that the resistance state of the memristor changes; because there is almost no voltage drop loss at the BL end and more voltage loss at the SL end, according to the simulation test results, the value of V0 is preferably The value of V1 is preferably
电压C的取值由逻辑运算类型和逻辑值Q、P决定，电压D的取值由逻辑运算 类型、逻辑值P以及电压C决定。The value of voltage C is determined by the logic operation type and the logic values Q and P, and the value of voltage D is determined by the logic operation type, the logic value P and voltage C.
以在0.18工艺节点下的NMOS晶体管为例，如图2所示为上述完备非易失布尔逻辑运算电路中所用的基于忆阻器的1T1R结构示意图及其I-V特性100次循环测试图；其中，图(a)为1T1R结构示意图；图(b)为1T1R结构的I-V特性100次循环测试图。Taking the NMOS transistor at the 0.18 process node as an example, as shown in Figure 2, it is a schematic diagram of the 1T1R structure based on the memristor used in the above-mentioned complete non-volatile Boolean logic operation circuit and its I-V characteristic 100 cycle test diagram; among them, Figure (a) is a schematic diagram of the 1T1R structure; Figure (b) is a 100 cycle test diagram of the I-V characteristics of the 1T1R structure.
具体的，当在晶体管的栅极施加2.5V，源极和衬底接GND，忆阻器的正极施加正向电压，忆阻器的阻值被设置到低阻态；当在晶体管的栅极施加3.3V的电压，在忆阻器的正极施加负向电压V
reset，并使源极和衬底接GND时，忆阻器的阻值被设置到高阻态；通过控制晶体管栅端和忆阻器端的电压，可以使忆阻器在高阻态与低阻态之间转换。本发明中忆阻器的高阻态对应逻辑值“0”，忆阻器的低阻态对应逻辑值“1”。
Specifically, when 2.5V is applied to the gate of the transistor, the source and the substrate are connected to GND, and a positive voltage is applied to the positive electrode of the memristor, the resistance of the memristor is set to a low resistance state; when a voltage of 3.3V is applied to the gate of the transistor, a negative voltage V reset is applied to the positive electrode of the memristor, and the source and the substrate are connected to GND, the resistance of the memristor is set to a high resistance state; by controlling the voltages at the gate terminal of the transistor and the memristor terminal, the memristor can be switched between a high resistance state and a low resistance state. In the present invention, the high resistance state of the memristor corresponds to a logic value "0", and the low resistance state of the memristor corresponds to a logic value "1".
优选地，本发明提出的逻辑电路，忆阻器件的开关比在[10，500]区间，大开关比可以使得忆阻器的低阻态、高阻态和定值电阻R的阻值能够明显区分，有利于基于分压关系完成逻辑计算。Preferably, in the logic circuit proposed in the present invention, the switching ratio of the memristor device is in the range of [10, 500]. The large switching ratio can make the resistance of the low resistance state, high resistance state and fixed resistance R of the memristor clearly distinguishable, which is conducive to completing logical calculations based on the voltage division relationship.
进一步地，电阻的阻值大小介于忆阻器M
1或忆阻器M
2的高阻态阻值与低阻态阻值之间；在一些可选实施方式下，定值电阻取值为
在该电路中主要起到可以区分忆阻器高低阻值的分压作用。考虑到忆阻器的高阻态与低阻态都存在一定的波动范围，定值电阻R的选取可以略大于
的结果，为该电路可靠性提供更好的保障。
Furthermore, the resistance value of the resistor is between the high resistance value and the low resistance value of the memristor M1 or the memristor M2 ; in some optional implementations, the fixed value resistor is In this circuit, it mainly plays the role of voltage division to distinguish the high and low resistance values of the memristor. Considering that the high and low resistance states of the memristor have a certain fluctuation range, the fixed value resistor R can be selected to be slightly larger than The result provides better guarantee for the reliability of the circuit.
进一步地，在一种可选实施方式下，如图3所示，上述完备非易失布尔逻辑电路还包括：读取电路；其中，读取电路包括：与电阻的第一端相连的传输门电路，以及与传输门电路的输出端相连的比较器，用于读取忆阻器M
2的阻态。本发明提供了一种逻辑计算读取电路，在逻辑计算脉冲中通过采样定值电阻端的节点电压电流，将比较器加入电路可实现实时获取数字域的输出结果。具体地，通过BL
0给M
1施加恒定操作电压脉冲幅值A＝-V
0，通过BL
1给M
2施加恒定操作电压脉冲幅值B＝V
1，通过控制端WL上的电压C控制晶体管的开启和关闭状态，通过SL端给定值电阻一端施加电压D，一同完成相应的逻辑计算操作，计算结果以电阻状态的形式保存在 输出忆阻器M
2中；同时在读取操过程中通过控制传输门使能端来选择是否得到数字式的输出结果，比较器参考电压在所有类型的逻辑计算中为固定电压值，空置状态各引脚浮空。需要说明的是，比较器的输入电压为源线电压，经过晶体管连接忆阻器下电极，通过字线WL施加电压V
on的行晶体管工作在线性区，其上的压降很小可以忽略不计，根据忆阻器状态翻转原理，变为电阻前此节点的压降需要降到大于等于V/3忆阻器才会从高阻变为低阻，所以可以把参考电压固定设置为-V
2/2，当比较器输入电压小于-V
2/2时，比较器输出电平翻转，外接数字电路D触发器采样上升沿得到数字域的结果。也可以把参考电压固定设置为V
2/2，因为变为低阻后的忆阻器M
2会把采样节点电势拉高，而保持高阻的忆阻器M
2没有这个作用，因而设置为V
2/2同样可以区分忆阻器的两种状态变化。
Further, in an optional implementation, as shown in FIG3 , the above-mentioned complete non-volatile Boolean logic circuit further includes: a reading circuit; wherein the reading circuit includes: a transmission gate circuit connected to the first end of the resistor, and a comparator connected to the output end of the transmission gate circuit, for reading the resistance state of the memristor M 2. The present invention provides a logic calculation reading circuit, which can obtain the output result of the digital domain in real time by sampling the node voltage and current of the fixed value resistor end in the logic calculation pulse, and adding the comparator to the circuit. Specifically, a constant operating voltage pulse amplitude A=-V 0 is applied to M 1 through BL 0 , a constant operating voltage pulse amplitude B=V 1 is applied to M 2 through BL 1 , the on and off states of the transistor are controlled by the voltage C on the control end WL, and a voltage D is applied to one end of the fixed value resistor through the SL end, and the corresponding logic calculation operation is completed together, and the calculation result is stored in the output memristor M 2 in the form of a resistance state; at the same time, during the reading operation, the transmission gate enable end is controlled to select whether to obtain a digital output result, and the comparator reference voltage is a fixed voltage value in all types of logic calculations, and each pin is floating in the idle state. It should be noted that the input voltage of the comparator is the source line voltage, which is connected to the lower electrode of the memristor through the transistor. The row transistor that applies the voltage V on through the word line WL works in the linear region, and the voltage drop on it is very small and can be ignored. According to the principle of memristor state flipping, the voltage drop of this node needs to be reduced to greater than or equal to V/3 before it becomes a resistor, and the memristor will change from high resistance to low resistance. Therefore, the reference voltage can be fixed to -V 2 /2. When the comparator input voltage is less than -V 2 /2, the comparator output level flips, and the external digital circuit D flip-flop samples the rising edge to obtain the result in the digital domain. The reference voltage can also be fixed to V 2 /2, because the memristor M 2 that becomes low resistance will pull up the potential of the sampling node, while the memristor M 2 that maintains high resistance does not have this effect. Therefore, setting it to V 2 /2 can also distinguish the two state changes of the memristor.
本发明提供一种基于忆阻器的完备非易失布尔逻辑实现方法，只需2步操作完成16种逻辑计算，且满足易实现逻辑联级并在计算过程中保护输入信息的完整性的要求，具体地，如表1所示：The present invention provides a complete non-volatile Boolean logic implementation method based on memristor, which can complete 16 kinds of logic calculations in only two steps, and can meet the requirements of easy implementation of logic cascade and protection of the integrity of input information during the calculation process. Specifically, as shown in Table 1:
当逻辑运算的类型为真逻辑运算(TRUE)时，无论P、Q何种输入，WL端输入的电压C为固定电压V
on，SL端输入的电压D为固定电压脉冲幅值0，忆阻器M
1的阻态根据输入Q而定；
When the type of logic operation is true logic operation (TRUE), no matter what input P and Q are, the voltage C input to the WL terminal is a fixed voltage V on , the voltage D input to the SL terminal is a fixed voltage pulse amplitude of 0, and the resistance state of the memristor M1 is determined according to the input Q;
当逻辑运算的类型为假逻辑运算(FALSE)时，无论P、Q何种输入，WL输入的电压C为固定电压0V，SL端输入的电压D为固定电压0V，忆阻器M
1的阻态根据输入Q而定；
When the type of logic operation is a false logic operation (FALSE), no matter what the inputs P and Q are, the voltage C of the WL input is a fixed voltage of 0V, the voltage D of the SL terminal input is a fixed voltage of 0V, and the resistance state of the memristor M1 is determined according to the input Q;
当逻辑运算的类型为P逻辑运算(COPY P)时，以选择表达式P的结果选择V
on或0V施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)；如WL配置0V，则SL为0V，如WL配置V
on，SL端为固定电压脉冲幅值-2V
2。具体地，若逻辑值P为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若逻辑值P为0，则电压C取值为0V，此时，电压D取值为0V；
When the type of logic operation is P logic operation (COPY P), V on or 0V is selected to be applied to the WL terminal according to the result of the expression P (when the expression result is 1, V on is selected; when the expression result is 0, 0V is selected); if WL is configured with 0V, SL is 0V; if WL is configured with V on , the SL terminal is a fixed voltage pulse amplitude of -2V 2 . Specifically, if the logic value P is 1, the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the logic value P is 0, the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为Q逻辑运算(COPY Q)时：以选择表达式Q的结果选择V
on或0V施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)；如WL配置0V，则SL为0V，如WL配置V
on，SL端为固定电压脉冲幅值0， 忆阻器M
1的阻态根据输入的Q而定。具体地，若逻辑值Q为1，则电压C取值为V
on；若逻辑值Q为0，则电压C取值为0V；电压D取值为0V；
When the type of logic operation is Q logic operation (COPY Q): select V on or 0V to be applied to the WL terminal according to the result of the expression Q (when the expression result is 1, select V on ; when the expression result is 0, select 0V); if WL is configured with 0V, SL is 0V; if WL is configured with V on , the SL terminal is a fixed voltage pulse with an amplitude of 0, and the resistance state of the memristor M1 is determined according to the input Q. Specifically, if the logic value Q is 1, the voltage C takes the value of V on ; if the logic value Q is 0, the voltage C takes the value of 0V; the voltage D takes the value of 0V;
当逻辑运算的类型为非P逻辑运算(NOT P)时：以选择表达式
的结果选择V
on或0V施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)；如WL配置0V，则SL为0V，如WL配置V
on，SL端为固定脉冲幅值-2V
2。具体地，若逻辑值P为1，则电压C取值为0V，此时，电压D取值为0V；若逻辑值P为0，则电压C取值为V
on，此时，电压D取值为-2V
2；
When the type of logical operation is NOT P: Select the expression The result of the expression selects V on or 0V to be applied to the WL terminal (when the expression result is 1, select V on ; when the expression result is 0, select 0V); if WL is configured with 0V, SL is 0V; if WL is configured with V on , the SL terminal is a fixed pulse amplitude of -2V 2. Specifically, if the logic value P is 1, the voltage C takes a value of 0V, at which time, the voltage D takes a value of 0V; if the logic value P is 0, the voltage C takes a value of V on , at which time, the voltage D takes a value of -2V 2 ;
当逻辑运算的类型为非Q逻辑运算(NOT Q)时：以选择表达式Q的结果选择V
on或0V施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)；如WL配置0V，则SL为0V，如WL配置V
on，SL端为固定电压脉冲幅值-2V
2，忆阻器M
1的阻态根据输入Q而定。具体地，若逻辑值Q为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若逻辑值Q为0，则电压C取值为0V，此时，电压D取值为0V；
When the type of logic operation is NOT Q logic operation (NOT Q): select V on or 0V to be applied to the WL terminal according to the result of the expression Q (when the expression result is 1, select V on ; when the expression result is 0, select 0V); if WL is configured with 0V, SL is 0V; if WL is configured with V on , the SL terminal is a fixed voltage pulse amplitude of -2V 2 , and the resistance state of the memristor M 1 is determined according to the input Q. Specifically, if the logic value Q is 1, the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the logic value Q is 0, the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为与逻辑运算(AND)时：以选择表达式Q？P:0的结果选择V
on或0V施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)；如WL配置0V，则SL为0V，如WL配置V
on，SL端为固定电压脉冲幅值0，忆阻器M
1的阻态根据输入Q而定。具体地，若选择表达式Q？P:0的逻辑运算结果为1，则电压C取值为V
on；若选择表达式Q？P:0的逻辑运算结果为0，则电压C取值为0V；电压D取值为0V；
When the type of logic operation is AND logic operation (AND): select V on or 0V to be applied to the WL terminal according to the result of the expression Q? P:0 (when the result of the expression is 1, select V on ; when the result of the expression is 0, select 0V); if WL is configured with 0V, SL is 0V; if WL is configured with V on , the SL terminal is a fixed voltage pulse with an amplitude of 0, and the resistance state of the memristor M1 is determined according to the input Q. Specifically, if the result of the logic operation of the expression Q? P:0 is 1, the voltage C takes the value of V on ; if the result of the logic operation of the expression Q? P:0 is 0, the voltage C takes the value of 0V; the voltage D takes the value of 0V;
当逻辑运算的类型为与非逻辑运算(NAND)时：以选择表达式
的结果选择V
on或0V施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)；如WL配置0V，则SL为0V，如WL配置V
on，SL端为固定电压脉冲幅值-2V
2，忆阻器M
1的阻态根据输入Q而定。具体地，若选择表达式
的逻辑运算结果为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若选择表达式
的逻辑运算结果为0，则电压C取值为0V，此时，电压D取值为0V；
When the logical operation type is NAND: Select the expression The result of the expression selects V on or 0V to be applied to the WL terminal (when the expression result is 1, select V on ; when the expression result is 0, select 0V); if WL is configured with 0V, SL is 0V. If WL is configured with V on , the SL terminal is a fixed voltage pulse with an amplitude of -2V 2 , and the resistance state of the memristor M 1 depends on the input Q. Specifically, if the expression is selected The logical operation result is 1, then the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the expression is selected The logical operation result is 0, then the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为或逻辑运算(OR)时：以选择表达式Q？1:P的结果选择V
on或0V施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)； 如WL配置0V，则SL为0V，如WL配置V
on，根据输入P选择电压脉冲幅值-2V
2或者0V施加在SL端(P＝1时选择-2V
2，P＝0时选择0V)，忆阻器M
1的阻态根据输入Q而定。具体地，在选择表达式Q？1:P的逻辑运算结果为1的情况下，电压C取值为V
on，此时，若逻辑值P取值为1，则电压D取值为-2V
2；若逻辑值P取值为0，则电压D取值为0V；在选择表达式Q？1:P的逻辑运算结果为0的情况下，电压C取值为0V，此时，电压D取值为0V；
When the type of logic operation is an OR logic operation (OR): select V on or 0V to be applied to the WL terminal according to the result of the selection expression Q? 1:P (when the expression result is 1, select V on ; when the expression result is 0, select 0V); If WL is configured with 0V, SL is 0V. If WL is configured with V on , a voltage pulse amplitude of -2V 2 or 0V is selected according to the input P and applied to the SL terminal (when P=1, select -2V 2 , and when P=0, select 0V), and the resistance state of the memristor M 1 depends on the input Q. Specifically, when the logic operation result of the selection expression Q? 1:P is 1, the voltage C takes the value of V on . At this time, if the logic value P takes the value of 1, the voltage D takes the value of -2V 2 ; if the logic value P takes the value of 0, the voltage D takes the value of 0V; when the logic operation result of the selection expression Q? 1:P is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为或非逻辑运算(NOR)时：以选择表达式
的结果选择V
on或0V施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)；如WL配置0V，则SL为0V，如WL配置V
on，SL端为固定电压脉冲幅值-2V
2，忆阻器M
1的阻态根据输入Q而定。具体地，若选择表达式
的逻辑运算结果为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若选择表达式
的逻辑运算结果为0，则电压C取值为0V，此时，电压D取值为0V；
When the logical operation type is NOR: select the expression The result of the expression selects V on or 0V to be applied to the WL terminal (when the expression result is 1, select V on ; when the expression result is 0, select 0V); if WL is configured with 0V, SL is 0V. If WL is configured with V on , the SL terminal is a fixed voltage pulse with an amplitude of -2V 2 , and the resistance state of the memristor M 1 depends on the input Q. Specifically, if the expression is selected The logical operation result is 1, then the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the expression is selected The logical operation result is 0, then the voltage C takes the value of 0V, at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为实质蕴涵逻辑运算(IMP)时：以选择表达式
的结果选择V
on或0V施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)；如WL配置0V，则SL为0V，如WL配置V
on，根据输入P选择电压脉冲幅值0或者-2V
2施加在SL端(P＝1时选择0V，P＝0时选择-2V
2)，忆阻器M
1的阻态根据输入Q而定。具体地，在选择表达式
的逻辑运算结果为1的情况下，电压C取值为V
on，此时，若逻辑值P取值为1，则电压D取值为0V；若逻辑值P取值为0，则电压D取值为-2V
2；在选择表达式
的逻辑运算结果为0的情况下，电压C取值为0V，此时，电压D取值为0V；
When the type of logical operation is an intrinsic implication logical operation (IMP): select the expression The result of the expression selects V on or 0V to be applied to the WL terminal (when the expression result is 1, select V on ; when the expression result is 0, select 0V); if WL is configured with 0V, SL is 0V. If WL is configured with V on , a voltage pulse amplitude of 0 or -2V 2 is selected according to the input P and applied to the SL terminal (select 0V when P=1, select -2V 2 when P=0), and the resistance state of the memristor M 1 depends on the input Q. Specifically, when the expression is selected, When the logical operation result is 1, the voltage C takes the value V on . At this time, if the logical value P takes the value 1, the voltage D takes the value 0V; if the logical value P takes the value 0, the voltage D takes the value -2V 2 ; when selecting the expression When the result of the logical operation is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V.
当逻辑运算的类型为负实质蕴涵逻辑运算(NIMP)时：以选择表达式Q？0:P的结果选择V
on或0V施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)；如WL配置0V，则SL为0V，如WL配置V
on，SL端为固定电压脉冲幅值-2V
2，忆阻器M
1的阻态根据输入Q而定。具体地，若选择表达式Q？0:P的逻辑运算结果为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若选择表达式Q？0:P的逻辑运算结果为0，则电压C取值为0V，此时，电压D取值为0V；
When the type of logic operation is negative essential implication logic operation (NIMP): select V on or 0V to be applied to the WL terminal according to the result of the expression Q? 0:P (when the result of the expression is 1, select V on ; when the result of the expression is 0, select 0V); if WL is configured with 0V, SL is 0V; if WL is configured with V on , the SL terminal is a fixed voltage pulse amplitude of -2V 2 , and the resistance state of the memristor M 1 is determined according to the input Q. Specifically, if the result of the logic operation of the expression Q? 0:P is 1, the voltage C takes the value of V on , and at this time, the voltage D takes the value of -2V 2 ; if the result of the logic operation of the expression Q? 0:P is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为反实质蕴涵逻辑运算(RIMP)时：以选择表达式Q？P:1的 结果选择V
on或0V施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)；如WL配置0V，则SL为0V，如WL配置V
on，SL端为固定电压脉冲幅值-2V
2，忆阻器M
1的阻态根据输入Q而定。具体地，若选择表达式Q？P:1的逻辑运算结果为1，则电压C取值为V
on，此时，电压D取值为-2V
2；若选择表达式Q？P:1的逻辑运算结果为0，则电压C取值为0V，此时，电压D取值为0V；
When the type of logic operation is the inverse substantial implication logic operation (RIMP): select V on or 0V to be applied to the WL terminal according to the result of the expression Q? P:1 (when the result of the expression is 1, select V on ; when the result of the expression is 0, select 0V); if WL is configured with 0V, SL is 0V; if WL is configured with V on , the SL terminal is a fixed voltage pulse amplitude of -2V 2 , and the resistance state of the memristor M 1 is determined according to the input Q. Specifically, if the result of the logic operation of the expression Q? P:1 is 1, the voltage C takes the value of V on , and at this time, the voltage D takes the value of -2V 2 ; if the result of the logic operation of the expression Q? P:1 is 0, the voltage C takes the value of 0V, and at this time, the voltage D takes the value of 0V;
当逻辑运算的类型为反负实质蕴涵逻辑运算(RNIMP)时：以选择表达式
的结果选择V
on或0V施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)；如WL配置0V，则SL为0V，如WL配置V
on，SL端为固定电压脉冲幅值0，忆阻器M
1的阻态根据输入Q而定。具体地，若选择表达式
的逻辑运算结果为1，则电压C取值为V
on；若选择表达式
的逻辑运算结果为0，则电压C取值为0V；电压D取值为0V；
When the type of logical operation is the reverse negative implication logical operation (RNIMP): select the expression The result of the expression selects V on or 0V to be applied to the WL terminal (when the expression result is 1, select V on ; when the expression result is 0, select 0V); if WL is configured with 0V, SL is 0V, if WL is configured with V on , the SL terminal is a fixed voltage pulse with an amplitude of 0, and the resistance state of the memristor M1 depends on the input Q. Specifically, if the expression is selected The logical operation result is 1, then the voltage C takes the value V on ; if the expression is selected The logical operation result is 0, then the voltage C takes the value of 0V; the voltage D takes the value of 0V;
当逻辑运算的类型为异或逻辑运算(XOR)时：以选择表达式
的结果选择V
on或0施加在WL端(表达式结果为1时，选择V
on；表达式结果为0时，选择0V)；如WL配置0V，则SL一定为0V，如WL配置V
on，根据输入P选择电压脉冲幅值为-2V
2或者0V施加在SL端(P＝1时选择-2V
2，P＝0时选择0V)，忆阻器M
1的阻态根据输入Q而定；具体地，在选择表达式
的逻辑运算结果为1的情况下，电压C取值为V
on，此时，若逻辑值P取值为1，则电压D取值为-2V
2；若逻辑值P取值为0，则电压D取值为0V；在选择表达式
的逻辑运算结果为0的情况下，电压C取值为0V，此时，电压D取值为0V；
When the logical operation type is XOR: Select the expression The result of the expression selects V on or 0 to be applied to the WL terminal (when the expression result is 1, select V on ; when the expression result is 0, select 0V); if WL is configured with 0V, SL must be 0V. If WL is configured with V on , the voltage pulse amplitude is selected to be -2V 2 or 0V applied to the SL terminal according to the input P (select -2V 2 when P=1, select 0V when P=0), and the resistance state of the memristor M 1 depends on the input Q; specifically, when the expression is selected, When the logical operation result is 1, the voltage C takes the value V on . At this time, if the logical value P takes the value 1, the voltage D takes the value -2V 2 ; if the logical value P takes the value 0, the voltage D takes the value 0V. When selecting the expression When the result of the logical operation is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V.
当逻辑运算的类型为同或逻辑运算(XNOR)时：以选择表达式
的结果选择V
on或0施加在WL端；如WL配置0V，则SL为0V，如WL配置V
on，根据输入P选择电压脉冲幅值0V或者-2V
2施加在SL端(P＝0时选择-2V
2，P＝1时选择0V)，忆阻器M1的阻态根据输入Q而定。具体地，在选择表达式
的逻辑运算结果为1的情况下，电压C取值为V
on，此时，若逻辑值P取值为1，则电压D取值为0V；若逻辑值P取值为0，则电压D取值为-2V
2；在选择表达式
的逻辑运算结果为0的情况下，电压C取值为0V，此时，电压D取值为0V；
When the logical operation type is XNOR: Select the expression The result of , selects V on or 0 to be applied to the WL terminal; if WL is configured with 0V, SL is 0V, if WL is configured with V on , selects a voltage pulse amplitude of 0V or -2V 2 to be applied to the SL terminal according to the input P (select -2V 2 when P = 0, select 0V when P = 1), and the resistance state of the memristor M1 is determined by the input Q. Specifically, when selecting the expression When the logical operation result is 1, the voltage C takes the value V on . At this time, if the logical value P takes the value 1, the voltage D takes the value 0V; if the logical value P takes the value 0, the voltage D takes the value -2V 2 ; when selecting the expression When the result of the logical operation is 0, the voltage C takes the value of 0V. At this time, the voltage D takes the value of 0V.
其中，V
on为第一晶体管或第二晶体管工作在线性区的电压，此时晶体管源漏接 通，等效为可变电阻；上述第一晶体管和第二晶体管均为NMOS晶体管。以在0.18工艺节点下的晶体管为例，V
on取值为3.3V。V
2＝V-V
1，V
2的取值范围与忆阻器V
set的电压范围成比例关系，优选取值为
Wherein, V on is the voltage of the first transistor or the second transistor when it is operating in the linear region. At this time, the source and drain of the transistor are connected, which is equivalent to a variable resistor. The first transistor and the second transistor are both NMOS transistors. Taking the transistor at the 0.18 process node as an example, the value of V on is 3.3V. V 2 = VV 1 , the value range of V 2 is proportional to the voltage range of the memristor V set , and the preferred value is
表1Table 1
第二方面，本发明提供了一种完备非易失布尔逻辑电路的控制方法，应用于本 发明第一方面所提供的完备非易失布尔逻辑电路中的控制单元，包括以下步骤：In a second aspect, the present invention provides a control method for a complete non-volatile Boolean logic circuit, which is applied to a control unit in the complete non-volatile Boolean logic circuit provided in the first aspect of the present invention, and comprises the following steps:
S1、将忆阻器M
1和忆阻器M
2均初始化为高阻态；
S1, initializing both memristor M1 and memristor M2 to a high impedance state;
S2、判断当前操作是否为与逻辑值Q有关的操作，若是，则将忆阻器M
1置为逻辑值Q所对应的阻态；其中，与逻辑值Q有关的操作包括对逻辑值P和逻辑值Q进行逻辑运算的操作和仅对逻辑值Q进行逻辑运算的操作；
S2, determining whether the current operation is an operation related to the logic value Q, and if so, setting the memristor M1 to a resistance state corresponding to the logic value Q; wherein the operation related to the logic value Q includes an operation of performing a logic operation on the logic value P and the logic value Q and an operation of performing a logic operation only on the logic value Q;
S3、通过位线BL
0对忆阻器M
1施加电压-V
0，通过位线BL
1对忆阻器M
2施加电压V
1，在字线WL上施加电压C，在源控制端上施加电压D，并读取忆阻器M
2的阻态，即为逻辑运算结果；
S3, applying a voltage -V 0 to the memristor M 1 through the bit line BL 0 , applying a voltage V 1 to the memristor M 2 through the bit line BL 1 , applying a voltage C to the word line WL, applying a voltage D to the source control terminal, and reading the resistance state of the memristor M 2 , which is the result of the logic operation;
其中，V
0和V
1同时满足：V
set/2≤V
0<V
set，V
set/2≤V
1<V
set，且V
0+V
1≥V；V
set为忆阻器M
1或忆阻器M
2由高阻态转变为低阻态的阈值；V＝E
set+3RMS
set为忆阻器M
1或忆阻器M
2阈值电压变化波动范围的上限；E
set为V
set的均值；RMS
set为V
set的均方差；
Wherein, V 0 and V 1 simultaneously satisfy: V set /2≤V 0 <V set , V set /2≤V 1 <V set , and V 0 +V 1 ≥V; V set is the threshold at which the memristor M 1 or the memristor M 2 changes from a high resistance state to a low resistance state; V＝E set +3RMS set is the upper limit of the fluctuation range of the threshold voltage change of the memristor M 1 or the memristor M 2 ; E set is the mean value of V set ; RMS set is the mean square error of V set ;
电压C的取值由逻辑运算类型和逻辑值Q、P决定，电压D的取值由逻辑运算类型、逻辑值P以及电压C决定。The value of voltage C is determined by the logic operation type and the logic values Q and P, and the value of voltage D is determined by the logic operation type, the logic value P and voltage C.
相关技术方案同本发明第一方面所提供的完备非易失布尔逻辑运算电路，这里不做赘述。The related technical solution is the same as the complete non-volatile Boolean logic operation circuit provided in the first aspect of the present invention, and will not be described in detail here.
综上，本发明提供的由忆阻器、晶体管、定值电阻和可配置的比较器组成的逻辑电路，通过在控制端配置不同的操作电压，两步操作实现了16种完备逻辑计算，并同步得到数字域的计算结果。本发明的目的在于提供一种基于忆阻器(1T1R阵列)的完备非易失布尔逻辑电路及其控制方法，在使用尽可能少的操作步数和固定电路拓扑结构的同时，提高计算并行度及效率，增加计算可靠性，减少忆阻器阵列中漏电带来的计算错误，计算方案易实现逻辑联级并在计算过程中保护输入信息的完整性。因此本方案可作为一种通用逻辑实现方法。In summary, the logic circuit composed of a memristor, a transistor, a fixed resistor and a configurable comparator provided by the present invention realizes 16 complete logic calculations in two steps by configuring different operating voltages at the control end, and obtains the calculation results of the digital domain synchronously. The object of the present invention is to provide a complete non-volatile Boolean logic circuit based on a memristor (1T1R array) and a control method thereof, which improves the parallelism and efficiency of calculations, increases the reliability of calculations, reduces the calculation errors caused by leakage in the memristor array, and the calculation scheme is easy to realize logical cascading and protects the integrity of input information during the calculation process. Therefore, this scheme can be used as a general logic implementation method.
第三方面，本发明提供了一种基于上述完备非易失布尔逻辑电路的逐位逻辑级联方法，包括：In a third aspect, the present invention provides a bit-by-bit logic cascading method based on the above-mentioned complete non-volatile Boolean logic circuit, comprising:
将按照第二方面所述控制方法操作所得的前一步逻辑运算结果作为新的输入逻辑值Q，重新按照第二方面所述的控制方法进行操作，从而实现逐位逻辑级联。The previous logic operation result obtained by operating according to the control method described in the second aspect is used as a new input logic value Q, and the control method described in the second aspect is re-operated to achieve bit-by-bit logic cascading.
相关技术方案同本发明完备非易失布尔逻辑电路的控制方法，这里不做赘述。The related technical solutions are the same as the control method of the complete non-volatile Boolean logic circuit of the present invention, and will not be described in detail here.
第四方面，本发明提出了一种完备非易失布尔逻辑并行运算电路，包括多个本发明第一方面所提供的完备非易失布尔逻辑运算电路；In a fourth aspect, the present invention provides a complete non-volatile Boolean logic parallel operation circuit, comprising a plurality of complete non-volatile Boolean logic operation circuits provided in the first aspect of the present invention;
各完备非易失布尔逻辑运算电路的忆阻器M
1的正极均连接在同一条位线BL
0上，忆阻器M
2的正极均连接在同一条位线BL
1上，用于在同一个逻辑计算脉冲周期内，并行处理多个逻辑运算。
The positive electrodes of the memristors M1 of each complete nonvolatile Boolean logic operation circuit are connected to the same bit line BL0 , and the positive electrodes of the memristors M2 are connected to the same bit line BL1 , for processing multiple logic operations in parallel within the same logic calculation pulse cycle.
具体地，如图4所示为基于图1所示的完备非易失布尔逻辑运算电路的完备非易失布尔逻辑并行运算电路示意图，图中显示了4条WL与2根BL交叉结构。Specifically, FIG4 is a schematic diagram of a complete non-volatile Boolean logic parallel operation circuit based on the complete non-volatile Boolean logic operation circuit shown in FIG1 , and the figure shows a cross structure of 4 WLs and 2 BLs.
为了进一步说明本发明所提供的完备非易失布尔逻辑并行运算电路，在一种可选实施例下，选用与CMOS工艺兼容的氧化铪忆阻器的Vset进行均值统计，得到V
set的均值E
set为0.6V，均方差RMS
set为0.05V，所以V＝0.75V，
操作脉冲脉宽设为100ns，选用的晶体管为0.18μm工艺库中的mn33NMOS，其工作在线性区的电压V
on取值为3.3V。如图5所示提供了四位输入按位异或逻辑计算的仿真结果以及WL和SL端根据输入所配置的电压关系：P＝0011，Q＝0101，P⊕Q逻辑计算结果应为0110，可选阵列第一行代表最低位，第四行代表最高位，仿真计算每一行第二个忆阻器上两端压降是否按照预期，比如计算结果为1，意味着第二个忆阻器两端压降需要大于V
set，阻态发生翻转；计算结果为0，意味着第二个忆阻器两端压降需要小于V
set，在1T1R阵列里可以利用WL关断，将此行隔离，第二个忆阻器两端压降近似为0，仿真结果符合预期。
To further illustrate the complete non-volatile Boolean logic parallel operation circuit provided by the present invention, in an optional embodiment, the Vset of the hafnium oxide memristor compatible with the CMOS process is selected for mean statistics, and the mean value Eset of Vset is 0.6V, and the mean square error RMSset is 0.05V, so V=0.75V, The pulse width of the operation pulse is set to 100ns, and the selected transistor is the mn33NMOS in the 0.18μm process library. The voltage V on of the linear region is 3.3V. As shown in Figure 5, the simulation results of the bitwise XOR logic calculation of the four-bit input and the voltage relationship between the WL and SL terminals according to the input configuration are provided: P = 0011, Q = 0101, the P⊕Q logic calculation result should be 0110, the first row of the optional array represents the lowest bit, and the fourth row represents the highest bit. The simulation calculates whether the voltage drop across the second memristor in each row is as expected. For example, if the calculation result is 1, it means that the voltage drop across the second memristor needs to be greater than V set , and the resistance state is flipped; if the calculation result is 0, it means that the voltage drop across the second memristor needs to be less than V set . In the 1T1R array, WL can be turned off to isolate this row, and the voltage drop across the second memristor is approximately 0. The simulation results are in line with expectations.
进一步地，如图6所示为每一行作为保存输出结果的忆阻器M
2在逻辑计算(施加脉冲)过程中电阻状态的变化结果；图7所示为每一行输出忆阻器M
2在逻辑计算(施加脉冲)过程中两端电压降的变化结果。图8所示为以高低电平形式输出的数字域计算结果。
Further, FIG6 shows the change result of the resistance state of each row of memristors M2 used to store output results during the logic calculation (pulse application); FIG7 shows the change result of the voltage drop across each row of output memristors M2 during the logic calculation (pulse application). FIG8 shows the digital domain calculation results output in the form of high and low levels.
当输入P＝0，Q＝0时，M
1设置为高阻态，BL0端操作脉冲幅值接-V
0，BL1端操作脉冲幅值接V
1，WL端接0V，SL端操作脉冲幅值接0V，此时M
2两端电压V
M2约为0，M
2保持高阻态不变，输出逻辑值0，比较器输出低电平；
When input P＝0, Q＝0, M1 is set to high impedance state, the operation pulse amplitude of BL0 terminal is connected to -V0 , the operation pulse amplitude of BL1 terminal is connected to V1 , the WL terminal is connected to 0V, and the operation pulse amplitude of SL terminal is connected to 0V. At this time, the voltage V M2 across M2 is approximately 0, M2 remains in high impedance state, outputs logic value 0, and the comparator outputs low level;
当输入P＝0，Q＝1时，M
1设置为低阻态，BL0端操作脉冲幅值接-V
0，BL1端操 作脉冲幅值接V
1，WL端接入晶体管工作在线性区的电压3.3V，SL端操作脉冲幅值接0，此时M
2两端电压V
M2大于V
set，M
2转变为低阻态，输出逻辑值1，比较器输出高电平；
When input P＝0, Q＝1, M1 is set to low impedance state, the operation pulse amplitude of BL0 terminal is connected to -V0 , the operation pulse amplitude of BL1 terminal is connected to V1 , the voltage 3.3V of the transistor working in the linear region is connected to WL terminal, and the operation pulse amplitude of SL terminal is connected to 0. At this time, the voltage V M2 across M2 is greater than V set , M2 changes to low impedance state, outputs logic value 1, and the comparator outputs high level;
当输入P＝1，Q＝0时，M
1设置为高阻态，BL0端操作脉冲幅值接-V
0，BL1端操作脉冲幅值接V
1，WL端接入晶体管工作在线性区的电压3.3V，SL端操作脉冲幅值接-2V
2此时M
2两端电压V
M2大于V
set，M
2转变为低阻态，输出逻辑值1，比较器输出高电平；
When input P=1, Q=0, M1 is set to high impedance state, the operating pulse amplitude of BL0 terminal is connected to -V0 , the operating pulse amplitude of BL1 terminal is connected to V1 , the voltage 3.3V of the transistor working in the linear region is connected to WL terminal, and the operating pulse amplitude of SL terminal is connected to -2V2. At this time, the voltage V M2 across M2 is greater than V set , M2 changes to low impedance state, outputs logic value 1, and the comparator outputs high level;
当输入P＝1，Q＝1时，M
1设置为低阻态，BL0端操作脉冲幅值接-V
0，BL1端操作脉冲幅值接V
1，WL端接0V，SL端操作脉冲幅值接0，M
2两端电压V
M2小于V
set，M
2保持高阻态不变，输出逻辑值0，比较器输出低电平。
When input P=1, Q=1, M1 is set to low impedance state, the operating pulse amplitude of BL0 terminal is connected to -V0 , the operating pulse amplitude of BL1 terminal is connected to V1 , the WL terminal is connected to 0V, the operating pulse amplitude of SL terminal is connected to 0, the voltage V M2 across M2 is less than Vset , M2 remains in high impedance state, outputs logic value 0, and the comparator outputs low level.
类似地，其它基本的布尔逻辑功能也可以按照上述方法来实现。Similarly, other basic Boolean logic functions can also be implemented using the above method.
综上所述，本发明公开了一种基于1T1R阵列的完备非易失布尔逻辑电路，该逻辑电路由两个忆阻器、两个增强型NMOS晶体管、一个定值电阻、传输门开关和比较器组成，在逻辑算法上充分利用了1T1R结构中晶体管的开关特性，通过动态的对该电路的字线和源线上的控制引脚进行配置，将逻辑迭代步骤控制到两步，在逻辑操作时选择开启传输门开关可以实现采样定值电阻上的电流，与固定参考电压值进行比较而得到数字域的输出结果，基于16种激励配置方案和有限的电源幅值种类来实现可重构的16种布尔逻辑功能；其中，忆阻器的正极与位线(BL
0、BL
1)相连，忆阻器的负极与晶体管的漏端相连，晶体管的连接采用共栅极和共源线的方式，同一行晶体管的源端接到一起并通过定值电阻接到SL引脚(源控制端)，定值电阻与源线相连的节点可选择的接入比较器。忆阻器M
1的输入阻态根据逻辑输入Q来决定，忆阻器M
2的阻态作为计算结果的输出。逻辑计算过程中，BL端加载的电压脉冲幅值固定，忆阻器阈值电压变化波动范围的上限V＝E
set+3RMS
set；其中，E
set为V
set的均值；RMS
set为V
set的均方差。输入忆阻器M
1上电极上的输入电压为-V
0(V
0为与忆阻器V
set的电压范围成比例关系，同时要满足V
0+V
1≥V)，输出忆阻器M
2上电极上的输入电压为V
1(V
1的取值范围与忆阻器V
set电压范围成比例关系，同时要满足V
0+V
1≥V)，WL端的电压根据逻辑类型和输入Q、P在两种电压{V
on，0V}间进 行选择；SL端的电压根据逻辑类型、WL的电压值和输入P在2种电压{0V，-2V
2}间进行选择(V
2＝V-V
1，其取值范围同样与忆阻器V
set的电压范围成比例关系)；当需要得到实时输出结果时，不需要增加传统方案的读步骤，通过开启传输门开关，在逻辑计算完成后同步得到数字式的计算结果，有利于实现数模混合系统的搭建。与现有的逻辑计算方案相比，本方案采用的操作步数少，采用1T1R阵列可以完全避开大规模并行处理时的漏电流导致的误操作或者操作不成功问题，因为BL端激励固定，可以实现在一个时钟周期内可以同时实现多个逻辑运算，大幅度提高了计算并行度和效率，增加了利用非易失器件做计算的优势。本方案具备逻辑完备性。本方案采用的逻辑实现方法为非破坏式，有利于保护输入信息的完整性。本方案逻辑联级简单易行，有助于实现更加复杂的逻辑功能应用。
In summary, the present invention discloses a complete non-volatile Boolean logic circuit based on a 1T1R array. The logic circuit is composed of two memristors, two enhanced NMOS transistors, a fixed resistor, a transmission gate switch and a comparator. The switching characteristics of the transistors in the 1T1R structure are fully utilized in the logic algorithm. The control pins on the word line and the source line of the circuit are dynamically configured to control the logic iteration step to two steps. When the transmission gate switch is turned on during the logic operation, the current on the fixed resistor can be sampled, and the current can be compared with the fixed reference voltage value to obtain the output result in the digital domain. Based on 16 excitation configuration schemes and limited power supply amplitude types, 16 reconfigurable Boolean logic functions can be realized; wherein, the positive electrode of the memristor is connected to the bit line (BL 0 , BL 1 ), the negative electrode of the memristor is connected to the drain end of the transistor, the connection of the transistor adopts the common gate and common source line mode, the source ends of the transistors in the same row are connected together and connected to the SL pin (source control end) through the fixed resistor, and the node where the fixed resistor is connected to the source line can be selectively connected to the comparator. The input resistance state of memristor M1 is determined by the logic input Q, and the resistance state of memristor M2 is used as the output of the calculation result. During the logic calculation process, the voltage pulse amplitude loaded on the BL terminal is fixed, and the upper limit of the fluctuation range of the memristor threshold voltage is V=E set +3RMS set ; where E set is the mean value of V set ; RMS set is the mean square error of V set . The input voltage on the upper electrode of the input memristor M1 is -V0 ( V0 is proportional to the voltage range of the memristor Vset , and V0 + V1≥V is satisfied), the input voltage on the upper electrode of the output memristor M2 is V1 (the value range of V1 is proportional to the voltage range of the memristor Vset , and V0 + V1≥V is satisfied), the voltage at the WL terminal is selected between two voltages { Von , 0V} according to the logic type and inputs Q and P; the voltage at the SL terminal is selected between two voltages {0V, -2V2 } according to the logic type, the voltage value of WL and the input P ( V2 ＝ VV1 , and its value range is also proportional to the voltage range of the memristor Vset ); when real-time output results are required, there is no need to add the reading step of the traditional solution. By turning on the transmission gate switch, the digital calculation results are obtained synchronously after the logic calculation is completed, which is conducive to the construction of a digital-analog hybrid system. Compared with the existing logic calculation scheme, this scheme adopts fewer operation steps. The use of 1T1R array can completely avoid the problem of misoperation or unsuccessful operation caused by leakage current during large-scale parallel processing. Because the BL end excitation is fixed, multiple logic operations can be realized simultaneously in one clock cycle, which greatly improves the parallelism and efficiency of calculation and increases the advantage of using non-volatile devices for calculation. This scheme has logical completeness. The logic implementation method adopted by this scheme is non-destructive, which is conducive to protecting the integrity of input information. The logic cascading of this scheme is simple and easy, which helps to realize more complex logic function applications.
本领域的技术人员容易理解，以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.
Claims (10)
- 一种基于1T1R阵列的完备非易失布尔逻辑运算电路，用于对输入的逻辑值P和/或输入的逻辑值Q进行逻辑运算，其特征在于，包括：控制单元、忆阻器M 1、忆阻器M 2、第一晶体管、第二晶体管和电阻； A complete non-volatile Boolean logic operation circuit based on a 1T1R array, used for performing a logic operation on an input logic value P and/or an input logic value Q, characterized by comprising: a control unit, a memristor M 1 , a memristor M 2 , a first transistor, a second transistor and a resistor;所述忆阻器M 1的正极与位线BL 0相连，负极与所述第一晶体管的漏极端相连；所述忆阻器M 2的正极与位线BL 1相连，负极与所述第二晶体管的漏极端相连；所述第一晶体管和所述第二晶体管的栅极连接在同一条字线WL上，源极连接在同一条源线SL上；所述第一晶体管和所述第二晶体管的源极通过所述源线SL引出后与所述电阻的第一端相连，所述电阻的第二端作为源控制端；所述第一晶体管和所述第一晶体管相同；所述忆阻器M 1和所述忆阻器M 2相同，且初始状态均为高阻态； The positive electrode of the memristor M1 is connected to the bit line BL0 , and the negative electrode is connected to the drain terminal of the first transistor; the positive electrode of the memristor M2 is connected to the bit line BL1 , and the negative electrode is connected to the drain terminal of the second transistor; the gates of the first transistor and the second transistor are connected to the same word line WL, and the sources are connected to the same source line SL; the sources of the first transistor and the second transistor are connected to the first end of the resistor after being led out through the source line SL, and the second end of the resistor serves as a source control terminal; the first transistor is the same as the first transistor; the memristor M1 is the same as the memristor M2 , and both are in a high impedance state in an initial state;所述控制单元用于在进行逻辑运算时，通过所述位线BL 0对所述忆阻器M 1施加电压-V 0，通过所述位线BL 1对所述忆阻器M 2施加电压V 1，在所述字线WL上施加电压C，在所述源控制端上施加电压D，并读取所述忆阻器M 2的阻态，即为逻辑运算结果； The control unit is used to apply a voltage -V 0 to the memristor M 1 through the bit line BL 0 , apply a voltage V 1 to the memristor M 2 through the bit line BL 1 , apply a voltage C to the word line WL, apply a voltage D to the source control terminal, and read the resistance state of the memristor M 2 , which is the result of the logic operation, when performing a logic operation;其中，当所述逻辑运算电路执行与所述逻辑值Q有关的操作时，所述控制单元还用于在进行逻辑运算之前，将所述忆阻器M 1置为所述逻辑值Q所对应的阻态；与所述逻辑值Q有关的操作包括对所述逻辑值P和所述逻辑值Q进行逻辑运算的操作和仅对所述逻辑值Q进行逻辑运算的操作； Wherein, when the logic operation circuit performs an operation related to the logic value Q, the control unit is further used to set the memristor M1 to a resistance state corresponding to the logic value Q before performing the logic operation; the operation related to the logic value Q includes an operation of performing a logic operation on the logic value P and the logic value Q and an operation of performing a logic operation only on the logic value Q;V 0和V 1同时满足：V set/2≤V 0<V set，V set/2≤V 1<V set，且V 0+V 1≥V；V set为所述忆阻器M 1或所述忆阻器M 2由高阻态转变为低阻态的阈值；V为所述忆阻器M 1或所述忆阻器M 2阈值电压变化波动范围的上限； V 0 and V 1 simultaneously satisfy: V set /2≤V 0 <V set , V set /2≤V 1 <V set , and V 0 +V 1 ≥V; V set is the threshold at which the memristor M 1 or the memristor M 2 changes from a high resistance state to a low resistance state; V is the upper limit of the threshold voltage fluctuation range of the memristor M 1 or the memristor M 2 ;所述电压C的取值由所述逻辑运算的类型和逻辑值Q、P决定，所述电压D的取值由所述逻辑运算的类型、所述逻辑值P以及所述电压C决定。The value of the voltage C is determined by the type of the logic operation and the logic values Q and P, and the value of the voltage D is determined by the type of the logic operation, the logic value P and the voltage C.
- 根据权利要求1所述的完备非易失布尔逻辑运算电路，其特征在于，V 0取值为V 1取值为
The complete non-volatile Boolean logic operation circuit according to claim 1 is characterized in that V 0 is
V 1 is - 根据权利要求1所述的完备非易失布尔逻辑运算电路，其特征在于，The complete non-volatile Boolean logic operation circuit according to claim 1 is characterized in that:当所述逻辑运算的类型为真逻辑运算时，所述电压C取值为V on，所述电压D取值为0V； When the type of the logic operation is a true logic operation, the voltage C takes a value of V on , and the voltage D takes a value of 0V;当所述逻辑运算的类型为假逻辑运算时，所述电压C取值为0V，所述电压D取值为0V；When the type of the logic operation is a false logic operation, the voltage C takes a value of 0V, and the voltage D takes a value of 0V;当所述逻辑运算的类型为P逻辑运算时：若所述逻辑值P为1，则所述电压C取值为V on，此时，所述电压D取值为-2V 2；若所述逻辑值P为0，则所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logic operation is a P logic operation: if the logic value P is 1, the voltage C takes a value of V on , at which time the voltage D takes a value of -2V 2 ; if the logic value P is 0, the voltage C takes a value of 0V, at which time the voltage D takes a value of 0V;当所述逻辑运算的类型为Q逻辑运算时：若所述逻辑值Q为1，则所述电压C取值为V on；若所述逻辑值Q为0，则所述电压C取值为0V；所述电压D取值为0V； When the type of the logic operation is a Q logic operation: if the logic value Q is 1, the voltage C takes a value of V on ; if the logic value Q is 0, the voltage C takes a value of 0V; the voltage D takes a value of 0V;当所述逻辑运算的类型为非P逻辑运算时：若所述逻辑值P为1，则所述电压C取值为0V，此时，所述电压D取值为0V；若所述逻辑值P为0，则所述电压C取值为V on，此时，所述电压D取值为-2V 2； When the type of the logic operation is a non-P logic operation: if the logic value P is 1, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V; if the logic value P is 0, the voltage C takes a value of V on , and at this time, the voltage D takes a value of -2V 2 ;当所述逻辑运算的类型为非Q逻辑运算时：若所述逻辑值Q为1，则所述电压C取值为V on，此时，所述电压D取值为-2V 2；若所述逻辑值Q为0，则所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logic operation is a non-Q logic operation: if the logic value Q is 1, the voltage C takes a value of V on , at which time, the voltage D takes a value of -2V 2 ; if the logic value Q is 0, the voltage C takes a value of 0V, at which time, the voltage D takes a value of 0V;当所述逻辑运算的类型为与逻辑运算时：若选择表达式Q？P:0的逻辑运算结果为1，则所述电压C取值为V on；若所述选择表达式Q？P:0的逻辑运算结果为0，则所述电压C取值为0V；所述电压D取值为0V； When the type of the logic operation is an AND logic operation: if the logic operation result of the selection expression Q? P:0 is 1, the voltage C takes a value of V on ; if the logic operation result of the selection expression Q? P:0 is 0, the voltage C takes a value of 0V; the voltage D takes a value of 0V;当所述逻辑运算的类型为与非逻辑运算时：若选择表达式的逻辑运算结果为1，则所述电压C取值为V on，此时，所述电压D取值为-2V 2；若所述选择表达式
的逻辑运算结果为0，则所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logical operation is the AND-NOT logical operation: If you select the expression
The logical operation result is 1, then the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the selection expressionThe logical operation result is 0, then the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;当所述逻辑运算的类型为或逻辑运算时：在选择表达式Q？1:P的逻辑运算结果为1的情况下，所述电压C取值为V on，此时，若所述逻辑值P取值为1，则所述电压D取值为-2V 2；若所述逻辑值P取值为0，则所述电压D取值为0V；在所述选择表达式Q？1:P的逻辑运算结果为0的情况下，所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logic operation is an OR logic operation: when the logic operation result of the selection expression Q? 1:P is 1, the voltage C takes a value of V on , at this time, if the logic value P takes a value of 1, the voltage D takes a value of -2V 2 ; if the logic value P takes a value of 0, the voltage D takes a value of 0V; when the logic operation result of the selection expression Q? 1:P is 0, the voltage C takes a value of 0V, at this time, the voltage D takes a value of 0V;当所述逻辑运算的类型为或非逻辑运算时：若选择表达式的逻辑运算结果为1，则所述电压C取值为V on，此时，所述电压D取值为-2V 2；若所述选择表达式
的逻辑运算结果为0，则所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logical operation is an OR or NOT logical operation: If you select the expression
The logical operation result is 1, then the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the selection expressionThe logical operation result is 0, then the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;当所述逻辑运算的类型为实质蕴涵逻辑运算时：在选择表达式的逻辑运算结果为1的情况下，所述电压C取值为V on，此时，若所述逻辑值P取值为1，则所述电压D取值为0V；若所述逻辑值P取值为0，则所述电压D取值为-2V 2；在所述选择表达式
的逻辑运算结果为0的情况下，所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logical operation is a substantial implication logical operation: in the selection expression
When the logical operation result is 1, the voltage C takes the value of V on . At this time, if the logical value P takes the value of 1, the voltage D takes the value of 0V; if the logical value P takes the value of 0, the voltage D takes the value of -2V 2 .When the result of the logic operation is 0, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;当所述逻辑运算的类型为负实质蕴涵逻辑运算时：若选择表达式Q？0:P的逻辑运算结果为1，则所述电压C取值为V on，此时，所述电压D取值为-2V 2；若所述选择表达式Q？0:P的逻辑运算结果为0，则所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logic operation is a negative substantial implication logic operation: if the logic operation result of the selection expression Q? 0:P is 1, the voltage C takes a value of V on , at which time, the voltage D takes a value of -2V 2 ; if the logic operation result of the selection expression Q? 0:P is 0, the voltage C takes a value of 0V, at which time, the voltage D takes a value of 0V;当所述逻辑运算的类型为反实质蕴涵逻辑运算时：若选择表达式Q？P:1的逻辑运算结果为1，则所述电压C取值为V on，此时，所述电压D取值为-2V 2；若所述选择表达式Q？P:1的逻辑运算结果为0，则所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logic operation is an inverse substantive implication logic operation: if the logic operation result of the selection expression Q? P:1 is 1, the voltage C takes a value of V on , and at this time, the voltage D takes a value of -2V 2 ; if the logic operation result of the selection expression Q? P:1 is 0, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;当所述逻辑运算的类型为反负实质蕴涵逻辑运算时：若选择表达式的逻辑运算结果为1，则所述电压C取值为V on；若所述选择表达式
的逻辑运算结果为0，则所述电压C取值为0V；所述电压D取值为0V； When the type of the logical operation is a negative substantive implied logical operation: If the expression is selected
The logical operation result is 1, then the voltage C takes the value V on ; if the selection expressionThe logical operation result is 0, then the voltage C takes a value of 0V; the voltage D takes a value of 0V;当所述逻辑运算的类型为异或逻辑运算时：在选择表达式的逻辑运算结果为1的情况下，所述电压C取值为V on，此时，若所述逻辑值P取值为1，则所述电压D取值为-2V 2；若所述逻辑值P取值为0，则所述电压D取值为0V；在所述选择表达式
的逻辑运算结果为0的情况下，所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logical operation is an exclusive OR logical operation: When selecting an expression
When the logical operation result is 1, the voltage C takes the value of V on . At this time, if the logical value P takes the value of 1, the voltage D takes the value of -2V 2 ; if the logical value P takes the value of 0, the voltage D takes the value of 0V. In the selection expressionWhen the result of the logic operation is 0, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;当所述逻辑运算的类型为同或逻辑运算时：在选择表达式的逻辑运算结果为1的情况下，所述电压C取值为V on，此时，若所述逻辑值P取值为1，则所述电压D取值为0V；若所述逻辑值P取值为0，则所述电压D取值为-2V 2；在所述选择 表达式
的逻辑运算结果为0的情况下，所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logical operation is an exclusive OR logical operation: When selecting an expression
When the logical operation result is 1, the voltage C takes the value of V on . At this time, if the logical value P takes the value of 1, the voltage D takes the value of 0V; if the logical value P takes the value of 0, the voltage D takes the value of -2V 2 .When the result of the logic operation is 0, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;其中，V on为所述第一晶体管或所述第二晶体管工作在线性区的电压；所述第一晶体管和所述第二晶体管均为NMOS晶体管；V 2＝V-V 1。 Wherein, V on is the voltage when the first transistor or the second transistor operates in the linear region; the first transistor and the second transistor are both NMOS transistors; and V 2 =VV 1 . - 根据权利要求1所述的完备非易失布尔逻辑运算电路，其特征在于，V 2取值为The complete non-volatile Boolean logic operation circuit according to claim 1 is characterized in that V2 is
- 根据权利要求1所述的完备非易失布尔逻辑运算电路，其特征在于，所述电阻的阻值大小介于所述忆阻器M 1或所述忆阻器M 2的高阻态阻值与低阻态阻值之间；所述电阻的阻值为其中，R H为所述忆阻器M 1或所述忆阻器M 2的高阻态电阻值，R L为所述忆阻器M 1或所述忆阻器M 2的低阻态电阻值。 The complete non-volatile Boolean logic operation circuit according to claim 1 is characterized in that the resistance value of the resistor is between the high resistance value and the low resistance value of the memristor M1 or the memristor M2 ; the resistance value of the resistor is
Wherein, RH is the high-resistance resistance value of the memristor M1 or the memristor M2 , and RL is the low-resistance resistance value of the memristor M1 or the memristor M2 . - 根据权利要求1-5任意一项所述的完备非易失布尔逻辑运算电路，其特征在于，还包括：读取电路；其中，所述读取电路包括：与所述电阻的第一端相连的传输门电路，以及与所述传输门电路的输出端相连的比较器，用于读取所述忆阻器M 2的阻态。 The complete non-volatile Boolean logic operation circuit according to any one of claims 1 to 5 is characterized in that it also includes: a reading circuit; wherein the reading circuit includes: a transmission gate circuit connected to the first end of the resistor, and a comparator connected to the output end of the transmission gate circuit, for reading the resistance state of the memristor M2 .
- 一种完备非易失布尔逻辑电路的控制方法，用于对输入的逻辑值P和/或输入的逻辑值Q进行逻辑运算，其特征在于，应用于权利要求1-6任意一项所述的完备非易失布尔逻辑电路中的控制单元，包括以下步骤：A control method for a complete non-volatile Boolean logic circuit, for performing a logic operation on an input logic value P and/or an input logic value Q, characterized in that the control unit applied to the complete non-volatile Boolean logic circuit according to any one of claims 1 to 6 comprises the following steps:S1、将所述忆阻器M 1和所述忆阻器M 2均初始化为高阻态； S1, initializing the memristor M1 and the memristor M2 to a high impedance state;S2、判断当前操作是否为与所述逻辑值Q有关的操作，若是，则将所述忆阻器M 1置为所述逻辑值Q所对应的阻态；其中，与所述逻辑值Q有关的操作包括对所述逻辑值P和所述逻辑值Q进行逻辑运算的操作和仅对所述逻辑值Q进行逻辑运算的操作； S2, determining whether the current operation is an operation related to the logic value Q, and if so, setting the memristor M1 to a resistance state corresponding to the logic value Q; wherein the operation related to the logic value Q includes an operation of performing a logic operation on the logic value P and the logic value Q and an operation of performing a logic operation only on the logic value Q;S3、通过所述位线BL 0对所述忆阻器M 1施加电压-V 0，通过所述位线BL 1对所述忆阻器M 2施加电压V 1，在所述字线WL上施加所述电压C，在所述源控制端上施加所述电压D，并读取所述忆阻器M 2的阻态，即为逻辑运算结果； S3, applying a voltage -V 0 to the memristor M 1 through the bit line BL 0 , applying a voltage V 1 to the memristor M 2 through the bit line BL 1 , applying the voltage C to the word line WL, applying the voltage D to the source control terminal, and reading the resistance state of the memristor M 2 , which is the result of the logic operation;其中，V 0和V 1同时满足：V set/2≤V 0<V set，V set/2≤V 1<V set，且V 0+V 1≥V；V set为所述忆阻器M 1或所述忆阻器M 2由高阻态转变为低阻态的阈值；V＝E set+ 3RMS set为所述忆阻器M 1或所述忆阻器M 2阈值电压变化波动范围的上限；E set为V set的均值；RMS set为V set的均方差； Wherein, V 0 and V 1 simultaneously satisfy: V set /2≤V 0 <V set , V set /2≤V 1 <V set , and V 0 +V 1 ≥V; V set is the threshold at which the memristor M 1 or the memristor M 2 changes from a high resistance state to a low resistance state; V＝E set + 3RMS set is the upper limit of the threshold voltage fluctuation range of the memristor M 1 or the memristor M 2 ; E set is the mean value of V set ; RMS set is the mean square error of V set ;所述电压C的取值由所述逻辑运算的类型和逻辑值Q、P决定，所述电压D的取值由所述逻辑运算的类型、所述逻辑值P以及所述电压C决定。The value of the voltage C is determined by the type of the logic operation and the logic values Q and P, and the value of the voltage D is determined by the type of the logic operation, the logic value P and the voltage C.
- 根据权利要求7所述的完备非易失布尔逻辑电路的控制方法，其特征在于，The control method of the complete non-volatile Boolean logic circuit according to claim 7 is characterized in that:当所述逻辑运算的类型为真逻辑运算时，所述电压C取值为V on，所述电压D取值为0V； When the type of the logic operation is a true logic operation, the voltage C takes a value of V on , and the voltage D takes a value of 0V;当所述逻辑运算的类型为假逻辑运算时，所述电压C取值为0V，所述电压D取值为0V；When the type of the logic operation is a false logic operation, the voltage C takes a value of 0V, and the voltage D takes a value of 0V;当所述逻辑运算的类型为P逻辑运算时：若所述逻辑值P为1，则所述电压C取值为V on，此时，所述电压D取值为-2V 2；若所述逻辑值P为0，则所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logic operation is a P logic operation: if the logic value P is 1, the voltage C takes a value of V on , at which time the voltage D takes a value of -2V 2 ; if the logic value P is 0, the voltage C takes a value of 0V, at which time the voltage D takes a value of 0V;当所述逻辑运算的类型为Q逻辑运算时：若所述逻辑值Q为1，则所述电压C取值为V on；若所述逻辑值Q为0，则所述电压C取值为0V；所述电压D取值为0V； When the type of the logic operation is a Q logic operation: if the logic value Q is 1, the voltage C takes a value of V on ; if the logic value Q is 0, the voltage C takes a value of 0V; the voltage D takes a value of 0V;当所述逻辑运算的类型为非P逻辑运算时：若所述逻辑值P为1，则所述电压C取值为0V，此时，所述电压D取值为0V；若所述逻辑值P为0，则所述电压C取值为V on，此时，所述电压D取值为-2V 2； When the type of the logic operation is a non-P logic operation: if the logic value P is 1, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V; if the logic value P is 0, the voltage C takes a value of V on , and at this time, the voltage D takes a value of -2V 2 ;当所述逻辑运算的类型为非Q逻辑运算时：若所述逻辑值Q为1，则所述电压C取值为V on，此时，所述电压D取值为-2V 2；若所述逻辑值Q为0，则所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logic operation is a non-Q logic operation: if the logic value Q is 1, the voltage C takes a value of V on , at which time, the voltage D takes a value of -2V 2 ; if the logic value Q is 0, the voltage C takes a value of 0V, at which time, the voltage D takes a value of 0V;当所述逻辑运算的类型为与逻辑运算时：若选择表达式Q？P:0的逻辑运算结果为1，则所述电压C取值为V on；若所述选择表达式Q？P:0的逻辑运算结果为0，则所述电压C取值为0V；所述电压D取值为0V； When the type of the logic operation is an AND logic operation: if the logic operation result of the selection expression Q? P:0 is 1, the voltage C takes a value of V on ; if the logic operation result of the selection expression Q? P:0 is 0, the voltage C takes a value of 0V; the voltage D takes a value of 0V;当所述逻辑运算的类型为与非逻辑运算时：若选择表达式的逻辑运算结果为1，则所述电压C取值为V on，此时，所述电压D取值为-2V 2；若所述选择表达式
的逻辑运算结果为0，则所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logical operation is the AND-NOT logical operation: If you select the expression
The logical operation result is 1, then the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the selection expressionThe logical operation result is 0, then the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;当所述逻辑运算的类型为或逻辑运算时：在选择表达式Q？1:P的逻辑运算结果为1的情况下，所述电压C取值为V on，此时，若所述逻辑值P取值为1，则所述电压D取值为-2V 2；若所述逻辑值P取值为0，则所述电压D取值为0V；在所述选择表达式Q？1:P的逻辑运算结果为0的情况下，所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logic operation is an OR logic operation: when the logic operation result of the selection expression Q? 1:P is 1, the voltage C takes a value of V on , at this time, if the logic value P takes a value of 1, the voltage D takes a value of -2V 2 ; if the logic value P takes a value of 0, the voltage D takes a value of 0V; when the logic operation result of the selection expression Q? 1:P is 0, the voltage C takes a value of 0V, at this time, the voltage D takes a value of 0V;当所述逻辑运算的类型为或非逻辑运算时：若选择表达式的逻辑运算结果为1，则所述电压C取值为V on，此时，所述电压D取值为-2V 2；若所述选择表达式
的逻辑运算结果为0，则所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logical operation is an OR or NOT logical operation: If you select the expression
The logical operation result is 1, then the voltage C takes the value of V on , at this time, the voltage D takes the value of -2V 2 ; if the selection expressionThe logical operation result is 0, then the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;当所述逻辑运算的类型为实质蕴涵逻辑运算时：在选择表达式的逻辑运算结果为1的情况下，所述电压C取值为V on，此时，若所述逻辑值P取值为1，则所述电压D取值为0V；若所述逻辑值P取值为0，则所述电压D取值为-2V 2；在所述选择表达式
的逻辑运算结果为0的情况下，所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logical operation is a substantial implication logical operation: in the selection expression
When the logical operation result is 1, the voltage C takes the value of V on . At this time, if the logical value P takes the value of 1, the voltage D takes the value of 0V; if the logical value P takes the value of 0, the voltage D takes the value of -2V 2 .When the result of the logic operation is 0, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;当所述逻辑运算的类型为负实质蕴涵逻辑运算时：若选择表达式Q？0:P的逻辑运算结果为1，则所述电压C取值为V on，此时，所述电压D取值为-2V 2；若所述选择表达式Q？0:P的逻辑运算结果为0，则所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logic operation is a negative substantial implication logic operation: if the logic operation result of the selection expression Q? 0:P is 1, the voltage C takes a value of V on , at which time, the voltage D takes a value of -2V 2 ; if the logic operation result of the selection expression Q? 0:P is 0, the voltage C takes a value of 0V, at which time, the voltage D takes a value of 0V;当所述逻辑运算的类型为反实质蕴涵逻辑运算时：若选择表达式Q？P:1的逻辑运算结果为1，则所述电压C取值为V on，此时，所述电压D取值为-2V 2；若所述选择表达式Q？P:1的逻辑运算结果为0，则所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logic operation is an inverse substantive implication logic operation: if the logic operation result of the selection expression Q? P:1 is 1, the voltage C takes a value of V on , and at this time, the voltage D takes a value of -2V 2 ; if the logic operation result of the selection expression Q? P:1 is 0, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;当所述逻辑运算的类型为反负实质蕴涵逻辑运算时：若选择表达式的逻辑运算结果为1，则所述电压C取值为V on；若所述选择表达式
的逻辑运算结果为0，则所述电压C取值为0V；所述电压D取值为0V； When the type of the logical operation is a negative substantive implied logical operation: If the expression is selected
The logical operation result is 1, then the voltage C takes the value V on ; if the selection expressionThe logical operation result is 0, then the voltage C takes a value of 0V; the voltage D takes a value of 0V;当所述逻辑运算的类型为异或逻辑运算时：在选择表达式的逻辑运算结果为1的情况下，所述电压C取值为V on，此时，若所述逻辑值P取值为1，则所述电压D取值为-2V 2；若所述逻辑值P取值为0，则所述电压D取值为0V；在所述选择 表达式
的逻辑运算结果为0的情况下，所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logical operation is an exclusive OR logical operation: When selecting an expression
When the logical operation result is 1, the voltage C takes the value of V on . At this time, if the logical value P takes the value of 1, the voltage D takes the value of -2V 2 ; if the logical value P takes the value of 0, the voltage D takes the value of 0V. In the selection expressionWhen the result of the logic operation is 0, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;当所述逻辑运算的类型为同或逻辑运算时：在选择表达式的逻辑运算结果为1的情况下，所述电压C取值为V on，此时，若所述逻辑值P取值为1，则所述电压D取值为0V；若所述逻辑值P取值为0，则所述电压D取值为-2V 2；在所述选择表达式
的逻辑运算结果为0的情况下，所述电压C取值为0V，此时，所述电压D取值为0V； When the type of the logical operation is an exclusive OR logical operation: When selecting an expression
When the logical operation result is 1, the voltage C takes the value of V on . At this time, if the logical value P takes the value of 1, the voltage D takes the value of 0V; if the logical value P takes the value of 0, the voltage D takes the value of -2V 2 .When the result of the logic operation is 0, the voltage C takes a value of 0V, and at this time, the voltage D takes a value of 0V;其中，V on为所述第一晶体管或所述第二晶体管工作在线性区的电压；所述第一晶体管和所述第二晶体管均为NMOS晶体管；V 2＝V-V 1。 Wherein, V on is the voltage when the first transistor or the second transistor operates in the linear region; the first transistor and the second transistor are both NMOS transistors; and V 2 =VV 1 . - 一种基于上述完备非易失布尔逻辑电路的逐位逻辑级联方法，其特征在于，包括：A bit-by-bit logic cascading method based on the above-mentioned complete non-volatile Boolean logic circuit, characterized by comprising:将按照权利要求7或8所述的控制方法操作所得的前一步逻辑运算结果作为新的输入逻辑值Q，重新按照权利要求7或8的控制方法进行操作，从而实现逐位逻辑级联。The previous logic operation result obtained by operating according to the control method described in claim 7 or 8 is used as a new input logic value Q, and the control method described in claim 7 or 8 is again operated to achieve bit-by-bit logic cascading.
- 一种完备非易失布尔逻辑并行运算电路，其特征在于，包括多个权利要求1-6任意一项所述的完备非易失布尔逻辑运算电路；A complete non-volatile Boolean logic parallel operation circuit, characterized in that it comprises a plurality of complete non-volatile Boolean logic operation circuits according to any one of claims 1 to 6;各所述完备非易失布尔逻辑运算电路的忆阻器M 1的正极均连接在同一条位线BL 0上，忆阻器M 2的正极均连接在同一条位线BL 1上，用于在同一个逻辑计算脉冲周期内，并行实现多个逻辑运算。 The positive electrodes of the memristors M1 of the complete non-volatile Boolean logic operation circuits are connected to the same bit line BL0 , and the positive electrodes of the memristors M2 are connected to the same bit line BL1 , so as to realize multiple logic operations in parallel within the same logic calculation pulse cycle.
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| US20150149517A1 (en) * | 2013-11-25 | 2015-05-28 | University Of The West Of England | Logic device and method of performing a logical operation |
| CN109388853A (en) * | 2018-09-07 | 2019-02-26 | 北京大学 | A kind of bipolar mixed high-efficient memristor logic circuit of list and its control method |
| CN109994139A (en) * | 2019-03-15 | 2019-07-09 | 北京大学 | A kind of complete non-volatile logic implementation method and its application based on unipolarity memristor |
| CN113362872A (en) * | 2021-06-16 | 2021-09-07 | 华中科技大学 | Memristor-based complete nonvolatile Boolean logic circuit and operation method |
| CN113872586A (en) * | 2020-06-30 | 2021-12-31 | 华为技术有限公司 | Logic gate device, operation method thereof, search task execution chip and search task execution method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20150149517A1 (en) * | 2013-11-25 | 2015-05-28 | University Of The West Of England | Logic device and method of performing a logical operation |
| CN109388853A (en) * | 2018-09-07 | 2019-02-26 | 北京大学 | A kind of bipolar mixed high-efficient memristor logic circuit of list and its control method |
| CN109994139A (en) * | 2019-03-15 | 2019-07-09 | 北京大学 | A kind of complete non-volatile logic implementation method and its application based on unipolarity memristor |
| CN113872586A (en) * | 2020-06-30 | 2021-12-31 | 华为技术有限公司 | Logic gate device, operation method thereof, search task execution chip and search task execution method |
| CN113362872A (en) * | 2021-06-16 | 2021-09-07 | 华中科技大学 | Memristor-based complete nonvolatile Boolean logic circuit and operation method |
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