CN115993935A - Efficient monotonic counting method based on Flash storage array, counter and application - Google Patents
Efficient monotonic counting method based on Flash storage array, counter and application Download PDFInfo
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Abstract
The invention relates to the technical field of circuit design and discloses a high-efficiency monotonic counting method based on a Flash storage array, a counter and application thereof, wherein the method comprises the steps of executing an erasing operation on the storage array and sequentially executing one-bit programming operation on the storage array according to one counting time, and the counter mainly comprises a storage array module, a count value conversion circuit module and a counting self-adding preparation circuit module; the counting method is convenient and fast, the counter is simple in structure, programming time is effectively reduced, power consumption is reduced, logic delay of a circuit is optimized, important performances such as power consumption and speed are further optimized on the basis of the design of prolonging the erasing life of the flash memory unit, and the counter has high practical value and wide application prospect.
Description
Technical Field
The invention relates to the technical field of circuit design, in particular to a high-efficiency monotonic counting method based on a Flash storage array, a counter and application.
Background
The monotonic counter (Monotonic Counter) is a counter having a monotonic counting function, and after the data is counted in the monotonic counter, the monotonic counter is monotonically increased only with the change of the count value. Monotonic counters are used in various financial or electronic systems. In such applications, the monotonic counter needs to continuously update its count value over a long period of time.
In the existing integrated circuit design technology for realizing the monotonic counter, a hardware counting circuit and a flash nonvolatile memory array are used, and counting is started each time, so that the counting value output by the counting circuit is programmed into the memory array. And waiting for the next counting, reading the last counting value from the storage array, and taking the last counting value as the initial counting value of the hardware counting circuit to enable the counting circuit to start counting from the last counting value, so that the aim of monotonically increasing the counting is ensured.
However, the implementation method of the monotonic counter needs to erase the last count value data of the memory array and then program new count value data of the memory array, so that the erasable life of the flash nonvolatile memory cell array is very tested. The erasable limit of the conventional flash nonvolatile memory cell array is about 10 ten thousand times, so that when the count time is greater than or equal to 10 ten thousand times, the monotonic counter with the design can not work normally due to the failure of the flash nonvolatile memory cell.
In addition, the existing design has a complex way of counting the total value, and the number of times of erasing is recorded by using an additional memory cell, so that redundant control logic circuits are increased, and the area of a chip is increased.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a high-efficiency monotonic counting method based on a Flash storage array, a counter and application thereof, the counting mode is convenient and fast, the design logic is simple, the circuit area is reduced, the circuit logic delay is optimized, the programming time is shortened, and the circuit power consumption is reduced.
The invention solves the technical problems by adopting the following technical scheme:
the invention provides a high-efficiency monotonic counting method based on a Flash storage array, which comprises the following steps:
performing an erase operation on the memory array;
sequentially executing one-bit programming operation on the memory array according to one count, and specifically comprises the following steps:
receiving a counting enabling signal, obtaining the address of non-all-zero data in the storage array and programmed bit number information in the non-all-zero data, and processing to obtain a current recorded numerical value;
and adding one to the current recorded value, processing to generate data information of the bit to be programmed, and executing programming operation on the bit to be programmed.
Preferably, the program operation further includes a program verification operation after execution, and if verification is not passed, the program operation is continued to be executed on the bit until the program verification is passed.
Preferably, the bit to be programmed is the least significant bit of non-all zero data that is not programmed;
if the non-all zero data is not read, a full signal is fed back.
The invention also provides a high-efficiency monotonic counter based on the Flash storage array, which comprises a storage array module, an erasing circuit module, a programming circuit module, a count value conversion circuit module and a count self-adding preparation circuit module;
the count value conversion circuit module is configured to process and output a stored count value according to the address of the non-all-zero data in the storage array module and the programmed bit number information in the non-all-zero data;
the count self-adding preparation circuit module is configured to generate count self-adding programming data according to the stored count value output by the count value conversion circuit module, and send the count self-adding programming data into the programming circuit module to execute programming operation on the memory array module.
Preferably, the address of the non-all-zero data is obtained as follows:
reading data in the memory array module according to a preset reading bit number;
if the data of the target address is all zero, continuing to read according to the address sequence until the non-all-zero data is read or the target address is a tail address:
if the non-all zero data is read, returning the address where the non-all zero data is located and bit number information of zero data in the non-all zero data;
if the target address is the tail address, a full signal is fed back.
Preferably, the preset reading bit number includes one or more of 8 bits, 16 bits and 32 bits.
Preferably, the preset reading bit number is 16 bits, the count value conversion circuit module comprises a circuit for converting 16 bits of reading data into 5 bits of count value, wherein,
where cout_4 … cout_0 is a 5-bit count value, read_15.
Preferably, the count self-adding preparation circuit module includes a circuit for converting a new count value of 5 bits into a programming data value of 16 bits, and directly maps the configuration circuit according to the programming data value of 16 bits corresponding to each new count value, and specifically includes:
ncout [4:0] =5 'b0_0000 corresponds to pgm [15:0] =16' hfffff;
ncout [4:0] =5 'b0_0001 corresponds to pgm [15:0] =16' hffe;
ncout [4:0] =5 'b0_0010 corresponds to pgm [15:0] =16' hffc;
ncout [4:0] =5 'b0_0011 corresponds to pgm [15:0] =16' hfff8;
ncout [4:0] =5 'b0_0100 corresponds to pgm [15:0] =16' hfff0;
ncout [4:0] =5 'b0_0101 corresponds to pgm [15:0] =16' hfffe0;
ncout [4:0] =5 'b0_0110 corresponds to pgm [15:0] =16' hffc0;
ncout [4:0] =5 'b0_0111 corresponds to pgm [15:0] =16' hf80;
ncout [4:0] =5 'b0_1000 corresponds to pgm [15:0] =16' hf00;
ncout [4:0] =5 'b0_1001 corresponds to pgm [15:0] =16' hfe00;
ncout [4:0] =5 'b0_1010 corresponds to pgm [15:0] =16' hfc00;
ncout [4:0] =5 'b0_1011 corresponds to pgm [15:0] =16' hf800;
ncout [4:0] =5 'b0_1100 corresponds to pgm [15:0] =16' hf000;
ncout [4:0] =5 'b0_1101 corresponds to pgm [15:0] =16' he000;
ncout [4:0] =5 'b0_1110 corresponds to pgm [15:0] =16' hc000;
ncout [4:0] =5 'b0_1111 corresponds to pgm [15:0] =16' h8000;
ncout [4:0] =5 'b1_0000 corresponds to pgm [15:0] =16' h0000;
where Ncout [4:0] is a 5-bit new count value and pgm [15:0] is a 16-bit program data value.
Preferably, the count self-priming circuit module is implemented by left shift logic.
The invention also provides a chip circuit which comprises the circuit structure of the monotonic counter.
Compared with the prior art, the invention has the following beneficial effects:
firstly, the counting method provided by the invention optimizes important performances such as circuit power consumption, speed and the like on the basis of the design of prolonging the erasing life of the flash memory unit, and only 1bit0 Programming (PGM) operation is carried out by counting each time, so that the operation of programming multiple bits 0 data once is avoided, thereby reducing programming time, reducing power consumption and improving the overall performance of the circuit; secondly, the counting method of the invention has the advantages of convenient and fast way of counting the total value and simple design logic, reduces the circuit area and reduces the logic delay of the circuit so that the working speed of the whole monotonic counter is faster; finally, the invention can select the 8bit, 16bit and 32bit read-write counting storage arrays according to the requirement, and controllably reduces the low-order address switching, thereby reducing the power consumption, and having great significance for realizing the high-efficiency counting of the counter.
Other prominent substantial features and significant advances of the invention relative to the prior art are described in further detail in the examples section.
Drawings
Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
FIG. 1 is a flow chart of a monotonic counting method of embodiment 1;
FIG. 2 is a truth table of the input/output correspondence relationship of the calculation and conversion circuit module in the embodiment 2;
fig. 3 is a logic circuit configuration diagram of a calculation value conversion circuit module in embodiment 2;
FIG. 4 is a truth table of the input/output correspondence of the count self-priming circuit module in example 2;
FIG. 5 is a schematic diagram of the input/output logic analysis structure of the count self-priming circuit module in embodiment 2;
FIG. 6 is a logic circuit configuration diagram of a count self-priming circuit module in accordance with embodiment 2;
fig. 7 is a logic circuit configuration diagram of a count self-priming circuit module implemented using left shift logic in embodiment 2.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that certain names are used throughout the specification and claims to refer to particular components. It should be appreciated that one of ordinary skill in the art may refer to the same component by different names. The description and claims do not identify differences in names as a way of distinguishing components, but rather are identified as a way of distinguishing components. As used in the specification and claims of this application, the terms "comprising" or "including" are to be construed as "including but not limited to" or "including but not limited to". The embodiments described in the detailed description are preferred embodiments of the invention and are not intended to limit the scope of the invention.
Example 1
Referring to fig. 1, a first embodiment of the present invention is a high-efficiency monotonic counting method based on a Flash storage array, the method comprising:
performing an erase operation on the memory array;
sequentially executing one-bit programming operation on the memory array according to one count, and specifically comprises the following steps:
receiving a counting enabling signal, obtaining the address of non-all-zero data in the storage array and programmed bit number information (namely, the bit number stored as 0) in the non-all-zero data, and processing to obtain a current recorded numerical value;
adding one to the current recorded value, processing to generate data information of a bit to be programmed, and executing programming operation on the bit to be programmed, wherein in the embodiment, after the programming operation is executed, programming verification operation is further included, if verification is not passed, continuing to execute the programming operation on the bit until the programming verification is passed;
the bit to be programmed is typically the lowest bit of the non-all-zero data that is not programmed (i.e., stored as 1) in this embodiment;
in this embodiment, if no non-all-zero data is read, a full signal is fed back.
For further clarity, referring to the flow chart of the monotonic counting method in fig. 1, a typical Flash memory array has a plurality of memory cells representing the maximum value that can be counted by the block memory array. One skilled in the art can assign addresses based on the storage array size, assuming count 2 N Next, one address reads out 8bit data, then
And sequentially reading the data in the addresses according to a reading rule, wherein the general reading rule is that 16-bit data are read each time, and of course, 8-bit data and 32-bit data can be read each time, and if 8-bit data are read each time, address switching is more frequent and more power consumption is consumed. If 16 bits of data are read or programmed at a time, add may not be switched<0>If 32 bits are used, add may not be switched<1:0>The power consumption is reduced. And continuing to read downwards until the data which is read to be not all 0 is stopped when the value of all 0 is read, and recording the address which is read to be not all 0. If no non-all 0 data is read in the memory array, this indicates that the memory array block is full.
Here, when data other than all 0 is read, the address of the data other than all 0 and the number of 0 s in the data mean the last count size. And then the read non-all 0 data is transmitted into a count value conversion module, the number of 0 in the non-all 0 data is obtained by using a logic circuit of the module, the count total value of the last count is calculated, then the read 0 data is transmitted into a count self-adding preparation circuit module by combining a count enabling signal, the new 0 data is obtained by self-adding 1bit0 on the basis of the read data, a programming high-voltage signal is generated by a high-voltage preparation module, the high-voltage signal acts on a count storage array, programming verification is needed after programming operation is finished, the programming operation is continuously executed without verification until programming is successful, and the current counting process is completed.
Continuing to explain how to acquire the address of the non-all-zero data in the storage array and the programmed bit number information in the non-all-zero data, processing to obtain the current recorded value, when the processing reading of the last counted value is performed, and when the storage array reads the non-all-0 data, reading the address of the non-all-0 data and the number of 0 in the data means the last counted size, so that the total counted value can be directly represented by address splicing: { memory array reads to addresses other than all 0 (add is removed if 16 bits are read<0>) The memory array reads the number of 0's in the 16bit data for addresses other than all 0's. To make the explanation of the acquisition of the count total more understandable, further examples are: first assume that a block of memory array has 2 10 And 7 (10-3) bits of address are needed to access a block of memory array. Assuming that the address of the memory array reading 16bit non-all 0 data is 7'h01, the address of the memory array reading 16bit non-all 0 data is 16' h8000, because the address of the memory array reading 16bit data is independent of add<0>We use A as the value of (2)<7:1>The value of =6 ' b000000 is expressed as the address of the memory array, so the total count value (COUNTER) =10 ' h { add, f } =10 ' h00f.
Example 2
As shown in fig. 2-7, the present embodiment provides a high-efficiency monotonic counter based on a Flash storage array, which includes a storage array module, an erasing circuit module, a programming circuit module, a count value conversion circuit module and a count self-adding preparation circuit module;
the counter value conversion circuit module in the embodiment is configured to process and output a stored counter value according to the address of the non-all-zero data in the storage array module and the programmed bit number information in the non-all-zero data;
the count self-adding preparation circuit module in the embodiment is configured to generate the program data after counting self-adding according to the stored count value output by the count value conversion circuit module, and send the program data into the programming circuit module to execute the programming operation on the memory array module.
Please refer to the description in embodiment 1, the address of the non-all-zero data in this embodiment is obtained as follows:
reading data in the memory array module according to a preset reading bit number;
if the data of the target address is all zero, continuing to read according to the address sequence until the non-all-zero data is read or the target address is a tail address:
if the non-all zero data is read, returning the address where the non-all zero data is located and bit number information of zero data in the non-all zero data;
if the target address is the tail address, a full signal is fed back.
The general preset read bit number includes one or more of 8 bits, 16 bits, and 32 bits, in this embodiment, taking 16bit data read at a time as an example for illustration, and in the preset read bit number is 16 bits, the count value conversion circuit module in this embodiment includes a 16bit read data to 5 bit count value circuit, wherein,
in the above, cout_4..cout_0 is a 5-bit count value, and read_15..read_0 is 16-bit read data.
The matched self-adding preparation circuit module in the embodiment comprises a circuit for converting a 5-bit new count value into a 16-bit programming data, and a configuration circuit for directly mapping the 16-bit programming data corresponding to each new count value, and specifically comprises the following steps:
ncout [4:0] =5 'b0_0000 corresponds to pgm [15:0] =16' hfffff;
ncout [4:0] =5 'b0_0001 corresponds to pgm [15:0] =16' hffe;
ncout [4:0] =5 'b0_0010 corresponds to pgm [15:0] =16' hffc;
ncout [4:0] =5 'b0_0011 corresponds to pgm [15:0] =16' hfff8;
ncout [4:0] =5 'b0_0100 corresponds to pgm [15:0] =16' hfff0;
ncout [4:0] =5 'b0_0101 corresponds to pgm [15:0] =16' hfffe0;
ncout [4:0] =5 'b0_0110 corresponds to pgm [15:0] =16' hffc0;
ncout [4:0] =5 'b0_0111 corresponds to pgm [15:0] =16' hf80;
ncout [4:0] =5 'b0_1000 corresponds to pgm [15:0] =16' hf00;
ncout [4:0] =5 'b0_1001 corresponds to pgm [15:0] =16' hfe00;
ncout [4:0] =5 'b0_1010 corresponds to pgm [15:0] =16' hfc00;
ncout [4:0] =5 'b0_1011 corresponds to pgm [15:0] =16' hf800;
ncout [4:0] =5 'b0_1100 corresponds to pgm [15:0] =16' hf000;
ncout [4:0] =5 'b0_1101 corresponds to pgm [15:0] =16' he000;
ncout [4:0] =5 'b0_1110 corresponds to pgm [15:0] =16' hc000;
ncout [4:0] =5 'b0_1111 corresponds to pgm [15:0] =16' h8000;
ncout [4:0] =5 'b1_0000 corresponds to pgm [15:0] =16' h0000;
where Ncout [4:0] is a 5-bit new count value and pgm [15:0] is a 16-bit program data value.
Of course, the count self-priming circuit module in this embodiment may also be implemented by left shift logic.
To further clarify the function and structure of the counter in the present embodiment, the count value conversion circuit module and the count self-addition preparation circuit module are further exemplified:
since 1bit0 represents one count of the counter in the memory array, the number of all memory cells in the initial memory array that are not counted is 1. So there are only 17 data combinations as shown in fig. 2 per the situation that 16bit data can be read.
Then the value of 0 may occur 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, and mcl_cout <0> is 1, i.e. the number of 0 s is 1, 3, 5, 7, 9, 11, 13, 15 is: mcl_read <0> is 0 while mcl_read <1> is 1, mcl_read <2> is 0 while mcl_read <3> is 1, mcl_read <4> is 0 while mcl_read <5> is 1, mcl_read <6> is 0 while mcl_read <7> is 1, mcl_read <8> is 0 while mcl_read <9> is 1, mcl_read <10> is 0 while mcl_read <11> is 1, mcl_read <12> is 0 while mcl_read <13> is 1, mcl_read <14> is 0 while mcl_read <15> is 1. The numbers mcl_cout <1> is 1, that is, 0 are 2, 3, 6, 7, 10, 11, 14, 15: mcl_read <1> is 0 while mcl_read <3> is 1, mcl_read <5> is 0 while mcl_read <7> is 1, mcl_read <9> is 0 while mcl_read <11> is 1, mcl_read <13> is 0 while mcl_read <15> is 1; the numbers of mcl_cout <2> being 1, that is, 0, are 4, 5, 6, 7, 12, 13, 14, 15 are as follows: mcl_read <3> is 0 while mcl_read <7> is 1, mcl_read <11> is 0 while mcl_read <15> is 1; only when mcl_cout <2> is 1, i.e. the number of 0 s is 8, 9, 10, 11, 12, 13, 14, 15 is mcl_read <7> is 0 and mcl_read <15> is 1; the number of mcl_cout <3> is 1, that is, 0 is 16, only: mcl_read <15> is 0;
the logic reasoning of 0 counting value input and output of the N-th order bit data of 2bit, 4bit, 8bit and 32bit … … 2 is performed respectively, and the logic relation between the input signal and the output signal of the count value conversion circuit module is combined, so that the digital circuit of the following count value conversion module is obtained, and the digital circuit is shown in fig. 3:
the count self-adding preparation circuit module is used for generating data of 1bit0 into the memory array. When the counting is needed, the data 0 is written into the memory array, so that only the number of 0 is read out and then the counting is increased by 1, namely the number of 0 is increased by 1, and then 16bit data corresponding to the new number of 0 is obtained, namely the data programmed into the memory array, thereby completing the counting. For example, if the non-full 0 data counted last time is 16' hffff 8, the data coded in the memory array this time is 16' hffff 0, and 4 bits of 0 are in the 16' hffff 0, and the embodiment only needs to code 1bit of 0 for programming the 16' hffff 0, so that the data coded in the memory array is 16' hffff 7, so that the power consumption in the process of counting is low, the programming time is short, and the overall performance of the chip is improved.
The count self-priming circuit module logic continues to analyze as follows:
the count self-adding preparation circuit module takes the number of 0 s as an input signal to obtain 16bit data to be programmed into the count storage array. The logic between the input signal and the output signal need then only be developed from a table, as shown in fig. 4.
First, when the input signal mcl_cout <4> is 1, the 16 bits of data representing programming into the memory array will be all 0 s.
When mcl_cout <4> is 0 and mcl_cout <3> is 0, the upper 8 bits of the 16 bits of data representing programming into the memory array are 1; when mcl_cout <4> is 0 and mcl_cout <3> is 1, the lower 8 bits of the 16-bit data representing programming into the memory array are 0.
When mcl_cout <4> is 0, mcl_cout <3> is 0, and mcl_cout <2> is 0, the upper 4 bits representing the lower 8 bits of the 16-bit data programmed into the memory array are 1, which is the overall thing
mcl_pgm[15:0]＝16’b1111_1111_1111_1xxx；
When mcl_cout <4> is 0, mcl_cout <3> is 0, and mcl_cout <2> is 1, the lower 4 bits representing the lower 8 bits of the 16-bit data programmed into the memory array are 0, which is the overall thing
16’bmcl_pgm[15:0]＝16’b1111_1111_1xxx_0000；
When mcl_cout <4> is 0, mcl_cout <3> is 1, and mcl_cout <2> is 0, the upper 4 bits representing the upper 8 bits of 16-bit data programmed into the memory array are 1, which is the overall
mcl_pgm[15:0]＝16’b1111_1xxx_0000_0000；
When mcl_cout <4> is 0, mcl_cout <3> is 1, and mcl_cout <2> is 1, the lower 4 bits representing the upper 8 bits of 16-bit data programmed into the memory array are 0, which is the overall thing
mcl_pgm[15:0]＝16’b1xxx_0000_0000_0000；
When mcl_cout <4> is 0, mcl_cout <3> is 0, mcl_cout <2> is 0, mcl_cout <1> is 0, 2' b [3:2] =2 ' b11 in the 16-bit data programmed into the memory array is represented, collectively mcl_pgm [15:0] =16 ' b 1111_1111_1111_1111_111 x;
when mcl_cout <4> is 0, mcl_cout <3> is 0, mcl_cout <2> is 0, mcl_cout <1> is 1, 2' b [1:0] =2 ' b00 in the 16-bit data programmed into the memory array is represented, collectively mcl_pgm [15:0] =16 ' b 1111_1111_1111_1111_1x00;
when mcl_cout <4> is 0, mcl_cout <3> is 0, mcl_cout <2> is 1, mcl_cout <1> is 0, 2' b [7:6] = 2' b11 in the 16-bit data programmed into the memory array is represented, collectively mcl_pgm [15:0] = 16' b 1111_1111_111_0000;
when mcl_cout <4> is 0, mcl_cout <3> is 0, mcl_cout <2> is 1, mcl_cout <1> is 1, 2' b [5:4] =2 ' b00 in the 16-bit data representing programming into the memory array, collectively mcl_pgm [15:0] =16 ' b1111_1111_1x00_0000;
when mcl_cout <4> is 0, mcl_cout <3> is 1, mcl_cout <2> is 0, mcl_cout <1> is 0, 2' b [11:10] = 2' b11 in the 16-bit data programmed into the memory array is represented, collectively mcl_pgm [15:0] = 16' b 1111_111x_0000;
when mcl_cout <4> is 0, mcl_cout <3> is 1, mcl_cout <2> is 0, mcl_cout <1> is 1, 2' b [9:8] =2 ' b00 in the 16-bit data representing programming into the memory array, collectively mcl_pgm [15:0] =16 ' b 1111_1x00_0000;
when mcl_cout <4> is 0, mcl_cout <3> is 1, mcl_cout <2> is 1, mcl_cout <1> is 0, 2' b [15:14] =2 ' b11 in the 16-bit data representing programming into the memory array, collectively mcl_pgm [15:0] =16 ' b111x_0000_0000_0000;
when mcl_cout <4> is 0, mcl_cout <3> is 1, mcl_cout <2> is 1, mcl_cout <1> is 1, 2' b [13:12] = 2' b00 in the 16-bit data programmed into the memory array is represented, collectively mcl_pgm [15:0] = 16' b1x00_0000_0000;
when mcl_cout [4:0] =5 'b0_0000, the 16 bits representing the data programmed into the memory array would be all 16' hfff; when mcl_cout [4:0] =5 'b0_0001, the 16-bit data representing programming into the memory array would be all 16' hffe; when mcl_cout [4:0] =5 'b0_0010, the 16-bit data representing programming into the memory array will be all 16' hffffc; when mcl_cout [4:0] =5 'b0_0011, the 16-bit data representing programming into the memory array will be all 16' hfff8; when mcl_cout [4:0] =5 'b0_0100, the 16-bit data representing programming into the memory array will be all 16' hfff0; when mcl_cout [4:0] =5 'b0_0101, the 16-bit data representing programming into the memory array will be all 16' hffe0; when mcl_cout [4:0] =5 'b0_0110, the 16-bit data representing programming into the memory array will be all 16' hffc0; when mcl_cout [4:0] =5 'b0_0111, the 16-bit data representing programming into the memory array will be all 16' hfff 80; when mcl_cout [4:0] =5 'b0_1000, the 16-bit data representing programming into the memory array would be all 16' hfff00; when mcl_cout [4:0] =5 'b0_1001, the 16-bit data representing programming into the memory array would be all 16' hfe00; when mcl_cout [4:0] =5 'b0_1010, the 16-bit data representing programming into the memory array would be all 16' hfc00; when mcl_cout [4:0] =5 'b0_1011, the 16-bit data representing programming into the memory array would be all 16' hf800; when mcl_cout [4:0] =5 'b0_1100, the 16-bit data representing programming into the memory array would be all 16' hf000; when mcl_cout [4:0] =5 'b0_1101, the 16 bits representing the data programmed into the memory array would be all 16' hes; when mcl_cout [4:0] =5 'b0_1110, the 16-bit data representing programming into the memory array would be all 16' hc000; when mcl_cout [4:0] =5 'b0_1111, the 16-bit data representing programming into the memory array would be all 16' h8000; when mcl_cout [4:0] =5 'b1_0000, the 16 bits representing data programmed into the memory array would be all 16' h0000.
From the above-described inference analysis of the truth table, logic can be designed to count the self-priming circuit blocks, such as: mcl_cout <4> =1, mcl_pgm [15:0] =16' h0000. For another example, mcl_cout <3:0> =4 ' h5=4 ' b0101, mcl_cout <3> =0, mcl_pgm [15:8] =8 ' hff; mcl_cout <2> =1, mcl_pgm [3:0] =4' h00; mcl_cout <1> =0, mcl_pgm [7:6] =2' b11; mcl_cout <0> =1, mcl_pgm [5:4] =2 'b10, so that data mcl_pgm [15:0] =16' hffe0 is obtained.
Summarizing this logic is shown in fig. 5:
the count self-priming circuit block may also be implemented by left shift logic, such as mcl_pgm [15:0] = 16' hfffff < < mcl_cout [4:0], shifting left 16 times generates the data to be programmed, but based on the comparison of the actual integrated circuits (as shown in fig. 6 and 7), it is found that the more mos transistors are used by the circuits using the left shift logic, the larger area is used. Therefore, in this embodiment, a multi-bit or one-bit rule corresponding to the value of each bit mcl_cout [4:0] mcl_pgm [15:0] is selected to realize the circuit design.
Further, by careful statistics, the count self-priming circuit module circuit for the left shift logic implementation has 164 mos tubes in total, while the count self-priming circuit module circuit for the corresponding logic implementation of fig. 5 has 140 mos tubes in total, which is reduced in area by 17.14% compared to the circuit for the left shift logic implementation.
Example 3
The present embodiment provides a chip circuit including the counter circuit structure in the foregoing embodiment.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to the embodiments described in detail below, and that the embodiments described in the examples may be combined as appropriate to form other embodiments that will be apparent to those skilled in the art.
Claims (10)
1. The efficient monotonic counting method based on the Flash storage array is characterized by comprising the following steps of:
performing an erase operation on the memory array;
sequentially executing one-bit programming operation on the memory array according to one count, and specifically comprises the following steps:
receiving a counting enabling signal, obtaining the address of non-all-zero data in the storage array and programmed bit number information in the non-all-zero data, and processing to obtain a current recorded numerical value;
and adding one to the current recorded value, processing to generate data information of the bit to be programmed, and executing programming operation on the bit to be programmed.
2. The efficient monotonic counting method based on Flash memory array as recited in claim 1, wherein the program operation further comprises a program verify operation after execution, and if the program operation does not pass, continuing to execute the program operation on the bit until the program verify passes.
3. The efficient monotonic counting method based on Flash memory array as recited in claim 1, wherein the bits to be programmed are the least significant bits of non-all-zero data that are not programmed;
if the non-all zero data is not read, a full signal is fed back.
4. The high-efficiency monotonic counter based on the Flash storage array comprises a storage array module, an erasing circuit module and a programming circuit module, and is characterized by further comprising a count value conversion circuit module and a count self-adding preparation circuit module;
the count value conversion circuit module is configured to process and output a stored count value according to the address of the non-all-zero data in the storage array module and the programmed bit number information in the non-all-zero data;
the count self-adding preparation circuit module is configured to generate count self-adding programming data according to the stored count value output by the count value conversion circuit module, and send the count self-adding programming data into the programming circuit module to execute programming operation on the memory array module.
5. The Flash storage array-based high-efficiency monotonic counter as recited in claim 4, wherein the address of the non-all zero data is obtained as follows:
reading data in the memory array module according to a preset reading bit number;
if the data of the target address is all zero, continuing to read according to the address sequence until the non-all-zero data is read or the target address is a tail address:
if the non-all zero data is read, returning the address where the non-all zero data is located and bit number information of zero data in the non-all zero data;
if the target address is the tail address, a full signal is fed back.
6. The efficient monotonic counter based on a Flash memory array as recited in claim 5, wherein the predetermined number of read bits comprises one or more of 8 bits, 16 bits, and 32 bits.
7. The efficient monotonic counter based on a Flash memory array as recited in claim 6, wherein the predetermined number of read bits is 16 bits, the count value conversion circuit module comprises a 16-bit read data to 5-bit count value circuit, wherein,
where cout_4..cout_0 is a 5-bit count value, and read_15..read_0 is 16-bit read data.
8. The efficient monotonic counter based on Flash memory array as recited in claim 7, wherein the self-adding preparation circuit module comprises a 5-bit new count value to 16-bit programming data circuit, and the configuration circuit is directly mapped according to the 16-bit programming data value corresponding to each new count value, and specifically comprises:
ncout [4:0] =5 'b0_0000 corresponds to pgm [15:0] =16' hfffff;
ncout [4:0] =5 'b0_0001 corresponds to pgm [15:0] =16' hffe;
ncout [4:0] =5 'b0_0010 corresponds to pgm [15:0] =16' hffc;
ncout [4:0] =5 'b0_0011 corresponds to pgm [15:0] =16' hfff8;
ncout [4:0] =5 'b0_0100 corresponds to pgm [15:0] =16' hfff0;
ncout [4:0] =5 'b0_0101 corresponds to pgm [15:0] =16' hfffe0;
ncout [4:0] =5 'b0_0110 corresponds to pgm [15:0] =16' hffc0;
ncout [4:0] =5 'b0_0111 corresponds to pgm [15:0] =16' hf80;
ncout [4:0] =5 'b0_1000 corresponds to pgm [15:0] =16' hf00;
ncout [4:0] =5 'b0_1001 corresponds to pgm [15:0] =16' hfe00;
ncout [4:0] =5 'b0_1010 corresponds to pgm [15:0] =16' hfc00;
ncout [4:0] =5 'b0_1011 corresponds to pgm [15:0] =16' hf800;
ncout [4:0] =5 'b0_1100 corresponds to pgm [15:0] =16' hf000;
ncout [4:0] =5 'b0_1101 corresponds to pgm [15:0] =16' he000;
ncout [4:0] =5 'b0_1110 corresponds to pgm [15:0] =16' hc000;
ncout [4:0] =5 'b0_1111 corresponds to pgm [15:0] =16' h8000;
ncout [4:0] =5 'b1_0000 corresponds to pgm [15:0] =16' h0000;
where Ncout [4:0] is a 5-bit new count value and pgm [15:0] is a 16-bit program data value.
9. The efficient monotonic counter based on Flash memory array as recited in claim 8, wherein said count self-priming circuit module is implemented by left shift logic.
10. A chip circuit comprising a circuit structure of a monotonic counter as recited in any one of claims 4-9.
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