CN115987289A - High-linearity sigma-delta modulator - Google Patents
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The application discloses a high linearity sigma-delta modulator, comprising: the system comprises an integrator, an adder, a multi-bit quantizer and a feedback DAC; the adder is connected with the integrator, the multi-bit quantizer and the feedback DAC in series; the adder comprises two stages: the first stage is an active adder, the second stage is a passive amplifier, and the output end of the active adder is electrically connected with the input end of the passive amplifier. The invention adopts a two-stage adder structure, the active adder only provides 1/2 of the original gain, the passive amplification of 2 times is carried out by introducing the charge pump of the passive amplification after the active adder, the output range of the operational amplifier in the adder is reduced while the total gain is not changed, thereby improving the linearity of the modulator, obviously reducing the output range of the active operational amplifier and greatly improving the linearity of the sigma-delta modulator.
Description
Technical Field
The application relates to the technical field of sigma-delta modulators, in particular to a high-linearity sigma-delta modulator.
Background
The output of an adder of a common multi-bit quantization sigma-delta modulator is close to rail-to-rail swing, an active operational amplifier is generally adopted as the adder in the sigma-delta modulator, and because an output stage MOS of the operational amplifier needs to work in a saturation region, the output swing range meeting high linearity is [ VDS, VDD-VDS ], wherein VDD is power supply voltage, and VDS is drain-source voltage of an MOS tube. When the input signal of the sigma-delta modulator is large, the output swing range reaches 0, VDD.
However, when the output of the active operational amplifier is operated close to the power supply or close to the ground, i.e., when the output voltage is close to 0 and VDD, the output stage MOS transistor of the active operational amplifier is operated in the linear region and cannot provide a large gain to obtain high linearity, resulting in a decrease in linearity, thereby affecting the performance of the Modulator (see references: A0.7-V870- μ W Digital-Audio CMOS Sigma-Delta Modulator, IEEE J.solid-State Circuits, vol.44, no.4, pp.1078-1087, april 2009).
A conventional 3-order single-loop feedforward sigma-delta modulator is shown in fig. 1, wherein 101 represents a first-stage integrator, 102 represents a second-stage integrator, 103 represents a third-stage integrator, 104 represents a summer, 105 represents a multi-bit quantizer, and 106 represents a feedback DAC; a1, a2, a3 are feedforward coefficients of the first stage integrator, the second stage integrator and the third stage integrator, respectively, b1, b2 are gains of the input signal U to the respective paths, and c1, c2, c3 are the gain of the feedback DAC, the gain of the first stage integrator and the gain of the second stage integrator, respectively.
The implementation of the feedforward coefficients and the b2 path gain of the a1, a2, a3 three-stage integrators in fig. 1 is implemented by the switched capacitors CA1, CA2, CA3, CA4 and the feedback capacitor CF in the conventional active adder circuit shown in fig. 2. In a period phi 1, an input signal U and outputs VO1, VO2 and VO3 of the three-stage integrator are respectively sampled on capacitors CA1, CA2, CA3 and CA4, and proportional amplification is completed through a feedback capacitor CF, so that the following calculation formula can be obtained:
b1＝CA1/CF，a1＝CA2/CF，a2＝CA3/CF，a3＝CA4/CF (1)
the active adder output Vadd is calculated as: vadd = CA1/CF × U + CA2/CF × VO1+ CA3/CF × VO2+ CA4/CF × VO3 (2)
When the input signal U in equation (2) is close to the full swing, the output Vadd of the active adder is also close to the full swing, so that the output stage of the operational amplifier 201 therein operates in a linear region, thereby reducing the output linearity.
Disclosure of Invention
Therefore, the embodiment of the present invention intends to provide a two-stage adder based on active amplification of an operational amplifier and passive amplification of a charge pump, wherein the charge pump can provide gain, and can reduce the amplification factor of the operational amplifier under the condition that the loop gain of a sigma-delta modulator is not changed, so that the output of the operational amplifier works in a rail-to-rail range of about 1/2, and MOS transistors of an output stage of the operational amplifier can all work in a saturation region, thereby improving the linearity of the whole adder.
The invention provides a high linearity sigma-delta modulator, comprising: the system comprises an integrator, an adder, a multi-bit quantizer and a feedback DAC; the adder is connected in series with the integrator, the multi-bit quantizer and the feedback DAC;
the adder comprises two stages: the first stage is an active adder, the second stage is a passive amplifier, and the output end of the active adder is electrically connected with the input end of the passive amplifier.
Furthermore, the number of the adders is 2, wherein 1 of the adders is electrically connected with the output end of the integrator and the input end of the multi-bit quantizer respectively, and the other 1 of the adders is electrically connected with the output end of the feedback DAC and the input end of the integrator respectively.
Further, the integrator comprises a three-stage integrator: the system comprises a first-stage integrator, a second-stage integrator and a third-stage integrator, wherein the outputs of the first-stage integrator, the second-stage integrator and the third-stage integrator are VO1, VO2 and VO3 respectively.
Further, the active adder includes: a CA1 capacitor, a CA2 capacitor, a CA3 capacitor, a CA4 capacitor, a phi 1 switch, a phi 2 switch, an operational amplifier and a CF feedback capacitor; the CA1 capacitor, the CA2 capacitor, the CA3 capacitor and the CA4 capacitor are connected in parallel in four ways, and the CA1 capacitor, the CA2 capacitor, the CA3 capacitor and the CA4 capacitor are respectively connected with input signals U, VO, VO2 and VO3; the CF feedback capacitor is arranged between the input end and the output end Vadd of the operational amplifier;
the number of the phi 1 switches is 4, and each phi 1 switch is respectively and electrically connected between an input signal U and the input end of a CA1 capacitor, between the output VO1 of the first-stage integrator and the input end of a CA2 capacitor, between the output VO2 of the second-stage integrator and the input end of a CA3 capacitor, and between the output VO3 of the third-stage integrator and the input end of a CA4 capacitor;
the number of the phi 2 switches is 6, wherein 4 phi 2 switches are respectively arranged at the Vcm input ends of the CA1 capacitor, the CA2 capacitor, the CA3 capacitor and the CA4 capacitor, 1 phi 2 switch is arranged between the Vcm input end and the input end of the operational amplifier in series, and 1 phi 2 switch is arranged at the input end and the output end of the CF feedback capacitor in parallel.
Further, the passive amplifier is a passive amplifying charge pump.
Further, the passive amplifying charge pump includes: the circuit comprises a CS1 capacitor, a CS2 capacitor, a phi s switch and a phi R switch, wherein the CS1 capacitor is connected with the CS2 capacitor in parallel; the number of the phi R switches is 2, wherein 1 phi R switch is respectively electrically connected with the input end of the CS1 capacitor and the output end of the CS2 capacitor, and the other 1 phi R switch is respectively electrically connected with the output end of the CS1 capacitor and the Gnd grounding end of the CS1 capacitor; the number of the phi s switches is 4, wherein 2 phi s switches are respectively arranged at the input ends of the CS1 capacitor and the CS2 capacitor, and the other 2 phi s switches are respectively arranged at Gnd grounding ends of the CS1 capacitor and the CS2 capacitor.
Further, the capacitance value C of the CS1 capacitor is equal to the capacitance value C of the CS2 capacitor.
Further, when the position of the Φ s switch is at a high level, the Φ s switch is controlled to be closed, and the output VB of the passive amplification charge pump = input VA; when the position of the Φ R switch is at a high level, the Φ R switch is controlled to be closed, and VB × C = VA × 2C, that is, VB =2VA is obtained according to charge conservation; since VA is the output of the active adder, i.e., VA = Vadd/2, and the final output of the adder, VB = Vadd, the adder output is the same and the output of the active amplifier is halved compared to the conventional adder structure consisting of only active amplifiers.
The whole adder consists of two stages of amplifiers, wherein the first stage is an active adder, and the second stage is a passive charge pump amplifier. Assuming that the total amplification factor is A, the feedforward coefficients of integrators of all stages of the sigma-delta modulator are proportionally added and amplified by the active adder of the first stage through a switched capacitor and an operational amplifier, and the passive charge pump amplifier of the second stage provides 2 times of gain, so that the loop gain A of the whole sigma-delta modulator is not changed, the output range of the active adder is halved, and the linearity of the operational amplifier of the active adder is improved.
Compared with the prior art, the invention has the beneficial effects that:
the invention adopts a two-stage adder structure, the active adder only provides 1/2 of the original gain, passive 2-fold amplification is carried out by introducing a passive amplification charge pump after the active adder, the output range of an operational amplifier in the adder is reduced while the total gain is not changed, thereby improving the linearity of the modulator, obviously reducing the output range of the active operational amplifier and greatly improving the linearity of the sigma-delta modulator.
Drawings
Embodiments of the invention will hereinafter be described in detail with reference to the accompanying drawings, wherein the elements shown are not to scale as shown in the figures, and wherein like or similar reference numerals denote like or similar elements, and wherein:
a schematic diagram of a conventional 3 rd order single-loop feed-forward sigma-delta modulator is shown in fig. 1;
a conventional active adder circuit diagram is shown in fig. 2;
FIG. 3 illustrates a conventional adder timing diagram;
FIG. 4 illustrates a two-stage active amplification + passive amplification charge pump adder configuration according to an embodiment of the present invention;
a passive amplified charge pump circuit and timing sequence of an embodiment of the present invention is shown in fig. 5.
Labeled in the figures of the drawings:
101. a first stage integrator, 102, a second stage integrator, 103, a third stage integrator, 104, an adder, 105, a multi-bit quantizer, 106, a feedback DAC,107, another adder, 201, an operational amplifier of a conventional active adder, 401, an operational amplifier of an active adder according to the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the following detailed description and accompanying drawings. The exemplary embodiments and descriptions of the present invention are provided to explain the present invention, but not to limit the present invention.
The term "including" and variations thereof as used herein is intended to be open-ended, i.e., "including but not limited to". The term "or" means "and/or" unless specifically stated otherwise. The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like may refer to different or the same objects. Other explicit and implicit definitions are also possible below.
In an embodiment of the invention there is provided a high linearity sigma-delta modulator comprising: an integrator, an adder 104, a multi-bit quantizer 105, and a feedback DAC106.
The integrator is connected in series with the adder 104, the multi-bit quantizer 105 and the feedback DAC106.
The adder 104 includes two stages: the first stage is an active adder, the second stage is a passive amplifier, and the output end of the active adder is electrically connected with the input end of the passive amplifier.
The number of the adders 104 is 2, wherein 1 adder 104 is electrically connected to the output end of the integrator and the input end of the multi-bit quantizer, and the other 1 adder 107 is electrically connected to the output end of the feedback DAC106 and the input end of the integrator.
In this embodiment, the integrator includes a three-stage integrator: the system comprises a first-stage integrator 101, a second-stage integrator 102 and a third-stage integrator 103, wherein the outputs of the first-stage integrator 101, the second-stage integrator 102 and the third-stage integrator 103 are VO1, VO2 and VO3 respectively.
The active adder includes: CA1 capacitor, CA2 capacitor, CA3 capacitor, CA4 capacitor, phi 1 switch, phi 2 switch, operational amplifier, CF feedback capacitor.
The CA1 capacitor, the CA2 capacitor, the CA3 capacitor and the CA4 capacitor are connected in parallel in four ways, and the CA1 capacitor, the CA2 capacitor, the CA3 capacitor and the CA4 capacitor are respectively connected with input signals U, VO, VO2 and VO3.
The CF feedback capacitor is disposed between the input terminal and the output terminal Vadd of the operational amplifier.
The number of the Φ 1 switches is 4, each Φ 1 switch is electrically connected between the input signal U and the input end of the CA1 capacitor, between the output VO1 of the first-stage integrator 101 and the input end of the CA2 capacitor, between the output VO2 of the second-stage integrator 102 and the input end of the CA3 capacitor, and between the output VO3 of the third-stage integrator 103 and the input end of the CA4 capacitor.
The number of the phi 2 switches is 6, wherein 4 phi 2 switches are respectively arranged at the Vcm input ends of the CA1 capacitor, the CA2 capacitor, the CA3 capacitor and the CA4 capacitor, 1 phi 2 switch is arranged between the Vcm input end and the input end of the operational amplifier in series, and 1 phi 2 switch is arranged at the input end and the output end of the CF feedback capacitor in parallel.
In this embodiment, the passive amplifier is a passive amplification charge pump. The passive amplifying charge pump includes: the circuit comprises a CS1 capacitor, a CS2 capacitor, a phi s switch and a phi R switch, wherein the CS1 capacitor is connected with the CS2 capacitor in parallel; the number of the phi R switches is 2, wherein 1 phi R switch is respectively electrically connected with the input end of the CS1 capacitor and the output end of the CS2 capacitor, and the other 1 phi R switch is respectively electrically connected with the output end of the CS1 capacitor and the Gnd grounding end of the CS1 capacitor; the number of the phi s switches is 4, wherein 2 phi s switches are respectively arranged at the input ends of the CS1 capacitor and the CS2 capacitor, and the other 2 phi s switches are respectively arranged at Gnd grounding ends of the CS1 capacitor and the CS2 capacitor.
The capacitance value C of the CS1 capacitor is equal to that of the CS2 capacitor. When the position of the phi s switch is at a high level, the phi s switch is controlled to be closed, and the output VB = input VA of the passive amplification charge pump; when the position of the Φ R switch is at a high level, the Φ R switch is controlled to be closed, and VB × C = VA × 2C, that is, VB =2VA is obtained according to charge conservation; since VA is the output of the active adder, i.e., VA = Vadd/2, and the final output of the adder, VB = Vadd, the adder output is the same and the output of the active amplifier is halved compared to a conventional adder structure consisting of only active amplifiers.
The whole adder of the embodiment of the invention consists of two stages of amplifiers, wherein the first stage is an active adder, and the second stage is a passive charge pump amplifier. Assuming that the total amplification factor is a, the first-stage active adder adds and amplifies feedforward coefficients of integrators of each stage of the sigma-delta modulator by a switched capacitor and an operational amplifier according to a proportion of a/2, and the second-stage passive charge pump amplifier provides 2-fold gain, so that the loop gain a of the whole sigma-delta modulator is not changed, and the output range of the active adder is halved, thereby improving the linearity of the operational amplifier 401 of the active adder.
The adder structure of an active adder + passive amplified charge pump of an embodiment of the present invention is shown in fig. 4. The adder is divided into two stages, the first stage is an active adder, and the second stage is a passive amplifier. The active adder structure is substantially the same as that of fig. 2, except that the capacitance of the feedback capacitor CF is 2 times that of the conventional adder structure, so that the output of the active adder is equal to half of the output Vadd of the conventional adder structure, namely Vadd/2; when the input signal U is close to the full swing, vadd/2 is only half of the full swing, the output stage of the operational amplifier 401 still operates in the saturation region, and the output linearity is not affected. However, the gain of the active amplification adder is only 1/2 of the original gain, and the loop gain is not changed, and the passive amplification charge pump 402 according to the embodiment of the present invention amplifies the output of the active amplification adder by 2 times, so that the output range of the active amplification adder is reduced and the linearity of the modulator is improved under the condition that the loop gain is not changed.
The conventional active adder operating timing is shown in fig. 3.Φ 1, Φ 2 are two-phase non-overlapping clocks. When phi 1 is high level, the adder completes proportional amplification; when phi 2 is high level, the adder completes zero clearing for next proportional amplification. Fig. 5 shows a passive amplification charge pump circuit and an operation timing sequence of the embodiment of the invention, where Φ s and Φ R are two-phase non-overlapping clocks. When phi s is high level, the passive amplification charge pump completes proportional amplification; and when the phi R is in a high level, the passive amplification charge pump completes zero clearing so as to carry out the next proportional amplification.
The embodiment of the invention adopts a two-stage adder structure, the active adder only provides 1/2 of the original gain, the passive 2-time amplification is carried out by introducing the passive amplification charge pump after the active adder, the output range of the operational amplifier in the adder is reduced while the total gain is not changed, thereby improving the linearity of the modulator, obviously reducing the output range of the active operational amplifier and greatly improving the linearity of the sigma-delta modulator
As will be appreciated by one skilled in the art, embodiments of the present description may be provided as a method, system, or computer program product. Thus, it will be apparent to one skilled in the art that the implementation of the functional modules/units or controllers and the associated method steps set forth in the above embodiments may be implemented in software, hardware, and a combination of software and hardware.
Unless specifically stated otherwise, the actions or steps of a method, program or process described in accordance with an embodiment of the present invention need not be performed in a particular order and still achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
While various embodiments of the invention have been described herein, the description of the various embodiments is not intended to be exhaustive or to limit the invention to the precise forms disclosed, and features and components that are the same or similar to one another may be omitted for clarity and conciseness. As used herein, "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means applicable in at least one embodiment or example, but not in all embodiments, in accordance with the present invention. The above terms are not necessarily meant to refer to the same embodiment or example. Various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Exemplary systems and methods of the present invention have been particularly shown and described with reference to the foregoing embodiments, which are merely illustrative of the best modes for carrying out the systems and methods. It will be appreciated by those skilled in the art that various changes in the embodiments of the systems and methods described herein may be made in practicing the systems and/or methods without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A high linearity sigma-delta modulator, comprising: the system comprises an integrator, an adder, a multi-bit quantizer and a feedback DAC; the adder is connected with the integrator, the multi-bit quantizer and the feedback DAC in series;
the adder comprises two stages: the first stage is an active adder, the second stage is a passive amplifier, and the output end of the active adder is electrically connected with the input end of the passive amplifier.
2. The high linearity sigma-delta modulator of claim 1, wherein the number of adders is 2, wherein 1 adder is electrically connected to the output of the integrator and the input of the multi-bit quantizer, and another 1 adder is electrically connected to the output of the feedback DAC and the input of the integrator.
3. The high linearity sigma-delta modulator of claim 1, wherein said integrator comprises a three-stage integrator: the output of first order integrator, second grade integrator, third grade integrator is VO1, VO2, VO3 respectively.
4. The high linearity sigma-delta modulator of claim 3, wherein said active summer comprises: a CA1 capacitor, a CA2 capacitor, a CA3 capacitor, a CA4 capacitor, a phi 1 switch, a phi 2 switch, an operational amplifier and a CF feedback capacitor; the CA1 capacitor, the CA2 capacitor, the CA3 capacitor and the CA4 capacitor are connected in parallel in four ways, and the CA1 capacitor, the CA2 capacitor, the CA3 capacitor and the CA4 capacitor are respectively connected with input signals U, VO, VO2 and VO3; the CF feedback capacitor is arranged between the input end and the output end Vadd of the operational amplifier;
the number of the phi 1 switches is 4, and each phi 1 switch is respectively and electrically connected between input signals U and the input end of a CA1 capacitor, between the output VO1 of a first-stage integrator and the input end of a CA2 capacitor, between the output VO2 of a second-stage integrator and the input end of a CA3 capacitor, and between the output VO3 of a third-stage integrator and the input end of a CA4 capacitor;
the number of the phi 2 switches is 6, wherein 4 phi 2 switches are respectively arranged at the Vcm input ends of the CA1 capacitor, the CA2 capacitor, the CA3 capacitor and the CA4 capacitor, 1 phi 2 switch is arranged between the Vcm input end and the input end of the operational amplifier in series, and 1 phi 2 switch is arranged at the input end and the output end of the CF feedback capacitor in parallel.
5. The high linearity sigma-delta modulator of claim 1, wherein said passive amplifier is a passive amplifying charge pump.
6. The high linearity sigma-delta modulator of claim 5, wherein said passive amplifying charge pump comprises: the circuit comprises a CS1 capacitor, a CS2 capacitor, a phi s switch and a phi R switch, wherein the CS1 capacitor is connected with the CS2 capacitor in parallel; the number of the phi R switches is 2, wherein 1 phi R switch is respectively electrically connected with the input end of the CS1 capacitor and the output end of the CS2 capacitor, and the other 1 phi R switch is respectively electrically connected with the output end of the CS1 capacitor and the Gnd grounding end of the CS1 capacitor; the number of the phi s switches is 4, wherein 2 phi s switches are respectively arranged at the input ends of the CS1 capacitor and the CS2 capacitor, and the other 2 phi s switches are respectively arranged at Gnd grounding ends of the CS1 capacitor and the CS2 capacitor.
7. The high linearity sigma-delta modulator of claim 6, wherein the capacitance value C of the CS1 capacitance and the capacitance value C of the CS2 capacitance are equal.
8. The high linearity sigma-delta modulator of claim 7, wherein when the Φ s switch is high, the Φ s switch control is closed, the output of the passive amplifying charge pump VB = input VA; when the position of the phi R switch is at a high level, the phi R switch is controlled to be closed, and VB x C = VA x 2C and VB =2VA are obtained according to charge conservation; VA = Vadd/2, and the final output of the adder VB = Vadd.
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| CN114362681A (en) * | 2022-01-07 | 2022-04-15 | 深圳昂瑞微电子技术有限公司 | Two-stage broadband low-noise high-linearity amplifier |
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| US20140070972A1 (en) * | 2012-09-10 | 2014-03-13 | Imec | Circuit For Digitizing A Sum Of Signals |
| CN114362681A (en) * | 2022-01-07 | 2022-04-15 | 深圳昂瑞微电子技术有限公司 | Two-stage broadband low-noise high-linearity amplifier |
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