CN115987078A - RT current generation circuit with clamping - Google Patents
RT current generation circuit with clamping Download PDFInfo
- Publication number
- CN115987078A CN115987078A CN202310182214.4A CN202310182214A CN115987078A CN 115987078 A CN115987078 A CN 115987078A CN 202310182214 A CN202310182214 A CN 202310182214A CN 115987078 A CN115987078 A CN 115987078A
- Authority
- CN
- China
- Prior art keywords
- tube
- pmos tube
- nmos tube
- current
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Dc-Dc Converters (AREA)
Abstract
The invention belongs to the field of integrated circuits and switching power supplies, and particularly relates to a RT current generating circuit with a clamp. The invention controls the current of the relaxation oscillator based on changing the external RT resistor, thereby changing the control frequency. On the basis of this, the current I is utilized RT The proportional current charges the capacitor, the capacitor is compared with the fixed current, and the voltage at the capacitor is fed back to the grid of the output current mirror, so that the upper limit and the lower limit of the RT current capacitor are set, the RT current is effectively limited, and the oscillator can work in a normal range under the condition that the RT resistance value is extreme.
Description
Technical Field
The invention relates to the field of integrated circuits and switching power supplies, in particular to a RT current generating circuit with a clamp.
Background
Miniaturized electronic devices require smaller size of the switching power supply and therefore higher frequency requirements, once to reduce the size of the peripheral components. A 10MHz relaxation oscillator generally has three operating frequencies, namely a fixed frequency, a default frequency and an external frequency, wherein when the relaxation oscillator operates at an adjustable frequency, the current of the oscillator is changed by externally connecting a variable resistor RT.
The relaxation oscillator generally changes the frequency by changing the magnitude of charging current for a fixed capacitor of the relaxation oscillator, when an RT resistor is connected to the outside of a switching power supply, two extreme conditions are considered, one of which is a short circuit and then the RT current is infinite, a circuit can be burnt out, the other is an open circuit and then the current is infinite, the circuit can not work, and therefore the two extreme conditions need to be limited to ensure the normal work of the oscillator.
Disclosure of Invention
In order to meet the requirements, the invention provides the RT current generating circuit with the clamp, which utilizes the current clamp function to limit the RT current within a certain range, so that the oscillator keeps normal working frequency.
Charging the capacitor by using a current proportional to the RT current, comparing the charging current with a fixed current, and pulling up the potential at a node of the capacitor to limit the RT current from being overlarge when the charging current is larger than a certain value; when the voltage is less than a certain value, the point position at the other capacitor node is pulled down to prevent the RT current from being too small.
The technical scheme of the invention is as follows:
a kind of RT current generating circuit with clamp, is used for utilizing the relaxation oscillator that RT current forms, the relaxation oscillator that said RT current forms includes current source IRT, the first electric capacity, the second electric capacity, the first switch, the second switch, the first comparator, the second comparator, the first RS trigger and the first phase inverter;
one end of the first capacitor is connected with a current source IRT, one end of a first switch and the non-inverting input end of the first comparator, and the other end of the first capacitor and the other end of the first switch are grounded;
one end of the second capacitor is connected with the current source IRT, one end of the second switch and the non-inverting input end of the second comparator, and the other end of the second capacitor and the other end of the second switch are grounded;
the inverting input end of the first comparator is connected with reference voltage VREF, and the output end of the first comparator is connected with the R end of the first RS trigger;
the inverting input end of the first comparator is connected with the reference voltage VREF, and the output end of the first comparator is connected with the S end of the first RS trigger;
the enabling end of the first RS trigger is connected with an enabling signal EN, and the output end of the first RS trigger is connected with the input end of the first inverter and the control end of the first switch;
the output end of the first inverter is connected with the control end of the second switch and is used as a PWM output end at the same time;
the RT current generation circuit with the clamp is used for controlling the size of a current source IRT and comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a first resistor, a third capacitor, a fourth capacitor and a fifth capacitor;
the source electrode of the first PMOS tube is connected with a power supply VIN, the grid electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the sixth PMOS tube, the source electrode of the seventh PMOS tube, the grid electrode of the ninth PMOS tube, the drain electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube, and the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube;
the grid electrode of the second PMOS tube is connected with a first control signal EN1;
the source electrode of the third PMOS tube is connected with a power VIN, and the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube;
the grid electrode of the fourth PMOS tube is connected with a second control signal EN2, and the drain electrode of the fourth PMOS tube is connected with one end of a third capacitor, the drain electrode of the fifth PMOS tube, the grid electrode of the eleventh PMOS tube and the drain electrode of the third NOMS tube;
the other end of the third capacitor is grounded;
the source electrode of the fifth PMOS tube is connected with a power supply VIN, and the grid electrode of the fifth PMOS tube is connected with an eighth control signal EN8;
a grid electrode of the sixth PMOS tube is connected with the power supply VIN, and a drain electrode of the sixth PMOS tube is connected with a grid electrode of the seventh PMOS tube, a drain electrode of the eighth PMOS tube, a drain electrode of the fifth NMOS tube and one end of the fourth capacitor;
the other end of the fourth capacitor is connected with a power supply VIN;
the drain electrode of the seventh PMOS tube is grounded;
the source electrode of the eighth PMOS tube is connected with a power supply VIN, and the grid electrode of the eighth PMOS tube is connected with an eighth control signal EN8;
the source electrode of the ninth PMOS tube is connected with the power VIN, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the tenth PMOS tube;
the first PMOS tube, the third PMOS tube, the sixth PMOS tube and the ninth PMOS tube form a current mirror of the mirror current IRT;
the grid electrode of the tenth PMOS tube is connected with a second control signal EN2;
the drain electrode of the eleventh PMOS tube is connected with the source electrode of the twelfth PMOS tube and the source electrode of the thirteenth PMOS tube;
the grid electrode of the twelfth PMOS tube is connected with the fourth control signal EN4, and the drain electrode of the twelfth PMOS tube is connected with the current IRT;
the grid electrode of the thirteenth PMOS tube is connected with a fifth control signal EN5, and the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the fourteenth NMOS tube;
the grid electrode of the first NMOS tube is connected with a second control signal EN2, and the source electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube;
the grid electrode of the second NMOS tube is connected with input bias current, and the source electrode of the second NMOS tube is grounded;
one end of the fifth capacitor is connected with the input bias current, and the other end of the fifth capacitor is grounded;
the grid electrode of the third NMOS tube is connected with input bias current, and the source electrode of the third NMOS tube is grounded;
the grid electrode of the fourth NMOS tube is connected with input bias current, the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the fifth NMOS tube;
the grid electrode of the fifth NMOS tube is connected with a first control signal EN1;
the grid electrode of the sixth NMOS tube is connected with the input bias current, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the seventh NMOS tube;
the drain electrode of the seventh NMOS tube is connected with the input bias current, and the grid electrode of the seventh NMOS tube is connected with a second control signal EN2;
the grid electrode of the eighth NMOS tube is connected with the input bias current, the source electrode of the eighth NMOS tube is grounded, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the ninth NMOS tube;
the drain electrode of the ninth NMOS tube is connected with the input bias current, and the grid electrode of the ninth NMOS tube is connected with the first control signal EN1;
the grid electrode of the tenth NMOS tube is connected with the input bias current, the source electrode of the tenth NMOS tube is grounded, and the drain electrode of the tenth NMOS tube is connected with the source electrode of the eleventh NMOS tube;
the grid electrode of the eleventh NNOS tube is connected with a third control signal EN3, and the drain electrode of the eleventh NNOS tube is connected with the source electrode of the twelfth NOMS tube;
the grid electrode of the twelfth NMOS tube is connected with the input bias current, and the drain electrode of the twelfth NMOS tube is connected with the current IRT;
the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the sixth NMOS tube, the eighth NMOS tube, the tenth NMOS tube and the twelve NMOS tubes form a current mirror for mirroring the input bias current;
the source electrode of the thirteenth NMOS tube is grounded, the grid electrode of the thirteenth NMOS tube is connected with a seventh control signal EN7, and the drain electrode of the thirteenth NMOS tube is connected with one end of the first resistor;
the other end of the first resistor is connected with a source electrode of the fourteenth NMOS tube;
the grid electrode of the fourteenth NMOS tube is connected with a sixth control signal EN6;
the first control signal EN1 and the second control signal EN2 are used for controlling switching between Burst mode and PWM mode, where Burst mode is used when EN1=0 and EN2=1, and PWM mode is used when EN1=1 and EN2= 0; the third control signal EN3 is used to control whether to use the internal current bias, which is used when EN3=1, and the external current bias is used when EN3= 0; the fourth control signal EN4 and the fifth control signal EN5 are used for controlling whether the oscillator current needs to be synchronized with the external, when EN4=1 and EN5=0, the external synchronization mode is selected, and when EN4=0 and EN5=1, the oscillator bias is realized for RT or the internal bias current; the sixth control signal EN6 is a charge pump output voltage, and is used to control the current of the oscillator during external synchronization, and the seventh control signal EN7 is used to enable the current of the oscillator to be externally synchronized and enabled when EN7= 1; the eighth control signal EN8 is used for IRT current sharing, enabled when EN8= 0.
The beneficial effects of the invention are as follows: according to the invention, the clamping circuit is added in the RT current distribution circuit, so that the oscillator can be ensured to normally work under the extreme condition that the RT resistance value of the external resistor is too high or too low, and the chip is prevented from being burnt out.
Drawings
FIG. 1 is a block diagram of an oscillator circuit comprising a clamped RT current generating circuit;
FIG. 2 is a graph of voltage waveforms at various points of the oscillator;
fig. 3 is a circuit diagram of an example of the RT current generating circuit with upper and lower limit clamps according to the present invention.
Detailed Description
The technical scheme of the invention is described in detail in the following with reference to the accompanying drawings and specific embodiments:
fig. 1 is a circuit block diagram of an oscillator composed of an RT current generating circuit with clamp, the oscillator is composed of capacitors C1 and C2, comparators COMP1 and COMP2, an RS trigger, and logic for switching a charging current path. The RT current generating circuit with the clamp is used for controlling a current source I RT When the oscillator starts to work, EN resets the RS comparator for an initial pulse, the current source I charges the capacitor C1, and when the voltage on the capacitor C1 exceeds the reference voltage V REF When the voltage on the capacitor C2 is greater than the reference voltage V, the comparator COMP1 is turned over, the RS trigger is turned over, the switch S1 is turned off, the charges on the capacitor C1 are discharged, the capacitor C2 is charged, and when the voltage on the capacitor C2 is greater than the reference voltage V REF And when the comparator COMP2 is turned over, the RS trigger is turned over, the switch S2 is closed, so that the PWM square wave with the duty ratio of 50% is realized, and the frequency of the PWM waveform is controlled by the magnitude of the charging current.
Fig. 2 is a graph of the voltage at point a, the voltage at point B and the output voltage waveform of the oscillator.
Fig. 3 is a circuit diagram of an example of a RT current generating circuit with clamp according to the present invention. The first PMOS tube, the third PMOS tube and the ninth PMOS tube form a mirror current I RT The current mirror of (1); the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the sixth NMOS tube, the eighth NMOS tube, the tenth NMOS tube and the twelve NMOS tubes form a current mirror for mirroring the input bias current I; the second PMOS tube, the fourth PMOS tube, the tenth PMOS tube, the first NMOS tube, the fifth NMOS tube, the seventh NMOS tube and the ninth NMOS tube are used for controlling the switching of Burst and PWM modes, wherein the Burst mode is performed when EN1=0 and EN2=1, and the Burst mode is performed when EN1=1 and EN2=The PWM mode is set at 0; the first capacitor and the second capacitor are used for comparing upper clamping current and lower clamping current; the capacitor C3 is used for filtering high-frequency burrs; the twelfth PMOS tube and the thirteenth PMOS tube are used for controlling whether the oscillator current needs to be synchronized with the outside, when EN4=1 and EN5=0, an external synchronization mode is selected, and when EN4=0 and EN5=1, the oscillator bias is realized for RT or an internal bias current; EN6 is a charge pump output voltage and is used for controlling the current of the oscillator during external synchronization; the eleventh NMOS transistor is used for controlling whether an internal bias current is adopted or not, when EN3=1, the oscillator is biased by the internal bias current, and when EN3=0, the oscillator is biased by the external bias current; the thirteenth NMOS tube is used for enabling the oscillator current to be externally synchronized, and is enabled when EN7= 1; the fifth PMOS tube and the eighth PMOS tube are used for I RT And the current distribution circuit is enabled when EN8=0, and the first resistor is used for limiting the magnitude of the oscillator current in the external synchronous mode.
When the bias current is too large, the voltage of the point L1 is increased, and the current of the MP11 is limited; when the bias current is too small, the voltage at the point L2 is reduced, the gate voltage of the MP7 is reduced, and the source stage pulls down the gate voltage of the MP9, so that the minimum bias current is limited. And L3 is connected with the current mirror at the later stage, and the output current of the current mirror is adjusted through the trim signal. Final output bias current I RT Sending the mixture into an oscillator.
From the specific implementation manner, the RT current generation circuit with the clamp provided by the invention limits the upper limit and the lower limit of the RT current based on comparison between the RT current and two fixed currents and feedback of voltages at two capacitor nodes to the grid of the current mirror, so that the size of the RT current is effectively controlled, and the oscillator is ensured to work in a normal frequency range.
Claims (1)
1. A clamped RT current generation circuit is used for a relaxation oscillator formed by utilizing RT current, and the relaxation oscillator formed by the RT current comprises a current source I RT The circuit comprises a first capacitor, a second capacitor, a first switch, a second switch, a first comparator, a second comparator, a first RS trigger and a first phase inverter;
one end of the first capacitor is connected with a current source I RT First, aOne end of the switch is connected with the non-inverting input end of the first comparator, and the other end of the first capacitor is connected with the other end of the first switch in a grounded mode;
one end of the second capacitor is connected with a current source I RT One end of the second switch and the non-inverting input end of the second comparator, and the other end of the second capacitor and the other end of the second switch are grounded;
the inverting input end of the first comparator is connected with reference voltage VREF, and the output end of the first comparator is connected with the R end of the first RS trigger;
the inverting input end of the first comparator is connected with the reference voltage VREF, and the output end of the first comparator is connected with the S end of the first RS trigger;
the enabling end of the first RS trigger is connected with an enabling signal EN, and the output end of the first RS trigger is connected with the input end of the first inverter and the control end of the first switch;
the output end of the first inverter is connected with the control end of the second switch and is used as a PWM output end at the same time;
wherein the clamped RT current generation circuit is used for controlling a current source I RT The voltage of the power supply comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a first resistor, a third capacitor, a fourth capacitor and a fifth capacitor;
the source electrode of the first PMOS tube is connected with a power supply VIN, the grid electrode of the first PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the third PMOS tube, the grid electrode of the sixth PMOS tube, the source electrode of the seventh PMOS tube, the grid electrode of the ninth PMOS tube, the drain electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube, and the drain electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube;
the grid electrode of the second PMOS tube is connected with a first control signal EN1;
the source electrode of the third PMOS tube is connected with a power VIN, and the drain electrode of the third PMOS tube is connected with the source electrode of the fourth PMOS tube;
the grid electrode of the fourth PMOS tube is connected with a second control signal EN2, and the drain electrode of the fourth PMOS tube is connected with one end of a third capacitor, the drain electrode of the fifth PMOS tube, the grid electrode of the eleventh PMOS tube and the drain electrode of the third NOMS tube;
the other end of the third capacitor is grounded;
the source electrode of the fifth PMOS tube is connected with a power supply VIN, and the grid electrode of the fifth PMOS tube is connected with an eighth control signal EN8;
a grid electrode of the sixth PMOS tube is connected with the power supply VIN, and a drain electrode of the sixth PMOS tube is connected with a grid electrode of the seventh PMOS tube, a drain electrode of the eighth PMOS tube, a drain electrode of the fifth NMOS tube and one end of the fourth capacitor;
the other end of the fourth capacitor is connected with a power supply VIN;
the drain electrode of the seventh PMOS tube is grounded;
the source electrode of the eighth PMOS tube is connected with a power supply VIN, and the grid electrode of the eighth PMOS tube is connected with an eighth control signal EN8;
the source electrode of the ninth PMOS tube is connected with the power VIN, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the tenth PMOS tube;
the first PMOS tube, the third PMOS tube, the sixth PMOS tube and the ninth PMOS tube form a mirror current I RT The current mirror of (1);
the grid electrode of the tenth PMOS tube is connected with a second control signal EN2;
the drain electrode of the eleventh PMOS tube is connected with the source electrode of the twelfth PMOS tube and the source electrode of the thirteenth PMOS tube;
the grid of the twelfth PMOS tube is connected with the fourth control signal EN4, and the drain thereof is connected with the current I RT ；
The grid electrode of the thirteenth PMOS tube is connected with the fifth control signal EN5, and the drain electrode of the thirteenth PMOS tube is connected with the drain electrode of the fourteenth NMOS tube;
the grid electrode of the first NMOS tube is connected with a second control signal EN2, and the source electrode of the first NMOS tube is connected with the drain electrode of the second PMOS tube;
the grid electrode of the second NMOS tube is connected with input bias current, and the source electrode of the second NMOS tube is grounded;
one end of the fifth capacitor is connected with the input bias current, and the other end of the fifth capacitor is grounded;
the grid electrode of the third NMOS tube is connected with input bias current, and the source electrode of the third NMOS tube is grounded;
the grid electrode of the fourth NMOS tube is connected with input bias current, the source electrode of the fourth NMOS tube is grounded, and the drain electrode of the fourth NMOS tube is connected with the source electrode of the fifth NMOS tube;
the grid electrode of the fifth NMOS tube is connected with a first control signal EN1;
the grid electrode of the sixth NMOS tube is connected with the input bias current, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the seventh NMOS tube;
the drain electrode of the seventh NMOS tube is connected with the input bias current, and the grid electrode of the seventh NMOS tube is connected with a second control signal EN2;
the grid electrode of the eighth NMOS tube is connected with the input bias current, the source electrode of the eighth NMOS tube is grounded, and the drain electrode of the eighth NMOS tube is connected with the source electrode of the ninth NMOS tube;
the drain electrode of the ninth NMOS tube is connected with the input bias current, and the grid electrode of the ninth NMOS tube is connected with the first control signal EN1;
the grid electrode of the tenth NMOS tube is connected with the input bias current, the source electrode of the tenth NMOS tube is grounded, and the drain electrode of the tenth NMOS tube is connected with the source electrode of the eleventh NMOS tube;
the grid electrode of the eleventh NNOS tube is connected with the third control signal EN3, and the drain electrode of the eleventh NNOS tube is connected with the source electrode of the twelfth NOMS tube;
the gate of the twelfth NMOS transistor is connected with an input bias current, and the drain thereof is connected with a current I RT ；
The second NMOS tube, the third NMOS tube, the fourth NMOS tube, the sixth NMOS tube, the eighth NMOS tube, the tenth NMOS tube and the twelve NMOS tubes form a current mirror for mirroring the input bias current;
the source electrode of the thirteenth NMOS tube is grounded, the grid electrode of the thirteenth NMOS tube is connected with the seventh control signal EN7, and the drain electrode of the thirteenth NMOS tube is connected with one end of the first resistor;
the other end of the first resistor is connected with the source electrode of the fourteenth NMOS tube;
the grid electrode of the fourteenth NMOS tube is connected with a sixth control signal EN6;
the first control signal EN1 and the second control signal EN2 are used for controlling switching between Burst mode and PWM mode, where Burst mode is used when EN1=0 and EN2=1, and PWM mode is used when EN1=1 and EN2= 0; the third control signal EN3 is used to control whether to use the internal current bias, which is used when EN3=1, and the external current bias is used when EN3= 0; the fourth control signal EN4 and the fifth control signal EN5 are used for controlling whether the oscillator current needs to be synchronized with the external, when EN4=1 and EN5=0, the external synchronization mode is selected, and when EN4=0 and EN5=1, the oscillator bias is realized for RT or the internal bias currentPlacing; the sixth control signal EN6 is a charge pump output voltage and is used for controlling the current of the oscillator during external synchronization; the seventh control signal EN7 is used to enable oscillator current external synchronization, enabled when EN7= 1; the eighth control signal EN8 is for I RT Current sharing, enabled when EN8= 0.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310182214.4A CN115987078A (en) | 2023-02-28 | 2023-02-28 | RT current generation circuit with clamping |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310182214.4A CN115987078A (en) | 2023-02-28 | 2023-02-28 | RT current generation circuit with clamping |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115987078A true CN115987078A (en) | 2023-04-18 |
Family
ID=85970497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310182214.4A Pending CN115987078A (en) | 2023-02-28 | 2023-02-28 | RT current generation circuit with clamping |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115987078A (en) |
-
2023
- 2023-02-28 CN CN202310182214.4A patent/CN115987078A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106357110B (en) | A kind of BUCK constant voltage drive circuits and BUCK constant-voltage drivers | |
| WO2015196861A1 (en) | Circuit for switching power supply with inductor | |
| CN108809071B (en) | Soft start control circuit of switching power supply and switching power supply | |
| CN112510983B (en) | Short-circuit protection circuit, chip and system for switching power supply | |
| WO2022142625A1 (en) | Oscillator for switching converter, and switching converter | |
| CN104638917B (en) | Control circuit for switching converter | |
| CN112737335B (en) | Zero-crossing detection device of boost conversion circuit | |
| CN110518800B (en) | Flyback converter and control method thereof | |
| CN112104203B (en) | Switch current-limiting circuit and power chip | |
| CN114421766A (en) | High-precision oscillator circuit applied to switching power supply and having jitter frequency and slope compensation functions | |
| CN115173686B (en) | Circuit structure for reducing output voltage ripple | |
| TW201143265A (en) | A heterodyne dual slope frequency generation method for the load change of power supply | |
| CN108988616B (en) | Ripple generation circuit, control circuit and switching converter | |
| CN117353431B (en) | Circuit structure with adjustable duty ratio | |
| CN113193540A (en) | Control circuit, control circuit system and power supply chip | |
| CN112117899A (en) | BOOST converter controlled by current mode | |
| CN219329698U (en) | Half-bridge driving circuit, half-bridge converter, circuit board and electronic equipment | |
| CN115102384B (en) | Soft start control circuit, control method thereof and power supply circuit | |
| CN115987078A (en) | RT current generation circuit with clamping | |
| CN107546982B (en) | PWM/PFM dual-mode control circuit | |
| CN215072203U (en) | Soft start circuit and motor | |
| CN211701851U (en) | Switch power supply | |
| CN113037070B (en) | Fast starting circuit of switching power supply | |
| CN210864451U (en) | DC-DC converter | |
| CN108429464B (en) | Power supply system with stable loop |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |