CN115985225A - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN115985225A CN115985225A CN202211517704.7A CN202211517704A CN115985225A CN 115985225 A CN115985225 A CN 115985225A CN 202211517704 A CN202211517704 A CN 202211517704A CN 115985225 A CN115985225 A CN 115985225A
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Abstract
The application discloses a display panel and a display device, wherein the display panel comprises a pixel circuit and a light-emitting element, the pixel circuit is used for providing a driving current for the light-emitting element; the frame refresh frequency of the pixel circuits located in the first display area is F1, and the frame refresh frequency of the pixel circuits located in the second display area is F2, where F1> F2. According to the display device and the display method, the display power consumption can be reduced when the display panel is at a higher refreshing frequency.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to a display panel and a display device.
Background
With the development of technology, the demand for display panels is also gradually increasing. To increase the visual fluency for users, panels have emerged that support high refresh rates, such as 90HZ, 120HZ, and so on. With the application of high frequency display technology, the power consumption of the display panel is inevitably increased significantly.
Disclosure of Invention
The embodiment of the application provides a display panel and a display device, which can reduce the power consumption of the display panel when the display panel is at a higher refreshing frequency.
In one aspect, there is provided a display panel, which may include:
the pixel circuit is used for providing a driving current for the light-emitting element;
the frame refresh frequency of the pixel circuits located in the first display area is F1, the frame refresh frequency of the pixel circuits located in the second display area is F2,
wherein F1> F2.
Optionally, the pixel circuit comprises a driving transistor, a gate of which is connected to the source driving circuit;
the frame includes a data write frame or a hold frame; in a data writing frame, the source electrode driving circuit writes a data signal into the grid electrode of the driving transistor; in the holding frame, the source driving circuit does not write the data signal to the gate of the driving transistor;
a data refresh cycle of the display panel comprises a first data refresh cycle corresponding to the first display area and a second data refresh cycle corresponding to the second display area;
m1 data writing frames and r1 maintaining frames are included in a first data refreshing period corresponding to the first display area;
m2 data writing frames and r2 maintaining frames are included in a second data refreshing period corresponding to the second display area;
wherein m1+ r1= m2+ r2, and m1> m2>0, r2> r1 ≧ 0.
Optionally, n data refreshing sub-periods are sequentially arranged in the second data refreshing period corresponding to the second display area, the data refreshing sub-period comprises m3 data writing frames and r3 maintaining frames,
wherein m2= n m3, r2= n r3, n ≧ 2.
Optionally, a data writing phase and a holding phase are sequentially arranged in a second data refreshing cycle corresponding to the second display area,
the data write phase includes m2 data write frames and the hold phase includes r2 hold frames.
Optionally, the display panel further comprises:
the input end of the first switch is electrically connected with the source electrode driving circuit, and the output end of the second switch is electrically connected with the grid electrode of the driving transistor;
the input end of the second switch is connected with the high-resistance signal, and the output end of the second switch is electrically connected with the grid electrode of the driving transistor;
when the pixel circuit works in a data writing frame, the control end of the first switch is connected with an effective signal, and the control end of the second switch is connected with a non-effective signal;
when the pixel circuit works in a holding frame, the control end of the first switch is connected with a non-effective signal, and the control end of the second switch is connected with an effective signal;
preferably, the high impedance signal is replaced with a VGMP signal or a VGSP signal.
Optionally, the display panel further comprises:
a gate driving circuit for providing a scanning signal to the pixel circuit;
the first type clock signal line is used for providing a first type clock signal for the grid driving circuit;
when the pixel circuit works in a holding frame, the first type clock signal is a first level signal.
Optionally, the first type of clock signal line includes a first clock signal line and a second clock signal line,
when the pixel circuit works in a data writing frame, the output time sequence of the first clock signal line is opposite to the electric potential of at least part of the output time sequence of the second clock signal line;
when the pixel circuit works in a holding frame, the first level signals output by the first clock signal line and the second clock signal line are high level signals.
Optionally, the display panel further comprises:
a light emission driving circuit for providing a light emission control signal to the pixel circuit;
the second type clock signal line is used for providing a second type clock signal for the light-emitting driving circuit;
when the pixel circuit works in the holding frame, the second type clock signal is a second level signal.
Optionally, the second type of clock signal line comprises a third clock signal line and a fourth clock signal line,
when the pixel circuit works in a data writing frame, the output time sequence of the third clock signal line and the output time sequence of the fourth clock signal line are opposite in potential of at least part of time sequences;
when the pixel circuit works in a holding frame, the second level signals output by the third clock signal line and the fourth clock signal line are both low level signals.
In another aspect, a display device is also provided, which may include the display panel of the above aspect.
Compared with the prior art, the display panel and the display device provided by the embodiment of the application are provided with the pixel circuit and the light-emitting element, wherein the pixel circuit is used for providing the driving current for the light-emitting element. The frame refresh frequency of the pixel circuits located in the first display region is F1, the frame refresh frequency of the pixel circuits located in the second display region is F2, and F1> F2. Therefore, when the display panel displays, the frame refresh frequency of the pixel circuits in different display areas is designed differently, so that the first display area can realize high refresh rate, and the second display area adopts lower frame refresh rate, thereby ensuring that the display panel is at higher refresh rate and reducing display power consumption.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of an alternative circuit structure of a pixel circuit and a light-emitting element according to a display panel of an embodiment of the present application.
Fig. 2 is a schematic diagram of an alternative arrangement of display regions according to the display panel of the embodiment of the present application.
Fig. 3 is a schematic diagram illustrating setting of frame refresh frequency of pixel circuits in different display areas according to an embodiment of the present application.
FIG. 4 is a schematic diagram illustrating an alternative timing sequence within a data refresh period of a display panel according to an embodiment of the present application.
FIG. 5 is a schematic diagram illustrating another alternative timing sequence within a data refresh period of a display panel according to an embodiment of the present application.
FIG. 6 is a schematic diagram illustrating an alternative timing sequence within a data refresh period of a display panel according to an embodiment of the present application.
FIG. 7 is a schematic diagram illustrating another alternative timing sequence within a data refresh period of a display panel according to an embodiment of the present application.
FIG. 8 is a frame number comparison table of data write frames in the first display area and the second display area when the frame refresh frequency of the first display area in the display panel of the embodiment of the present application is 60 Hz.
Fig. 9 is a schematic diagram of a driving architecture of a source driving circuit in a display panel according to an embodiment of the present application.
Fig. 10 is a schematic diagram of another driving structure of the source driving circuit in the display panel according to the embodiment of the present application.
Fig. 11 is a schematic circuit structure diagram of a cascade connection of a plurality of gate driving circuits in a display panel according to an embodiment of the present application.
Fig. 12 is a schematic diagram of an alternative circuit structure of a single gate driving circuit in a display panel according to an embodiment of the present application.
Fig. 13 is an alternative driving timing diagram of a gate driving circuit in a display panel according to an embodiment of the present application.
Fig. 14 is a schematic circuit structure diagram of a cascade connection of a plurality of light emitting driving circuits in the display panel according to the embodiment of the present application.
Fig. 15 is a schematic diagram of an alternative circuit structure of a single light emitting driving circuit in a display panel according to an embodiment of the present disclosure.
Fig. 16 is an alternative driving timing diagram of the light emission driving circuit in the display panel according to the embodiment of the present application.
Description of the drawings:
the liquid crystal display device includes a pixel circuit 10, a threshold compensation module 11, a first initialization module 12, a light emitting element 20, a data refresh period T1, a data refresh sub-period T2, a data write period T3, a hold period T4, a first switch K1, a second switch K2, a third switch K3, a driving transistor M5, a gate driving circuit VSR1, a light emission driving circuit VSR2, a data signal Vdata, a scanning signal line SCAN, a light emission control signal line EM, a first kind of clock signal line SCK, a first clock signal line SCK1, a second clock signal line SCK2, a second kind of clock signal line ECK, a third clock signal line ECK1, a fourth clock signal line ECK2, a frame F, a high resistance signal NC, and a digital-to analog conversion unit DAC.
Detailed Description
Features of various aspects of the present application and exemplary embodiments will be described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It should be noted that, in the present application, the embodiments and features of the embodiments may be combined with each other without conflict. The embodiments will be described in detail below with reference to the accompanying drawings.
The display panel in the related art generally supports a low refresh rate, but a display picture with the low refresh rate can only support normal video and application display, and the problems of unsmooth video image quality, poor visual experience and the like exist. With the development of display technology, in order to meet the demand of users for better video display effect, electronic devices such as computers and mobile phones gradually support high refresh rate. At high refresh rates, the display panel can display high definition movie video and gaming applications. The use of high refresh rates necessarily results in a significant increase in power consumption of the display panel.
In order to solve the above technical problem, embodiments of the present application provide a display panel and a display device, and the display panel of the embodiments of the present application is first described with reference to the accompanying drawings.
Referring to fig. 1 to 3, in an alternative example of the display panel of the embodiment of the present application, the display panel may include a pixel circuit 10 and a light emitting element 20.
It should be noted that the display panel may further include a plurality of pixel units (not shown) arranged in an array, and the pixel circuit 10 and the light emitting element 20 may be disposed in the pixel units.
The Light emitting element 20 may be a Light-emitting diode (LED), an Organic Light Emitting Diode (OLED), or the like.
The pixel circuit 10 can be used to provide a driving current for the light emitting element 20, and the pixel circuit 10 can be a 7T1C circuit, an 8T2C circuit, a 9T2C circuit, etc., and can be even a basic 2T1C circuit. Referring to fig. 1, fig. 1 shows an alternative circuit structure diagram of a pixel circuit 10 and a light emitting element 20 according to the present application, in which the threshold compensation module 11 in the pixel circuit 10 may be composed of two thin film transistors M2 and M8, and the first initialization module 12 for initializing the gate of the driving transistor M5 may be composed of two thin film transistors M4 and M6.
The display panel may include at least two display regions, which in some alternative examples, referring to fig. 2, may include a first display region and a second display region. Illustratively, the first display region and the second display region may extend in a row direction, and may be sequentially arranged in a column direction.
For example, when the display panel is a flexible display screen (e.g., a folded OLED screen), the intersection of the first display region and the second display region may be bent in some cases.
Please refer to fig. 1 to fig. 3, wherein the frame refresh frequency of the pixel circuit 10 in the first display area is F1, and the frame refresh frequency of the pixel circuit 10 in the second display area is F2, where F1> F2.
The frame in the frame refresh frequency is calculated with a minimum period of one light emitting period. By correspondingly setting frame refreshing frequencies with different sizes in different display areas of the display panel, when the display panel displays the same image picture, a picture with higher definition requirement is displayed on one partial image picture, and a picture with lower definition requirement is displayed on the other partial image picture, so that the power consumption of the display panel is reduced.
For example, the display panel may be a folding screen, a high-refresh dynamic display scene such as a game may be displayed in a folding area a (i.e., a first display area) on one side of the folding screen, and a static picture with a low frame refresh frequency, such as a keyboard operation picture, may be displayed in a folding area B (i.e., a second display area) on the other side of the folding screen.
The display device in this embodiment is provided with a pixel circuit 10 and a light emitting element 20, wherein the pixel circuit 10 is configured to supply a drive current to the light emitting element 20. The frame refresh frequency of the pixel circuits 10 located in the first display area is F1, the frame refresh frequency of the pixel circuits 10 located in the second display area is F2, and F1> F2. Therefore, when the display panel displays, the frame refresh frequency of the pixel circuits 10 in different display areas is designed differently, so that the high refresh rate can be realized in the first display area, and meanwhile, the lower frame refresh rate is adopted in the second display area, so that the display power consumption is reduced while the display panel is ensured to be at the higher refresh rate.
In some alternative examples, referring to fig. 4 to 5 and fig. 1 to 3, the pixel circuit 10 may include a driving transistor M5, and a gate of the driving transistor M5 is connected to a source driving circuit (not shown). Illustratively, the driving transistor M5 may be connected to a data signal line, and the source driving circuit may supply a data signal Vdata to each pixel circuit 10 via the data signal line.
Further, the frame F referred to by the above-described minimum period of one lighting phase may include a data write frame and/or a hold frame. In a data writing frame, the source driving circuit may write a data signal Vdata to the gate of the driving transistor M5 through the data signal line, and at this time, the driving transistor M5, the threshold compensation module 11, and the like may be turned on; in the sustain frame, the source driving circuit may not write the data signal Vdata to the gate of the driving transistor M5.
A data refresh period T1 of the display panel comprises a first data refresh period corresponding to the first display area and a second data refresh period corresponding to the second display area.
Wherein m1 data write frames and r1 hold frames may be included in the first data refresh period. M2 data write frames and r2 hold frames may be included in the second data refresh period, m1+ r1= m2+ r2, and m1> m2>0, r2> r1 ≧ 0.
The data refresh in the data refresh period T1 is calculated as a minimum period of the write data signal Vdata. When actually displayed, the partial picture of the first display area and the partial picture of the second display area constitute a complete one-frame image picture, so that when data writing corresponding to the image picture is performed, the total number of data frames F in the first display area and the second display area is consistent, that is, m1+ r1= m2+ r2. In order to realize a relatively low frame refresh frequency of the second display region and a relatively high frame refresh frequency of the first display region, relatively more retention frames, i.e., r2> r1, may be set in the second display region, so that the data signal Vdata is relatively less written in the second data refresh period corresponding to the second display region, thereby enabling the display panel to reduce the display power consumption while supporting a high refresh rate.
For example, referring to fig. 4, and referring to fig. 1 to 3 together, only the data write frame, i.e., r1=0, may be set in the first data refresh period, and the pixel circuits 10 of the first display area are in the data write frame regardless of whether the pixel circuits 10 of the second display area are operated in the data write frame or the hold frame. So set up, can furthest promote the display effect in first display area, promote display panel's high definition and experience.
For example, referring to fig. 5 together with fig. 1 to 3, only one data write frame may be set in the second data refresh period, and the rest is a holding frame, that is, m2=1, thereby reducing the display power consumption of the second display region as much as possible.
It should be further noted that the working order of the data writing frame and the holding frame in one data refreshing period T1 of a single display area may be arranged according to actual needs.
In some alternative examples, with continuing reference to fig. 6 and with further reference to fig. 1-5, n data refresh sub-periods T2 may be sequentially arranged within the second data refresh period corresponding to the second display region, where the data refresh sub-period T2 includes m3 data write frames and r3 hold frames, where m2= n × m3, r2= n × r3, and n ≧ 2.
In this example, a single second data refresh period in the second display region is further divided into a plurality of data refresh sub-periods T2, and each data refresh sub-period T2 further includes a plurality of data write frames and a plurality of hold frames, so that in the second data refresh period, the data write frames and the hold frames are alternately present, so that the on-off states of the transistors in the pixel circuit 10 can be changed at certain intervals, the stability of the display effect is maintained, and at the same time, a high refresh rate picture can be displayed, and the power consumption is reduced.
To illustrate with a frame refresh frequency of 60Hz for the display panel, 60 data frames F may be included in a single data refresh period in the second display region. A second data refresh period of the pixel circuits 10 located in the second display region may include 10 data refresh sub-periods T2, i.e., n =10. Then m3 may be set to 1, r3 may be set to 5, and the pixel circuit 10 in the second display region may operate after one frame data writing frame in one data refreshing sub-period T2, and then no data signal Vdata is written in 5 retention frames, and then continue to enter a new data refreshing sub-period T2, and continue to write one frame data signal Vdata, and then no data signal Vdata is written in 5 retention frames, and is in a retention state.
Still continuing with the above example, if the first data refresh period does not include a retention frame, the pixel circuits 10 of the first display area operate once in the data write frame every time a 6-frame data write frame is refreshed.
In other alternative examples, referring to fig. 7 and referring to fig. 1 to 6 together, the second data refresh cycle includes a data write phase T3 and a hold phase T4, which are sequentially arranged. The data writing phase T3 includes m2 data writing frames, and the holding phase T4 includes r2 holding frames. By sequentially setting the data writing stage T3 and the holding stage T4 in a single period, the pixel circuit 10 operates in different frame stages, so that the frame refresh frequency of the second display area is reduced, and the power consumption of the display panel is reduced.
In this refresh mode, when the pixel circuit 10 in the second display region operates, the data write frame and the retention frame do not appear alternately, but the pixel circuit operates in the data write frame in the second data refresh period to write the data signal Vdata, and the data signal Vdata is continuously retained in 50 retention frames until 10 data write frames are refreshed, and the data signal Vdata is not written.
If the first data refresh period does not include the retention frame, that is, m1=60, and r1=0, the pixel circuits 10 of the first display region and the pixel circuits 10 of the second display region may sequentially refresh 10 data write frames in the data refresh period T1, and then the pixel circuits 10 of the first display region continue to write the data signal Vdata, while the pixel circuits 10 of the second display region are in the retention phase T4, and only retain the data signal Vdata.
It should be noted that, referring to fig. 8 and fig. 1 to 7 together, where fig. 8 shows the number of data write frames when the pixel circuits 10 of the first display area and the second display area operate, and the frame refresh frequency of the second display area is obtained by calculation correspondingly, taking the frame refresh frequency of the display panel and the frame refresh frequency of the first display area as an example of 60 Hz.
The ratio between the frame refresh frequency of the pixel circuits 10 in the first display area and the frame refresh frequency of the pixel circuits 10 in the second display area may be an integer or a non-integer. And the larger the ratio is, the lower the frame refreshing frequency of the second display area is, and the effect of reducing power consumption is more obvious.
The number of data writing frames in the first data refreshing period and the second data refreshing period can also be set according to actual needs, but m1+ r1= m2+ r2, m1> m2>0, and r2> r1 ≧ 0 still need to be satisfied overall.
In still other alternative examples, please refer to fig. 1 to 9 together, in which the display panel may further include a first switch K1 and a second switch K2. The first switch K1 and the second switch K2 may be thin film transistors.
The input end of the first switch K1 may be electrically connected to the source driving circuit, and the output end of the first switch K1 is electrically connected to the gate of the driving transistor M5. An input end of the second switch K2 may be connected to the high-resistance signal NC, and an output end of the second switch K2 may be electrically connected to the gate of the driving transistor M5.
When the pixel circuit 10 operates in a data write frame, the control terminal of the first switch K1 is connected to an active signal, and the control terminal of the second switch K2 is connected to a non-active signal. When the pixel circuit 10 works in the hold frame, the control terminal of the first switch K1 is connected to the inactive signal, and the control terminal of the second switch K2 is connected to the active signal.
Alternatively, the input end of the first switch K1 may also be connected to a digital-to-analog conversion unit DAC in the source driving circuit, and the output end of the first switch K1 may pass through a buffer, for example, the buffer may be a signal amplifier, and finally access the gate of the driving transistor M5 through a data signal line.
In this example, the original driving architecture is optimized, and the first switch K1 and the second switch K2 are added, so that whether the gate of the driving transistor M5 in the pixel circuit 10 is connected to the data signal Vdata can be controlled by the control signal connected by the first switch K1 and the second switch K2, and an optional implementation scheme is provided for inter-frame switching of the data frame.
The types of the first switch K1 and the second switch K2 may be different, and for example, the first switch K1 may be an N-type thin film transistor, and the second switch K2 may be a P-type thin film transistor. The input end of the first switch K1 may be connected to a high impedance signal, or may also be connected to a VGMP (peak voltage output by the gamma power supply) signal or a VGSP (valley voltage output by the gamma power supply) signal, and referring to fig. 10, three third switches K3 may be further provided, and by outputting an effective signal to the control end of any third switch K3, the input end of the first switch K1 may be selectively controlled to be connected to different signals, thereby maintaining the pixel circuit 10 in the hold state.
The data refresh is performed in the order of the first display area and the second display area. When the pixel circuits 10 in the first display area and the second display area need to write data, the display area of the display panel can realize normal refreshing display on a full screen, that is, the pixel circuits 10 in the first display area and the second display area sequentially write data, at this time, the control end of the first switch K1 is connected to an effective signal, the first switch K1 maintains a conducting state, the control end of the second switch K2 is connected to a non-effective signal, and the second switch K2 is switched off.
When the pixel circuit 10 in the first display area operates in a data writing frame, the control terminal of the first switch K1 is connected to the valid signal, the first switch K1 is turned on, and the second switch K2 is turned off. When the pixel circuit 10 in the first display area or the second display area works in the hold frame, the control end of the second switch K2 is connected to the effective signal, the second switch K2 is turned on, and the first switch K1 is turned off.
In this example, by additionally providing the first switch K1 and the second switch K2, the data signal Vdata is no longer continuously connected into the display region, data writing is performed at certain intervals while maintaining frames, an optional implementation scheme is provided for implementing different frame refresh frequencies in different display regions, and data writing is not performed in real time, so that the driving power consumption of the source driving circuit is reduced.
In still other alternative examples, referring to fig. 11, 12 and 13, and referring to fig. 1 to 10 together, the display panel may further include a gate driving circuit VSR1 and a first type clock signal line SCK.
The gate driving circuit VSR1 may be used to provide the pixel circuit 10 with the SCAN signal SCAN. The first type clock signal line SCK may be used to provide the first type clock signal to the gate driving circuit VSR 1. When the pixel circuit 10 operates in the hold frame, the first type clock signal is a first level signal.
The first level signal is a fixed level signal, and may be, for example, a steady high level signal or a steady low level signal. When the pixel circuit 10 of the first display region or the second display region is in a hold frame in which writing of the data signal Vdata is stopped, the first type of clock signal supplied to the gate driving circuit VSR1 is set to a fixed level state at this time, so that the gate driving circuit VSR1 stops outputting the SCAN signal SCAN in the hold frame, the gate driving power consumption of the corresponding display region in the hold frame can be reduced, and the power consumption of the display panel is further reduced on the basis of reducing the display power consumption by the frame refresh frequency.
It should be noted that, when the data signal Vdata is normally written into the driving transistor M5 of the pixel circuit 10, the SCAN signal SCAN needs to be switched to different output states, so that when the first-type clock signal line SCK is set, the first-type clock signal line SCK may include the first clock signal line SCK1 and the second clock signal line SCK2.
When the pixel circuit 10 operates in a data write frame, the output timing of the first clock signal line SCK1 is opposite to the potential of at least a part of the output timing of the second clock signal line SCK2. For example, please refer to fig. 12 and 13, wherein in the control output phase of the SCANm in fig. 13, the partial output timing potentials of the first clock signal line SCK1 and the second clock signal line SCK2 are opposite, so as to ensure the stable output of the gate driver when the pixel circuit 10 operates in the data writing frame.
When the pixel circuit 10 is operated to maintain a frame, the first clock signal output from the first clock signal line SCK1 and the second clock signal line SCK2 may be a high level signal.
Taking fig. 11 to 13 as an example, the description is made with reference to fig. 1 to 10, where fig. 11 shows an optional structure schematic diagram of a cascade connection of a plurality of gate driving circuits VSR1, fig. 12 shows an optional circuit structure schematic diagram of a single gate driving circuit VSR1, fig. 13 shows an output timing of a scan signal line SCANm closest to the second display region in the first display region and a scan signal line SCANm +1 closest to the first display region in the second display region when the first display region and the second display region are sequentially arranged in a column direction, and output timing schematic diagrams of a first clock signal line SCK1 and a second clock signal line SCK2 that send control signals to the gate driving circuits VSR 1.
It can be seen that the scanning signal lines in the 1 st to m th rows are arranged in the projection range of the first display area, and the scanning signal lines in the m +1 th row are arranged in the projection range of the second display area. When the pixel circuits 10 in the first display area all work in a data writing frame, frame refreshing can be performed in the order from top to bottom, and at this time, the gate driving circuit VSR1 can normally receive the first type of clock signals output by the first clock signal line SCK1 and the second clock signal line SCK2, thereby implementing gate driving control. When the row m +1 is reached, the switching between the high and low potentials of the first clock signal line SCK1 and the second clock signal line SCK2 is stopped, and the fixed level state is maintained, so that the SCAN signal SCAN is not output to the pixel circuit 10 after the row m, and the row close state is maintained, therefore, the second display area after the row m cannot perform data refreshing, and still maintains the image picture of the previous frame.
In these examples, by providing the first clock signal line SCK1 and the second clock signal line SCK2, the pixel circuit 10 is made to operate at the time of data writing frame, and normal gate drive control can be achieved. When the pixel circuit 10 operates in the hold frame, the first type clock signal output from the first clock signal line SCK1 and the second clock signal line SCK2 is maintained in a fixed level state, for example, a high level state, whereby power consumption of the gate control circuit can be reduced.
In still other alternative examples, referring to fig. 14 to 16 and referring to fig. 1 to 13, the display panel may further include a light emitting driving circuit VSR2 and a second type clock signal line ECK.
Among them, the light emission driving circuit VSR2 may be used to supply the pixel circuit 10 with the light emission control signal EM. The second type clock signal line ECK may be used to provide the second type clock signal to the light-emitting driving circuit VSR 2. The second type clock signal is a second level signal when the pixel circuit 10 operates in the hold frame.
It should be noted that the light-emitting driving circuit VSR2 may provide the light-emitting control signal EM to the pixel circuit 10 via the light-emitting control signal line, so that the light-emitting element 20 selectively enters a light-emitting stage. The second level signal may or may not coincide with the first level signal. The second level signal may also be a fixed level signal, for example, a steady low level signal or a steady high level signal.
When the pixel circuit 10 in the first display region or the second display region is in a hold frame in which writing of the data signal Vdata is stopped, the second type of clock signal supplied to the light-emission driving circuit VSR2 at this time is set to a fixed level state, so that the light-emission driving circuit VSR2 stops outputting the light-emission control signal EM in the hold frame, the light-emission control power consumption of the corresponding display region in the hold frame can be reduced, and the power consumption of the display panel can be further reduced on the basis of reducing the display power consumption by the frame refresh frequency.
It should be noted that, when the data signal Vdata is normally written into the driving transistor M5 of the pixel circuit 10, the emission control signal EM needs to be switched to different states, so that when the second type clock signal line ECK is set, the second type clock signal line ECK may include the third clock signal line ECK1 and the fourth clock signal line ECK2.
When the pixel circuit 10 operates in a data write frame, at least a part of the output timings of the third clock signal line ECK1 and the fourth clock signal line ECK2 are opposite in potential. For example, please refer to fig. 16, wherein in the control output stage of EMm in fig. 16, the partial output timing potentials of the third clock signal line ECK1 and the fourth clock signal line ECK2 are opposite, thereby ensuring stable output of the emission control signal EM when the pixel circuit 10 operates in the data write frame.
When the pixel circuit 10 is operated in the hold frame, the second type of clock signals output from the third clock signal line ECK1 and the fourth clock signal line ECK2 may be both second level signals, for example, the second level signals may be both low level signals.
Fig. 14 to 16, which is taken in conjunction with fig. 1 to 13 for illustration, are respectively a schematic diagram of an alternative circuit structure of a cascade connection of a plurality of light-emitting driving circuits VSR2 in fig. 14, a schematic diagram of an alternative circuit structure of a single light-emitting driving circuit VSR2 in fig. 15, a schematic diagram of an output timing of a light-emitting control signal line EMm closest to the second display region in the first display region and a light-emitting control signal line EMm +1 closest to the first display region in the second display region when the first display region and the second display region are sequentially arranged in the column direction, and a schematic diagram of an output timing of a third clock signal line ECK1 and a fourth clock signal line ECK2 which send control signals to the light-emitting driving circuit VSR2 at this time.
It can be seen that the light-emitting control signal lines in the 1 st row to the mth row are arranged in the projection range of the first display area, and the light-emitting control signal lines in the m +1 th row are arranged in the projection range of the second display area. When the pixel circuits 10 in the first display area are all operated in the data writing frame, frame refreshing may be performed in the order from top to bottom, and at this time, the light-emitting driving circuit VSR2 may normally receive the second type of clock signals output by the third clock signal line ECK1 and the fourth clock signal line ECK2, so as to implement light-emitting driving control. When the display is executed to the (m + 1) th row, the switching of the high and low potentials of the third clock signal line ECK1 and the fourth clock signal line ECK2 is stopped, and the fixed level state is maintained, so that the light-emitting control signal EM is not output to the pixel circuit 10 after the m-th row, and the row closing state is maintained, therefore, the second display area after the m-th row can not perform data refreshing, and still maintains the image picture of the previous frame.
In these examples, by providing the third clock signal line ECK1 and the fourth clock signal line ECK2, the pixel circuit 10 is operated at the time of data write frame, and normal light emission drive control can be realized. When the pixel circuit 10 operates in the hold frame, the power consumption of the light-emitting gate control circuit can be reduced by maintaining the second type of clock signal output from the third clock signal line ECK1 and the fourth clock signal line ECK2 in a fixed level state, for example, in a high level state or a low level state.
The display panel according to the embodiment of the present invention is described in detail above with reference to fig. 1 to 16. On this basis, this application embodiment also protects a display device, and this display device can be at least one in wearable equipment, camera, cell-phone, panel computer, display screen, TV set and on-vehicle display terminal. The display device comprises the display panel provided by the embodiment, so that the display device has all the beneficial effects of the display panel.
In addition, the term "and/or" herein is only one kind of association relationship describing an associated object, and means that there may be three kinds of relationships, for example, a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
It should be understood that in the embodiment of the present application, "B corresponding to a" means that B is associated with a, from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.
While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A display panel, comprising:
the pixel circuit is used for providing a driving current for the light-emitting element;
the frame refresh frequency of the pixel circuits located in the first display area is F1, the frame refresh frequency of the pixel circuits located in the second display area is F2,
wherein F1> F2.
2. The display panel according to claim 1, wherein the pixel circuit includes a driving transistor whose gate is connected to a source driving circuit;
the frame includes a data write frame or a hold frame; in the data writing frame, the source driving circuit writes a data signal to the gate of the driving transistor; in the holding frame, the source drive circuit does not write a data signal to the gate of the drive transistor;
a data refresh cycle of the display panel comprises a first data refresh cycle corresponding to the first display area and a second data refresh cycle corresponding to the second display area;
m1 data writing frames and r1 holding frames are included in a first data refreshing period corresponding to the first display area;
m2 data writing frames and r2 maintaining frames are included in a second data refreshing period corresponding to the second display area;
wherein m1+ r1= m2+ r2, and m1> m2>0, r2> r1 ≧ 0.
3. The display panel according to claim 2, wherein the second data refresh period corresponding to the second display region comprises n data refresh sub-periods arranged in sequence, the data refresh sub-periods comprise m3 data write frames and r3 hold frames,
wherein m2= n m3, r2= n r3, n ≧ 2.
4. The display panel according to claim 2, wherein the second data refresh period corresponding to the second display region comprises a data writing phase and a holding phase sequentially arranged,
the data writing phase includes m2 of the data writing frames, and the holding phase includes r2 of the holding frames.
5. The display panel according to claim 2, characterized in that the display panel further comprises:
the input end of the first switch is electrically connected with the source electrode driving circuit, and the output end of the first switch is electrically connected with the grid electrode of the driving transistor;
the input end of the second switch is connected with a high-resistance signal, and the output end of the second switch is electrically connected with the grid electrode of the driving transistor;
when the pixel circuit works in the data writing frame, the control end of the first switch is connected with an effective signal, and the control end of the second switch is connected with a non-effective signal;
when the pixel circuit works in the holding frame, the control end of the first switch is connected with a non-effective signal, and the control end of the second switch is connected with an effective signal;
preferably, the high impedance signal is replaced with a VGMP signal or a VGSP signal.
6. The display panel according to claim 1, characterized in that the display panel further comprises:
a gate driving circuit for providing a scanning signal to the pixel circuit;
the first type clock signal line is used for providing a first type clock signal for the grid driving circuit;
when the pixel circuit works in the holding frame, the first type clock signal is a first level signal.
7. The display panel according to claim 6, wherein the first clock signal line includes a first clock signal line and a second clock signal line,
when the pixel circuit operates in the data writing frame, the output timing of the first clock signal line is opposite to the potential of at least part of the output timing of the second clock signal line;
when the pixel circuit works in the holding frame, the first level signals output by the first clock signal line and the second clock signal line are high level signals.
8. The display panel according to claim 1, characterized in that the display panel further comprises:
a light emission driving circuit for providing a light emission control signal to the pixel circuit;
a second type clock signal line for providing a second type clock signal to the light emitting driving circuit;
when the pixel circuit works in the holding frame, the second type clock signals are second level signals.
9. The display panel according to claim 8, wherein the second type of clock signal lines include a third clock signal line and a fourth clock signal line,
when the pixel circuit operates in the data writing frame, the output timing of the third clock signal line and the output timing of the fourth clock signal line are opposite in potential of at least part of the timings;
when the pixel circuit operates in the hold frame, the second level signals output by the third clock signal line and the fourth clock signal line are both low level signals.
10. A display device characterized in that it comprises a display panel as claimed in claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211517704.7A CN115985225A (en) | 2022-11-30 | 2022-11-30 | Display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211517704.7A CN115985225A (en) | 2022-11-30 | 2022-11-30 | Display panel and display device |
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| CN115985225A true CN115985225A (en) | 2023-04-18 |
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| CN202211517704.7A Pending CN115985225A (en) | 2022-11-30 | 2022-11-30 | Display panel and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117437879A (en) * | 2023-12-19 | 2024-01-23 | 维信诺科技股份有限公司 | Display panel driving method and device and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117437879A (en) * | 2023-12-19 | 2024-01-23 | 维信诺科技股份有限公司 | Display panel driving method and device and display device |
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