CN115965087A - Superconducting qubit self-capacitance miniaturization design method and superconducting qubit self-capacitance - Google Patents
Superconducting qubit self-capacitance miniaturization design method and superconducting qubit self-capacitance Download PDFInfo
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Abstract
The invention belongs to the technical field of superconducting quantum computing, and particularly relates to a superconducting qubit self-capacitance miniaturization design method and a superconducting qubit self-capacitance, wherein the width of a capacitor is used as a capacitance miniaturization measurement standard, basic parameters of the capacitor are set to be constant values, and the shape of the capacitor is set to be adjustment optimization parameters; acquiring the performance parameters of the capacitor under the current shape by using third-party simulation software, wherein the performance parameters at least comprise: approximating a capacitance value, a coherence time length and electric field distribution, and selecting a next optimization direction of the capacitor shape according to the performance parameters; and screening out the capacitor shape with optimal coherence time and optimal electric field distribution according to the performance parameters before and after capacitor optimization, and comparing the size difference between the screened capacitor shape and the parallel plate capacitor to measure the miniaturization effect. The invention can realize the miniaturization design of the self-capacitance while keeping the coherence time of the superconducting qubit so as to meet the application in the current superconducting qubit chip integration.
Description
Technical Field
The invention belongs to the technical field of superconducting quantum computing, and particularly relates to a superconducting qubit self-capacitance miniaturization design method and a superconducting qubit self-capacitance.
Background
Superconducting qubits have received a great deal of attention since their introduction and are considered to be one of the best candidate systems for the realization of large-scale practical quantum computation in the future. Current superconducting qubit designs employ large coplanar parallel plate capacitors for energy participation in diluting the amorphous interface dielectric. The capacitor structure has the following problems: 1. large size single quantum scale and complexity of microwave design. Parasitic capacitive coupling between the parallel plate capacitances can result in stray qubit coupling, increasing coherence errors, and affecting qubit fidelity. 2. Superconducting qubit chips have limited integration. Fault-tolerant quantum computing requires a huge number of physical bits to implement, and the number of bits in a superconducting quantum chip will increase rapidly in the foreseeable future, thus requiring higher integration of the superconducting quantum chip. Because qubits are currently limited on a single chip, the size of the qubits is therefore limited. 3. Problems with increased integration: the performance of superconducting qubits is affected by charge noise, circuit crosstalk, and loss.
Disclosure of Invention
Therefore, the invention provides a miniaturization design method of a superconducting qubit self-capacitance and the superconducting qubit self-capacitance, which can realize the miniaturization design of the self-capacitance to meet the application in the current superconducting qubit chip integration while keeping the coherence time of the superconducting qubit.
According to the design scheme provided by the invention, a miniaturized design method of a superconducting qubit self-capacitance is provided, which comprises the following contents:
taking the width as a capacitance miniaturization measurement standard, setting basic capacitance parameters as constant values, setting the coherence time between capacitances as an optimization index, and setting the capacitance shape as an adjustment optimization parameter, wherein the basic capacitance parameters at least comprise the size of a parallel electrode plate, a Josephson junction broadband, the spacing of parallel electrode plates, and the equivalent inductance capacitance value of the Josephson junction;
acquiring the performance parameters of the capacitor under the current shape by means of third-party simulation software, wherein the performance parameters at least comprise: approximating a capacitance value, a coherence time length and electric field distribution, and selecting a next optimization direction of the capacitor shape according to the performance parameters;
and screening out the capacitor shape with optimal coherence time and optimal electric field distribution according to the performance parameters before and after capacitor optimization, and comparing the size difference between the screened capacitor shape and the parallel plate capacitor to measure the miniaturization effect.
As the miniaturization design method of the superconducting qubit self-capacitance, in the process of obtaining the capacitance performance parameters under the current shape by means of third-party simulation software, the superconducting qubit property is changed by adjusting the capacitance shape, a Maxwell capacitance matrix under the current capacitance shape is obtained by means of Q3D model simulation, and an approximate capacitance value and a coherence time length are obtained according to the capacitance matrix and LOM superconducting qubit simulation; and (3) analyzing the electric field distribution and dielectric loss of the capacitor under the current shape by establishing an electric field simulation graph.
As a method for designing the superconducting qubit self-capacitance miniaturization, further, the capacitance shape optimization direction includes: the width dimension of the parallel electrode plate is reduced and the shape is adjusted.
As a method for designing the superconducting qubit self-capacitance miniaturization, further, the capacitance shape optimization direction further comprises: the number and shape of the projections between the parallel electrode plates are adjusted.
Further, the present invention also provides a superconducting qubit self-capacitance, which adopts a parallel plate capacitance structure, and utilizes the above method to realize design, comprising: the capacitor comprises a first electrode plate, a second electrode plate, a dielectric medium positioned between the first electrode plate and the second electrode plate, and control lines arranged on the first electrode plate and the second electrode plate, wherein expansion bulge components which are symmetrically interwoven with each other and used for preventing capacitor loss are arranged at the central parts of the inner sides of the first electrode plate and the second electrode plate; the expansion bulge component comprises bulges and grooves which are respectively arranged on the inner side surface of the first electrode plate and the inner side surface of the second electrode plate and are correspondingly arranged.
As the superconducting qubit self-capacitance of the invention, further, the bulge adopts a bulge structure with an arc-shaped section.
As the superconducting qubit self-capacitance, further, the protrusions on the second electrode plate are arranged in the middle of the inner side surface of the second electrode plate, the grooves on the first electrode plate are arranged in the middle of the inner side surface of the first electrode plate, the grooves on the second electrode plate are symmetrically arranged along the central line of the protrusions of the second electrode plate, and the protrusions of the first electrode plate are symmetrically arranged along the central line of the grooves of the first electrode plate.
As the superconducting qubit self-capacitance of the present invention, further, the expansion bump component further comprises: triangular capacitor protrusions respectively arranged on the inner side surfaces of the first electrode plate and the second electrode plate and used for increasing decoherence time.
As the superconducting qubit self-capacitance of the invention, further, the triangular capacitance bulge is respectively arranged at the center of the middle groove at the inner side of the first electrode plate and the center of the middle bulge at the inner side of the second electrode plate, or respectively arranged at the center of the middle bulge at the inner side of the first electrode plate and the center of the middle groove at the inner side of the second electrode plate.
As the superconducting qubit self-capacitance, the triangular capacitance bulge adopts a structure with an isosceles triangle section.
The invention has the beneficial effects that:
on the premise of ensuring the property of the superconducting qubit, the invention changes the property of the superconducting qubit by changing the shape of the capacitor, adding a fillet, a triangular structure and the like in a large coplanar parallel plate and by miniaturizing the shape of the capacitor, thereby meeting the application in the integration of a superconducting qubit chip; the superconducting qubit self-capacitance designed in a miniaturization way can enlarge the surface size of a parallel plate capacitor, reduce dielectric loss and increase capacitance value to a certain extent on the premise of ensuring the capacitance performance, and is convenient for application in quantum chip integration.
Description of the drawings:
FIG. 1 is a schematic diagram of a design flow of the superconducting qubit self-capacitance miniaturization in an embodiment;
FIG. 2 is a schematic diagram of a design principle of miniaturization of a capacitor in an embodiment;
FIG. 3 is a diagram illustrating a superconducting qubit self-capacitance structure in an embodiment;
FIG. 4 is a schematic diagram of a parallel plate capacitor design according to an embodiment;
FIG. 5 is a diagram showing an electric field distribution of parallel plate capacitance in the example;
FIG. 6 is a schematic diagram of an elliptical parallel plate capacitor design according to an embodiment;
FIG. 7 is a diagram showing an electric field distribution of an elliptical parallel plate capacitor in an example;
FIG. 8 is a schematic diagram showing the four-corner rounding of the parallel plate capacitor in the example;
FIG. 9 is a diagram showing the distribution of electric field after rounding the four corners of the parallel plate capacitor in the example;
FIG. 10 is a schematic view showing the addition of triangular protrusions in the parallel plate in the embodiment;
FIG. 11 is a diagram showing an electric field distribution of the parallel plate in the embodiment after triangular protrusions are added;
FIG. 12 is a schematic diagram showing the design of adding triangular capacitors in the rounded parallel plates in the embodiment;
FIG. 13 is a diagram showing an electric field distribution after triangular capacitance is added to rounded parallel plates in the example;
FIG. 14 is a schematic diagram of a novel extended capacitor with additional circular protrusions in the embodiment;
FIG. 15 is a comparison of sizes of two capacitor products with the addition of the arc bumps in the example;
FIG. 16 is a schematic diagram of an embodiment of adding triangular capacitor bumps and arc bumps;
FIG. 17 is a schematic comparison of sizes of two capacitor products with triangular capacitor bumps and circular arc bumps added in the embodiment;
FIG. 18 is a schematic diagram of an electric field distribution diagram of the embodiment with the triangular capacitor bumps and the circular arc bumps added.
In the drawing, reference numeral 1 denotes a first electrode plate, reference numeral 2 denotes a second electrode plate, reference numeral 3 denotes a dielectric, and reference numeral 4 denotes a control line pin.
The specific implementation mode is as follows:
in order to make the objects, technical solutions and advantages of the present invention clearer and more obvious, the present invention is further described in detail below with reference to the accompanying drawings and technical solutions.
An embodiment of the present invention, as shown in fig. 1, provides a method for miniaturized design of a self-capacitance of a superconducting qubit, including:
s101, taking the width as a capacitance miniaturization measuring standard, setting basic capacitance parameters as constant values, setting the coherence time between capacitances as an optimization index, and setting the capacitance shape as an adjustment optimization parameter, wherein the basic capacitance parameters at least comprise the size of a parallel electrode plate, a Josephson junction broadband, the interval of the parallel electrode plates, and the equivalent inductance capacitance value of the Josephson junction;
s102, acquiring the performance parameters of the capacitor in the current shape by means of third-party simulation software, wherein the performance parameters at least comprise: approximating a capacitance value, a coherence time length and electric field distribution, and selecting a next optimization direction of the capacitor shape according to the performance parameters;
s103, screening out a capacitor shape with optimal coherence time and optimal electric field distribution according to performance parameters before and after capacitor optimization, and comparing the size difference between the screened capacitor shape and the parallel plate capacitor to measure the miniaturization effect.
Various parameters of the capacitor are set to be constant values, the shape of the capacitor is changed, round corners, triangular structures and the like are added in the large coplanar parallel plates, the property of the superconducting qubit is changed through the miniaturization design of the shape of the capacitor, and the application in the integration of the superconducting qubit chip is met. Furthermore, in the process of obtaining the capacitance performance parameters under the current shape by means of third-party simulation software, the superconducting qubit property is changed by adjusting the capacitance shape, a Maxwell capacitance matrix under the current capacitance shape is obtained by means of Q3D model simulation, and an approximate capacitance value and a coherence time length are obtained according to the capacitance matrix and LOM superconducting qubit simulation; and analyzing the electric field distribution and dielectric loss of the capacitor under the current shape by establishing an electric field simulation graph.
Referring to fig. 2, as the miniaturization of the capacitor is based on the coherence time as a measure, the coherence time of the novel capacitor and the coherence time of the parallel plate capacitor can be compared, and the parameters except the shape are kept constant by adopting a control variable method; on the premise of ensuring bit properties, the properties of the superconducting qubits are changed by changing the shape of the capacitor and adding a fillet, a triangular structure and the like in the large coplanar parallel plate. For example, the parallel plate capacitance can be set according to the parameters shown in table 1, there are three control lines, three corresponding plates can be connected, and the width and equivalent inductance values of the josephson junction, the parallel plate height, the plate width, etc. are set as follows:
TABLE 1 basic parameter setting table
| Parameter name | Value of | |
| Parallel plate capacitor spacing | pad_gap | 30um |
| Josephson junction width | inductor_width | 20um |
| Width of parallel plate facing | pad_width | 425um |
| Height of parallel plates | pad_height | 90um |
| Width of the bag | pocket_width | 650um |
| Height of the bag | pocket_height | 650um |
| Offset of x axis | pos_x | 0.5mm |
| Offset of y axis | pos_y | 0.5mm |
| readout pad | pad_gap | 15um |
| cl pad | pad_width | 125um |
| bus pad | pad_heigh | 30um |
| Josephson junction inductor | L j | 14nH |
| Josephson junction capacitance | C j | 2fF |
| Resonant cavity read frequency | freq_readout | 7.0GHz |
The specific design parameters for elliptical capacitance that differ from the basic parameters can be seen in table 2:
TABLE 2 ellipse capacitance parameter table
The specific design parameters of the corner capacitor after optimizing the elliptical capacitor can be shown in table 3:
TABLE 3 fillet capacitance correction parameter table
The specific design parameters for the inner triangular capacitor that differ from the basic parameters can be seen in table 4:
TABLE 4 internal triangle capacitance parameter table
| Parameter name | Value of | |
| Triangle side length | s | 20μm |
| Obtuse angle of triangle | a | 120° |
The specific design parameters of the optimized capacitor by combining the inner triangular capacitor and the rounded corner capacitor can be shown in table 5:
TABLE 5 fillet-combined inner triangle capacitance parameter table
The specific design parameters of the miniaturized capacitor of the present embodiment different from the basic parameters can be shown in table 6:
TABLE 6 extended form capacitance parameter table
| Name of parameter | Value of | ||
| Radius of circle | radius | 10μm | |
| Number of | n | 3 |
The parameter adjustments for the capacitance optimized for the new shape capacitance can be as shown in table 7:
TABLE 7 extended shape internal triangle capacitance parameter table
| Parameter name | Value of | ||
| Radius of circle | radius | 30μm | |
| Number of | n | 3 | |
| Triangle side length | s | 10μm | |
| Triangular offset | pad_gap/2+radius | 45μm |
Drawing a design drawing by adjusting the shape of the capacitor, and finely adjusting the shape by means of a qisskit-metal to prepare for next simulation analysis of the capacitor and calculation of coherence time; the Maxwell capacitance matrix can be obtained by means of Q3D model simulation, and the approximate capacitance value and the coherence time length can be obtained by means of capacitance matrix and LOM superconducting qubit simulation calculation; establishing an electric field simulation image by means of an HFSS simulation method, and analyzing electric field distribution and dielectric loss of the capacitor, thereby providing a basis for further design of capacitor miniaturization; combining and analyzing the capacitance value, the coherence time and the electric field distribution result, measuring the advantages and disadvantages of each shape, combining the advantages of each shape, and selecting the optimization direction of the next capacitor shape; and continuously updating and perfecting the shape of the capacitor, and screening the capacitor with optimal coherence time and optimal electric field distribution condition so as to obtain the shape of the capacitor with optimal performance of the super-conductance qubit under the current capacitance parameter setting. The miniaturization effect can be measured by comparing the size difference between the novel capacitor shape and the parallel plate capacitor.
Based on the above method, an embodiment of the present invention further provides a superconducting qubit self-capacitance, which adopts a parallel plate capacitance structure, and includes: the capacitor comprises a first electrode plate, a second electrode plate, a dielectric medium positioned between the first electrode plate and the second electrode plate, and control lines arranged on the first electrode plate and the second electrode plate, wherein expansion bulge components which are symmetrically interwoven with each other and used for preventing capacitor loss are arranged at the central parts of the inner sides of the first electrode plate and the second electrode plate; the expansion bulge component comprises bulges and grooves which are respectively arranged on the inner side surface of the first electrode plate and the inner side surface of the second electrode plate and are correspondingly arranged.
The electric field distribution can be optimized by referring to the structure shown in fig. 3, wherein the protrusion has an arc-shaped cross section. The bulge on the second electrode plate is arranged in the middle of the inner side face of the second electrode plate, the groove on the first electrode plate is arranged in the middle of the inner side face of the first electrode plate, the groove on the second electrode plate is symmetrically arranged along the central line of the bulge on the second electrode plate, and the bulge on the first electrode plate is symmetrically arranged along the central line of the groove on the first electrode plate. The expansion bulge component also comprises: triangular capacitor protrusions respectively arranged on the inner side surfaces of the first electrode plate and the second electrode plate and used for increasing decoherence time. The triangular capacitor bulge is respectively arranged at the center of the middle groove of the inner side surface of the first electrode plate and the center of the middle bulge of the inner side surface of the second electrode plate, or respectively arranged at the center of the middle bulge of the inner side surface of the first electrode plate and the center of the middle groove of the inner side surface of the second electrode plate. The triangular capacitor bulge can adopt a structure with an isosceles triangle section.
In order to verify the validity of the scheme, the following further explanation is made by combining the test data:
a classic parallel plate capacitor design is shown in fig. 4, where three control lines are placed at the center of the pocket, on either side of the large parallel plate. The GDS file of the parallel plate capacitor is led into HFSS software for simulation, and the obtained capacitor matrix of the parallel plate capacitor is shown in table 8, wherein the diagonal line represents the capacitance value of each flat plate and is constant positive; the off-diagonal represents the coupling capacitance value of any two parts, which is constantly negative:
TABLE 8 parallel-plate capacitor simulation capacitor matrix
The capacitance matrix obtained by HFSS simulation can be approximated by LOM method to find parameters such as bit capacitance, decoherence time, bit frequency, etc., and after 15 times of iterative computations, the results are as shown in Table 9:
TABLE 9 parallel plate capacitance parameter calculation results
| Parameter of property | Value of |
| f_Q | 5.021551[GHz] |
| EC | 306.286385[MHz] |
| EJ | 11.671114[GHz] |
| alpha | -361.341682[MHz] |
| dispersion | 105.828700[KHz] |
| Lq | 13.994355[nH] |
| Cq | 63.242211[fF] |
| T1 | 226.351758[μs] |
The parallel plate capacitance model of Q3D consists of a 430mm thick sapphire substrate and surface parallel plate capacitance, coupling capacitance, pocket, josephson junction and bridge. The Mag _ E electric field distribution image is drawn by HFSS, as in fig. 5. Since the electric field distribution is related to the size of the capacitor, the larger the size, the weaker the surface loss effect of the qubit device. Therefore, the electric field distribution changes in the different capacitance shapes were compared with each other using the electric field distribution of the parallel plate capacitance as a reference. As can be seen from FIG. 5, the in-plane electric field of the parallel plate capacitor ranges from 1.1417 to 1.4271E +10V/m, and is mainly concentrated in the middle of the two parallel plates, and the electric field intensity is more obvious as the electric field is closer to the inner part.
The elliptic parallel plate capacitor shown in fig. 6 is formed by rounding rectangular capacitor plates to reduce charge noise and energy dissipation and prolong decoherence time, but the elliptic parallel plate capacitor has the influence on miniaturization of capacitor design volume at the expense of capacitor. The parameters are shown in Table 2, except for the same parameters as in Table 1. To round the capacitor, a semicircle with a radius of 45 μm (where r = pad _ height/2) was added to each of the left and right sides of a rectangular plate with a width of 335 μm and a thickness of 90 μm, keeping the total length at 425 μm, which is the same as the basic parallel plate capacitance parameter. If (0, 0) is taken as the initial position of the rectangular capacitor plate, then (0.1675mm, 0) and (-0.1675mm, 0) are taken as the positions of the centers of the two semicircles to be combined with the parallel plate capacitor. After the parameters are set, the HFSS is called for simulation, and the calculated capacitance matrix is shown in table 10:
TABLE 10 ellipse parallel plate capacitance simulation capacitance matrix
The capacitance matrix obtained by HFSS simulation can be approximated by LOM method to obtain the parameters of capacitance, decoherence time, bit frequency, etc. of the elliptic parallel plate capacitor, and after 15 times of iterative computation, the results are shown in Table 11:
TABLE 11 results of calculation of capacitance parameters of elliptical parallel plates
| Parameter of property | Value of |
| f_Q | 5.157391[GHz] |
| EC | 324.411849[MHz] |
| EJ | 11.671114[GHz] |
| alpha | -385.246118[MHz] |
| dispersion | 169.977097[KHz] |
| Lq | 13.994355[nH] |
| Cq | 59.708757[fF] |
| T1 | 198.341307[μs] |
At the same time, the electric field profile of the elliptical parallel plate capacitor structure can also be viewed by HFSS, as in fig. 7. The electric field concentration is distributed in the internal Josephson junction, the distribution of the electric field in the plate of the elliptic parallel plate is 1.1412-1.4265E +10V/m, which is reduced compared with the electric field range of the parallel plate capacitor, which is 1.1417-1.4271E + 10V/m. Due to the excessive reduction of the size of the elliptical capacitor, the capacitance value is greatly influenced, and thus the properties of the qubit are changed.
Referring to fig. 8, four corners of the parallel plate are rounded to reduce the area lost during rounding, increase the capacitance, and prevent the over-reduction of the decoherence time. It is based on a base parallel plate capacitance, with four fillet settings as shown in table 3, except for the same parameters as the parallel plates in table 1. The four corners of a rectangular plate 425 μm wide and 90 μm thick were rounded: four circles each having a radius of 30 μm were arranged and joined to four corners of a rectangular plate having a width of 365 μm and a thickness of 90 μm, and the remaining portions were joined together by a long plate having a width of 30 μm and a thickness of 30 μm. If (0, 0) is the initial position of the rectangular capacitor plate, the (+ -182.5, + -15) μm is also used as the position of the center of the circular arc for splicing, and the circular arc is respectively combined with the parallel plate capacitor. After the parameters are set, the HFSS is called for simulation, and the calculated capacitance matrix is shown in table 12:
table 12 modified corner capacitor simulation capacitor matrix
Through the capacitance matrix obtained by HFSS simulation, parameters such as the capacitance value, the decoherence time, the bit frequency and the like of the rounded corner capacitor after correction can be approximately obtained by means of an LOM method, and after 15 times of iterative calculation, the result is shown in table 13, the T1 time is increased from 198.341307 mu s to 211.456076 mu s, and the capacitance is also increased to 61.440766fF:
TABLE 13 fillet capacitance parameter calculation results after correction
| Parameter of property | Value of |
| f_Q | 5.089424[GHz] |
| EC | 315.266711[MHz] |
| EJ | 11.671114[GHz] |
| alpha | -373.148807[MHz] |
| dispersion | 134.532106[KHz] |
| Lq | 13.994355[nH] |
| Cq | 61.440766[fF] |
| T1 | 211.456076[μs] |
Looking at the electric field distribution diagram of the modified rounded corner capacitor structure through HFSS, as shown in FIG. 9, the electric field intensity inside the capacitor plate is between 1.1309 and 1.4136V/m, and the maximum electric field intensity is concentrated at the center inside the capacitor and is reduced by 10V/m compared with that of 1.1417 and 1.4271E < ++ of the parallel plate capacitor. The angle of the parallel plate becomes smooth within a certain range, and the surface loss of the quantum device becomes small. Due to the large loss of capacitance in the rounding process, if the holding capacitance is the same as the common parallel plate capacitance, the length of the corner capacitor is extended to 440 μm, and the calculated parameters are as shown in table 4.13, wherein the decoherence time is 240.200063us, which is increased by 6.12% compared with 226.351758us of the parallel plate capacitance and 13.59% compared with 211.456076us of the corner capacitor.
Referring to FIG. 10, a trapezoidal or triangular shaped capacitor bump is added to the inside of the two parallel plates to increase the decoherence time. Due to the fact that small triangles in the rectangle are added, surface loss of the quantum bit device can be weakened. Based on the base parallel plate capacitance, the internal small triangle setup modification is shown in Table 4, except for the same parameters as for the parallel plates in Table 1. A pair of isosceles triangles with side length s =20 μm and obtuse angle of 120 DEG are added inside a rectangular plate with width of 425 μm and thickness of 90 μm, and if (0, 0) is taken as the initial position of the rectangular capacitor plate, (0, 0) is also taken as the position of the isosceles triangle, and the isosceles triangle is rotated by 90 DEG in the forward direction and then is combined with the parallel plate capacitor. After the parameters are set, the HFSS is called for simulation, and the calculated capacitance matrix is shown in table 14:
TABLE 14 inner triangular capacitance simulation capacitance matrix
Through a capacitance matrix obtained by HFSS simulation, parameters such as capacitance value, decoherence time, bit frequency and the like of the inner triangular capacitor can be approximately obtained by means of an LOM method, after 15 times of iterative calculation, the result is shown in a table 15, T1 time is increased from original 230.865608 mu s to 237.054564 mu s, and the capacitance is slightly increased:
TABLE 15 results of parallel plate inner triangle capacitance parameter calculation
| Parameter of property | Value of |
| f_Q | 4.998405[GHz] |
| EC | 303.258391[MHz] |
| EJ | 11.671114[GHz] |
| alpha | -357.376520[MHz] |
| dispersion | 97.364514[KHz] |
| Lq | 13.994355[nH] |
| Cq | 63.873676[fF] |
| T1 | 237.054564[μs] |
Looking at the electric field distribution diagram of the inner triangular capacitor structure through HFSS, as shown in FIG. 11, it is found that the electric field intensity inside the capacitor plate is between 1.1567-1.3495E +10V/m, and the maximum electric field intensity is only concentrated at the Josephson junction at the innermost part of the capacitor. The addition of triangles in the parallel plates weakens the concentration of electric field distribution, so that the shape of the capacitor can be improved by reference.
As shown in fig. 12, the fillet parallel plate inner triangular capacitor is derived from the combination of the inner triangular capacitor and the fillet parallel plate capacitor, and because the simulation result effect of the two capacitor shapes is better, the rectangular capacitor plate is subjected to rounding treatment, so that the charge noise and the energy dissipation can be reduced, the surface loss of the superconducting quantum device can be reduced by adding a small triangle inside, the decoherence time is greatly increased, and the two capacitors are combined to verify whether the capacitor has a better effect. Based on the extended rounded parallel plate capacitance and the inner triangular capacitance, the parameters are combined with table 1, table 3, table 4, and the specific implementation is shown in table 5. On one hand, the capacitor shape realizes the rounding treatment of the capacitor, four circles with the radius of 30 mu m are arranged and spliced at the four corners of a rectangular plate with the width of 380 mu m and the thickness of 90 mu m, and the vacant parts are spliced by a long plate with the width of 30 mu m and the thickness of 30 mu m. If (0, 0) is the initial position of the rectangular capacitor plate, the (+/-190, +/-15) μm is also taken as the position of the center of the splicing circular arc, and the splicing circular arc is respectively combined with the parallel plate capacitor. On the other hand, a pair of isosceles triangles with side length s =20 μm and angle 120 ° is added inside the rectangular plate, and if (0, 0) is taken as the initial position of the rectangular capacitor plate, then (0, 0) is also taken as the position of the isosceles triangle to be combined with the parallel plate capacitor. After the parameters are set, the HFSS is called for simulation, and the calculated capacitance matrix is shown in table 16:
TABLE 16 fillet parallel plate inner triangle capacitance simulation capacitance matrix
Parameters such as capacitance, decoherence time, bit frequency and the like of the triangular capacitor in the round-angle parallel plate can be approximately solved through a capacitance matrix obtained by HFSS simulation by means of an LOM method, and after 15 times of iterative calculation, the results are shown in a table 17:
TABLE 17 calculation of bit-property parameters of triangular capacitors in rounded parallel plates
Meanwhile, an electric field distribution diagram of the rounded-corner parallel-plate inner triangular capacitor structure can be checked through HFSS, as shown in FIG. 13, the electric field range inside the capacitor plate is 1.1243-1.4054E +10V/m, and is reduced compared with the electric field range before the small triangle is increased by 1.1309-1.4136E + 10V/m.
Because of the extension of the corner capacitor, the size of the capacitor is changed although the decoherence time is improved. Thus, two capacitance optimization directions can be summarized: firstly, the electric field intensity distribution is weaker along with the smoother and smoother angle of the capacitor plate, and a right angle can be replaced by an arc, so that the loss is weakened; second, the triangular capacitors added on the inner sides of the two plates can improve the bit performance, and the capacitors can be optimized inside. The rounding degree of the capacitor can influence the performance of the quantum ratio characteristic and the decoherence time, but the loss of the capacitor is too large, and the loss of the capacitor is also compensated by the method. Attempts to place the arc on the inside of the two plates, similar to an inside triangular capacitor, avoid the loss of capacitance due to parallel plate angle optimization. In summary, referring to the new extended capacitor design drawing shown in fig. 14, an arc is added to the inner sides of the two plates, the specific parameter design is shown in table 6, parameters such as capacitance, decoherence time, bit frequency, and the like of the extended capacitor can be approximately obtained by means of the LOM method through the capacitance matrix obtained by HFSS simulation, and the simulation result obtained by calculation is shown in table 18:
TABLE 18 extended shape capacitance parameter calculation results
| Parameter of property | Value of |
| f_Q | 4.806487[GHz] |
| EC | 278.820648[MHz] |
| EJ | 11.671114[GHz] |
| alpha | -325.665845[MHz] |
| dispersion | 47.263011[KHz] |
| Lq | 13.994355[nH] |
| Cq | 69.472000[fF] |
| T1 | 335.471349[μs] |
The decoherence time of the capacitance simulation result of the extended shape is increased from 226.35176us to 335.471349us, which is improved by more than 100 mus. It can also be seen from the data of the current simulation that the new shape can increase the decoherence time because: this shape increases the capacitance value for the same size. Because of the large scale expansion of qubits, it is not possible to maintain a fixed capacitance value and make the capacitance size as small as possible while ensuring the quantum ratio performance at the expense of bit performance loss. The capacitor size, such as the reduced plate length, is adjusted to keep the decoherence time of the extended shape capacitor around 226 mus, which is comparable to the parallel plate capacitance. The size comparison is as follows: the area of the parallel plate capacitor is 425 μm wide by 90 μm high; the area of the new shape capacitor was 373 μm wide by 90 μm high. The width was shortened by 52 μm as shown in FIG. 15.
And in combination with the advantages of the inner triangular capacitor, two opposite small triangles are added on the inner sides of the two arcs of the new shape, and the performance condition of the coherence time is verified. First, a plan is drawn using the qisskit-metal, as shown in FIG. 16. The two plates are respectively and symmetrically interwoven with three arcs, two triangles are arranged at the arc vertex in the center, specific parameters are set as shown in table 7, parameters such as capacitance value, decoherence time, bit frequency and the like of the triangular capacitor in the extended shape can be approximately solved by means of a capacitance matrix obtained by HFSS simulation by means of an LOM method, and a simulation result obtained by calculation is shown in table 19:
TABLE 19 extended shape inner triangle capacitance parameter calculation results
| Parameter of property | Value of |
| f_Q | 4.792311[GHz] |
| EC | 277.062560[MHz] |
| EJ | 11.671114[GHz] |
| alpha | -323.404254[MHz] |
| dispersion | 44.701384[KHz] |
| Lq | 13.994355[nH] |
| Cq | 69.912832[fF] |
| T1 | 344.272928[μs] |
The decoherence time of the expansion capacitance of the new shape after the small triangle is added inside is increased from 335.471349 mus to 344.272928 mus, and the improvement effect is more obvious. The plate width of the capacitor is reduced, the decoherence time is controlled to be about 227us, and the size of the obtained miniaturized capacitor is 369 μm wide × 90 μm high. Under the condition of ensuring the performance of the superconducting qubit to be unchanged, the size of the capacitor is reduced by 56 μm compared with that of a parallel plate capacitor, as shown in FIG. 17. The electric field distribution of the extended capacitor is simulated by using HFSS, as shown in FIG. 18, wherein the maximum intensity electric field is concentrated at the center, which is about 7.9987E +09V/m-1.1198E +10V/m, and the electric field intensity of the capacitor is reduced compared with that of capacitors of other shapes, which shows that the shape can effectively reduce dielectric loss, improve the electric field distribution condition, reduce the size of a parallel plate from 425 μm to 369 μm under the condition of keeping the decoherence time unchanged, and realize the miniaturization of the capacitor.
In summary, in the embodiments of the present invention, the capacitor shape can be optimized by using a capacitor angle rounding mechanism and a method of reducing dielectric loss, so as to reduce the energy participation ratio, improve the coherence time of the superconducting qubit, and achieve the miniaturization of the capacitor under the condition of maintaining the coherence time of the superconducting qubit. According to experimental data, compared with a parallel plate capacitor, the novel shape width of the capacitor is shortened from 425 micrometers to 369 micrometers, the width of the capacitor is shortened by 56 micrometers, and the capacitor accounts for 13.18% of the original parallel plate size. Based on the influence of the angle correction value, the rounding degree of the capacitor angle is changed to change the decoherence time, and when the angle of the parallel capacitor plate is more rounded, the dielectric loss is smaller, and the decoherence time expression value is larger; meanwhile, the defect of the capacitor is considered, and the smooth treatment is arranged on the inner side of the parallel plate, so that the surface size of the parallel plate capacitor is enlarged, and the dielectric loss is reduced; on the other hand, the capacitance value is increased to a certain extent; and finally, in combination with the excellent performance of the inner triangular capacitor, a pair of small triangles are additionally arranged on the inner sides of the two arcs, so that smaller dielectric loss can be realized, and the electric field distribution condition is optimized. And the dielectric loss is analyzed by adopting electric field distribution, the appearance of decoherence time is taken as a measurement standard of superconducting quantum specific performance, through experimental comparison, the maximum electric field distribution can be reduced from 1.4271E +10V/m of the original parallel-plate capacitor to 1.1198E +10V/m of the newly-shaped capacitor, and the method has a guidance promotion effect on further realizing the miniaturization of superconducting quantum bits.
Unless specifically stated otherwise, the relative steps, numerical expressions, and values of the components and steps set forth in these embodiments do not limit the scope of the present invention.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. For the system disclosed by the embodiment, the description is relatively simple because the system corresponds to the method disclosed by the embodiment, and the relevant points can be referred to the method part for description.
The elements of each example, and method steps, described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and the components and steps of each example have been described in a functional generic sense in the foregoing description for the purpose of illustrating the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
Those skilled in the art will appreciate that all or part of the steps of the above methods can be implemented by a program instructing relevant hardware, and the program can be stored in a computer readable storage medium, such as: read-only memory, magnetic or optical disk, and the like. Alternatively, all or part of the steps of the foregoing embodiments may also be implemented by using one or more integrated circuits, and accordingly, each module/unit in the foregoing embodiments may be implemented in the form of hardware, and may also be implemented in the form of a software functional module. The present invention is not limited to any specific form of combination of hardware and software.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, which are used for illustrating the technical solutions of the present invention and not for limiting the same, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the embodiments of the present invention, and they should be construed as being included therein. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for designing a miniaturized self-capacitance of a superconducting qubit is characterized by comprising the following steps:
taking the width of the capacitor as a capacitor miniaturization measuring standard, setting basic parameters of the capacitor as constant values, setting the coherence time between capacitors as an optimization index, and setting the shape of the capacitor as an adjustment optimization parameter, wherein the basic parameters of the capacitor at least comprise the size of a parallel electrode plate, a Josephson junction broadband, the interval of the parallel electrode plates, and the equivalent inductance capacitance value of the Josephson junction;
acquiring the performance parameters of the capacitor under the current shape by means of third-party simulation software, wherein the performance parameters at least comprise: approximating a capacitance value, a coherence time length and electric field distribution, and selecting a next optimization direction of the capacitor shape according to the performance parameters;
and screening out the capacitor shape with optimal coherence time and optimal electric field distribution according to the performance parameters before and after capacitor optimization, and comparing the size difference between the screened capacitor shape and the parallel plate capacitor to measure the miniaturization effect.
2. The superconducting qubit self-capacitance miniaturization design method of claim 1, wherein in obtaining the capacitance performance parameters in the current shape by means of third-party simulation software, the superconducting qubit property is changed by adjusting the capacitance shape, a maxwell capacitance matrix in the current capacitance shape is obtained by means of Q3D model simulation, and an approximate capacitance value and a coherence time length are obtained according to the capacitance matrix and LOM superconducting qubit simulation; and analyzing the electric field distribution and dielectric loss of the capacitor under the current shape by establishing an electric field simulation graph.
3. The method of claim 1 or 2, wherein the optimization direction of the capacitance shape comprises: the width dimension of the parallel electrode plate is reduced and the shape is adjusted.
4. The method of claim 3, wherein the optimization direction of the capacitance shape further comprises: the number and shape of the projections between the parallel electrode plates are adjusted.
5. A superconducting qubit self-capacitance employing a parallel plate capacitance architecture, the design implemented using the method of claim 1, comprising: the capacitor comprises a first electrode plate, a second electrode plate, a dielectric medium positioned between the first electrode plate and the second electrode plate, and control lines arranged on the first electrode plate and the second electrode plate, wherein expansion bulge components which are symmetrically interwoven with each other and used for preventing capacitor loss are arranged at the central parts of the inner sides of the first electrode plate and the second electrode plate; the expansion projection assembly comprises projections and grooves which are respectively arranged on the inner side surface of the first electrode plate and the inner side surface of the second electrode plate and are arranged correspondingly.
6. A superconducting qubit self-capacitance according to claim 1, wherein the protrusion is of an arc-shaped cross-section.
7. A superconducting qubit self-capacitance according to claim 1, wherein the protrusions on the second electrode plate are disposed in the middle of the inner side of the second electrode plate, the grooves on the first electrode plate are disposed in the middle of the inner side of the first electrode plate, and the grooves on the second electrode plate are symmetrically disposed along the center line of the protrusions on the second electrode plate, and the protrusions on the first electrode plate are symmetrically disposed along the center line of the grooves on the first electrode plate.
8. The superconducting qubit self-capacitance of claim 1, wherein the expansion bump assembly further comprises: triangular capacitor protrusions respectively arranged on the inner side surfaces of the first electrode plate and the second electrode plate and used for increasing decoherence time.
9. A superconducting qubit self-capacitor according to claim 8, wherein the triangular capacitor projections are respectively provided at the center of the middle recess at the inner side of the first electrode plate and at the center of the middle projection at the inner side of the second electrode plate, or at the center of the middle projection at the inner side of the first electrode plate and at the center of the middle recess at the inner side of the second electrode plate.
10. The superconducting qubit self-capacitance of claim 8 wherein said triangular capacitive protrusions have a cross-section in the form of an isosceles triangle.
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