CN115965087B - Miniaturization design method of superconducting quantum bit self-capacitance and superconducting quantum bit self-capacitance - Google Patents

Abstract

The present invention belongs to the field of superconducting quantum computing technology, and particularly relates to a superconducting quantum bit self-capacitor miniaturization design method and superconducting quantum bit self-capacitor, using the capacitor width as a capacitor miniaturization measurement standard, setting the basic parameters of the capacitor as constant values, and setting the capacitor shape as an adjustment optimization parameter; using third-party simulation software to obtain the capacitor performance parameters under the current shape, wherein the performance parameters at least include: approximate capacitance value, coherence time length and electric field distribution, and selecting the next optimization direction of the capacitor shape according to the performance parameters; based on the performance parameters before and after the capacitor optimization, the capacitor shape with the best coherence time and the best electric field distribution is screened out, and the miniaturization effect is measured by comparing the size difference between the screened capacitor shape and the parallel plate capacitor. While maintaining the coherence time of the superconducting quantum bit, the present invention can realize the miniaturization design of the self-capacitor to meet the application in the current superconducting quantum bit chip integration.

Description

Miniaturization design method of superconducting quantum bit self-capacitance and superconducting quantum bit self-capacitance

Technical Field

The present invention belongs to the technical field of superconducting quantum computing, and in particular relates to a method for miniaturizing the self-capacitance of a superconducting quantum bit and a superconducting quantum bit self-capacitance.

Background technique

Since its proposal, superconducting qubits have received widespread attention and are considered to be one of the best candidate systems for realizing large-scale practical quantum computing in the future. The current superconducting qubit design uses large coplanar parallel plate capacitors to dilute the energy participation of amorphous interface dielectrics. The capacitor structure has the following problems: 1. Large single quantum scale and complexity of microwave design. Parasitic capacitance coupling between parallel plate capacitors will lead to stray qubit coupling, increase coherence errors, and affect the fidelity of qubits. 2. The integration of superconducting qubit chips is limited. Fault-tolerant quantum computing requires a large number of physical bits to be realized. In the foreseeable future, the number of bits in superconducting quantum chips will increase rapidly, so the integration of superconducting quantum chips is required to be higher. Due to the current limitation of qubits on a single chip, the size of qubits is also limited. 3. Problems caused by increased integration: charge noise, circuit crosstalk, and loss affect the performance of superconducting qubits.

Summary of the invention

To this end, the present invention provides a superconducting qubit self-capacitance miniaturization design method and a superconducting qubit self-capacitance, which can achieve a miniaturized design of the self-capacitance while maintaining the coherence time of the superconducting qubit to meet the application in the current superconducting qubit chip integration.

According to the design scheme provided by the present invention, a method for miniaturizing the self-capacitance of a superconducting quantum bit is provided, which includes the following contents:

The width is used as a measure of capacitor miniaturization, and basic parameters of the capacitor are set as constant values, the coherence time between capacitors is set as an optimization index, and the capacitor shape is set as an adjustment optimization parameter, wherein the basic parameters of the capacitor at least include parallel electrode plate size, Josephson junction bandwidth, parallel electrode plate spacing, and Josephson junction equivalent inductance and capacitance value;

Using third-party simulation software to obtain capacitor performance parameters under the current shape, where the performance parameters at least include: approximate capacitance value, coherence time length and electric field distribution, and selecting the next optimization direction of the capacitor shape based on the performance parameters;

Based on the performance parameters before and after capacitor optimization, the capacitor shape with the best coherence time and electric field distribution is screened out, and the miniaturization effect is measured by comparing the size difference between the screened capacitor shape and the parallel plate capacitor.

As a design method for miniaturizing the self-capacitance of a superconducting quantum bit in the present invention, further, a third-party simulation software is used to obtain the capacitor performance parameters under the current shape, the superconducting quantum bit properties are changed by adjusting the capacitor shape, and the Maxwell capacitor matrix under the current capacitor shape is obtained by Q3D model simulation, and the approximate capacitance value and coherence time length are obtained based on the capacitor matrix and LOM superconducting quantum bit simulation; the electric field distribution and dielectric loss of the capacitor under the current shape are analyzed by establishing an electric field simulation diagram.

As a method for miniaturizing the self-capacitor of a superconducting quantum bit in the present invention, further, the capacitor shape optimization direction includes: reducing the width of the parallel electrode plates and adjusting the shape.

As a design method for miniaturizing the self-capacitance of a superconducting quantum bit in the present invention, further, the capacitor shape optimization direction also includes: adjusting the number and shape of protrusions between parallel electrode plates.

Furthermore, the present invention also provides a superconducting quantum bit self-capacitor, which adopts a parallel plate capacitor structure and is designed using the above method, comprising: a first electrode plate, a second electrode plate, a dielectric located between the first electrode plate and the second electrode plate, and control lines arranged on the first electrode plate and the second electrode plate, and an extended protrusion component that is symmetrically interwoven and used to prevent capacitance loss is arranged in the inner central part of the first electrode plate and the second electrode plate; the extended protrusion component comprises protrusions and grooves that are arranged on the inner side surface of the first electrode plate and the inner side surface of the second electrode plate and are arranged correspondingly.

As the superconducting quantum bit self-capacitor of the present invention, further, the protrusion adopts a protrusion structure with an arc-shaped cross section.

As the superconducting quantum bit self-capacitor of the present invention, further, the protrusion on the second electrode plate is arranged in the middle of the inner side surface of the second electrode plate, the groove of the first electrode plate is arranged in the middle of the inner side surface of the first electrode plate, and the groove on the second electrode plate is symmetrically arranged along the center line of the protrusion of the second electrode plate, and the protrusion of the first electrode plate is symmetrically arranged along the center line of the groove of the first electrode plate.

As the superconducting quantum bit self-capacitor of the present invention, further, the extended protrusion component also includes: triangular capacitor protrusions respectively arranged on the inner side surfaces of the first electrode plate and the second electrode plate for increasing the decoherence time.

As the superconducting quantum bit self-capacitor of the present invention, further, the triangular capacitor protrusion is respectively arranged at the center of the middle groove on the inner side of the first electrode plate and the center of the middle protrusion on the inner side of the second electrode plate, or respectively arranged at the center of the middle protrusion on the inner side of the first electrode plate and the center of the middle groove on the inner side of the second electrode plate.

As the superconducting quantum bit self-capacitor of the present invention, further, the triangular capacitor protrusion adopts a structure with an isosceles triangle cross section.

Beneficial effects of the present invention:

Under the premise of ensuring the properties of superconducting quantum bits, the present invention changes the properties of superconducting quantum bits by changing the shape of the capacitor, adding rounded corners, triangular structures, etc. in large coplanar parallel plates, and miniaturizing the capacitor shape to change the properties of superconducting quantum bits to meet the application in superconducting quantum bit chip integration; the superconducting quantum bit self-capacitor designed with miniaturization can, under the premise of ensuring the capacitor performance, reduce dielectric loss by expanding the surface size of the parallel plate capacitor, and increase the capacitance value to a certain extent, which is convenient for application in quantum chip integration.

Description of the drawings:

FIG1 is a schematic diagram of a design process for miniaturization of superconducting quantum bit self-capacitance in an embodiment;

FIG2 is a schematic diagram of the design principle of capacitor miniaturization in an embodiment;

FIG3 is a schematic diagram of a superconducting quantum bit self-capacitance structure in an embodiment;

FIG4 is a schematic diagram of a parallel plate capacitor design in an embodiment;

FIG5 is a schematic diagram of the electric field distribution of a parallel plate capacitor in an embodiment;

FIG6 is a schematic diagram of an elliptical parallel plate capacitor design in an embodiment;

FIG7 is a diagram showing the electric field distribution of an elliptical parallel plate capacitor in an embodiment;

FIG8 is a schematic diagram showing a design of rounded corners of a parallel plate capacitor according to an embodiment;

FIG9 is a diagram showing the electric field distribution of the parallel plate capacitor after rounding of the four corners in the embodiment;

FIG10 is a schematic diagram showing a design of adding triangular protrusions in parallel plates in an embodiment;

FIG11 is a diagram showing the electric field distribution after adding triangular protrusions in the parallel plates in the embodiment;

FIG12 is a schematic diagram showing a design of adding a triangular capacitor to a rounded parallel plate in an embodiment;

FIG13 is a diagram showing the electric field distribution after a triangular capacitor is added to the rounded parallel plate in the embodiment;

FIG14 is a schematic diagram of a new extended capacitor design with an arc protrusion added in the embodiment;

FIG15 is a schematic diagram showing the comparison of the sizes of two capacitor products after adding arc protrusions in the embodiment;

FIG16 is a schematic diagram showing a design of adding a triangular capacitor protrusion and an arc protrusion in the embodiment;

FIG17 is a schematic diagram showing the comparison of the sizes of two capacitor products after adding a triangular capacitor protrusion and an arc protrusion in the embodiment;

FIG. 18 is a diagram showing the electric field distribution after adding triangular capacitor protrusions and arc protrusions in the embodiment.

In the figure, reference numeral 1 represents the first electrode plate, reference numeral 2 represents the second electrode plate, reference numeral 3 represents the dielectric, and reference numeral 4 represents the control line pin.

Detailed ways:

In order to make the purpose, technical solutions and advantages of the present invention clearer and more understandable, the present invention is further described in detail below in conjunction with the accompanying drawings and technical solutions.

The embodiment of the present invention, as shown in FIG1 , provides a method for miniaturizing the self-capacitance of a superconducting quantum bit, comprising:

S101, using the width as a capacitor miniaturization measurement standard, setting the basic parameters of the capacitor as a constant value, setting the coherence time between the capacitors as an optimization index, and setting the capacitor shape as an adjustment optimization parameter, wherein the basic parameters of the capacitor at least include the parallel electrode plate size, the Josephson junction bandwidth, the parallel electrode plate spacing, and the Josephson junction equivalent inductance and capacitance value;

S102, using third-party simulation software to obtain capacitor performance parameters under the current shape, wherein the performance parameters at least include: approximate capacitance value, coherence time length and electric field distribution, and selecting the next optimization direction of the capacitor shape according to the performance parameters;

S103. Screen out a capacitor shape with optimal coherence time and electric field distribution based on performance parameters before and after capacitor optimization, and measure the miniaturization effect by comparing the size difference between the screened capacitor shape and the parallel plate capacitor.

Set all parameters of the capacitor to constant values, change the shape of the capacitor, add rounded corners and triangular structures to the large coplanar parallel plates, and change the properties of the superconducting quantum bit by miniaturizing the capacitor shape to meet the application of superconducting quantum bit chip integration. Further, use third-party simulation software to obtain the performance parameters of the capacitor under the current shape, change the properties of the superconducting quantum bit by adjusting the capacitor shape, and use Q3D model simulation to obtain the Maxwell capacitor matrix under the current capacitor shape. According to the capacitor matrix and LOM superconducting quantum bit simulation, the approximate capacitance value and coherence time length are obtained; the electric field distribution and dielectric loss of the capacitor under the current shape are analyzed by establishing an electric field simulation diagram.

As shown in Figure 2, since the miniaturization of capacitors is measured by the coherence time, the coherence time of the new capacitor and the parallel plate capacitor can be compared, and the control variable method is used to keep all parameters except the shape constant; under the premise of ensuring the properties of the bit, the properties of the superconducting quantum bit can be changed by changing the shape of the capacitor and adding rounded corners and triangular structures to the large coplanar parallel plates. For example, the parallel plate capacitor can be set according to the parameters shown in Table 1. There are three control lines that can be connected to three corresponding plates. The width and equivalent inductance of the Josephson junction, the height of the parallel plate, the width of the plate, etc. are set as follows:

Table 1 Basic parameter setting table

parameter name value Parallel plate capacitor spacing pad_gap 30um Josephson junction width inductor_width 20um Parallel plate width pad_width 425um Parallel plate height pad_height 90um Bag width pocket_width 650um Bag height pocket_height 650um x-axis offset pos_x 0.5mm Y-axis offset pos_y 0.5mm readout pad pad_gap 15um cl pad pad_width 125um bus pad pad_heigh 30um Josephson Junction Inductor _L 14nH Josephson Junction Capacitance _C 2f Resonant cavity readout frequency freq_readout 7.0GHz

The special design parameters of elliptical capacitors that are different from the basic parameters can be shown in Table 2:

Table 2 Elliptical capacitor parameter table

The special design parameters of the rounded corner capacitor after optimizing the elliptical capacitor can be shown in Table 3:

Table 3 Fillet capacitor correction parameter table

The special design parameters of the inner triangle capacitor that are different from the basic parameters can be shown in Table 4:

Table 4 Inner triangle capacitor parameter table

parameter name value Triangle side length s 20μm Triangle obtuse angle a 120°

The special design parameters of the optimized capacitor by combining the inner triangle capacitor and the rounded corner capacitor can be shown in Table 5:

Table 5 Parameters of capacitors with rounded corners and inner triangles

The special design parameters of the miniaturized capacitor in this embodiment are different from the basic parameters as shown in Table 6:

Table 6 Extended shape capacitor parameter table

parameter name value Circle radius radius 10μm Number of arcs n 3

The parameter adjustment of the capacitor after the new shape capacitor is optimized can be shown in Table 7:

Table 7 Extended shape inner triangle capacitor parameter table

parameter name value Circle radius radius 30μm Number of arcs n 3 Triangle side length s 10μm Triangle offset pad_gap/2+radius 45μm

By adjusting the capacitor shape to draw a design drawing, the shape can be fine-tuned with qiskit-metal to prepare for the next step of simulation analysis of capacitance and coherence time calculation; the Maxwell capacitance matrix can be simulated with the help of Q3D model, and the approximate capacitance value and coherence time length can be obtained with the help of capacitance matrix and LOM superconducting quantum bit simulation calculation; the electric field simulation image is established with the help of HFSS simulation method to analyze the electric field distribution and dielectric loss of the capacitor, so as to provide a basis for the further design of capacitor miniaturization; the capacitance value, coherence time and electric field distribution results are combined and analyzed to measure the advantages and disadvantages of each shape, and the optimization direction of the next capacitor shape is selected based on the advantages of each shape; the capacitor shape is continuously updated and improved, and the capacitor with the best coherence time and the best electric field distribution is selected, so as to obtain the capacitor shape with the best performance of superconducting quantum bits under the current capacitor parameter setting. The miniaturization effect can be measured by comparing the size difference between the new capacitor shape and the parallel plate capacitor.

Based on the above method, an embodiment of the present invention also provides a superconducting quantum bit self-capacitor, which adopts a parallel plate capacitor structure, including: a first electrode plate, a second electrode plate, a dielectric located between the first electrode plate and the second electrode plate, and control lines arranged on the first electrode plate and the second electrode plate, and an extended protrusion component that is symmetrically interwoven and used to prevent capacitance loss is arranged in the inner central part of the first electrode plate and the second electrode plate; the extended protrusion component includes protrusions and grooves that are respectively arranged on the inner side surface of the first electrode plate and the inner side surface of the second electrode plate and are arranged correspondingly.

Referring to the structure shown in FIG. 3 , the electric field distribution can be optimized, wherein the protrusion adopts a protrusion structure with an arc-shaped cross section. The protrusion on the second electrode plate is arranged in the middle of the inner side surface of the second electrode plate, the groove of the first electrode plate is arranged in the middle of the inner side surface of the first electrode plate, and the groove on the second electrode plate is symmetrically arranged along the center line of the protrusion of the second electrode plate, and the protrusion of the first electrode plate is symmetrically arranged along the center line of the groove of the first electrode plate. The extended protrusion assembly also includes: triangular capacitor protrusions respectively arranged on the inner sides of the first electrode plate and the second electrode plate for increasing the decoherence time. The triangular capacitor protrusions are respectively arranged at the center of the middle groove on the inner side surface of the first electrode plate and the center of the middle protrusion on the inner side surface of the second electrode plate, or respectively arranged at the center of the middle protrusion on the inner side surface of the first electrode plate and the center of the middle groove on the inner side surface of the second electrode plate. The triangular capacitor protrusion can adopt a structure with an isosceles triangle cross section.

In order to verify the effectiveness of this solution, the following is a further explanation based on the test data:

The design diagram based on the classic parallel plate capacitor is shown in Figure 4. The three control lines are arranged on both sides of the large parallel plate, and the capacitor is placed in the center of the pocket. The GDS file of the parallel plate capacitor is imported into the HFSS software for simulation, and the capacitance matrix of the parallel plate capacitor is shown in Table 8, where the diagonal lines represent the capacitance values of each plate itself, which are always positive; the non-diagonal lines represent the coupling capacitance values of any two parts, which are always negative:

Table 8 Parallel plate capacitor simulation capacitance matrix

The capacitance matrix obtained by HFSS simulation can be used to approximate the bit capacitance, decoherence time, bit frequency and other parameters with the help of LOM method. After 15 iterative calculations, the results are shown in Table 9:

Table 9 Calculation results of parallel plate capacitance parameters

Property parameters value f 5.021551[GHz] EC 306.286385[MHz] EJ 11.671114[GHz] alpha -361.341682[MHz] dispersion 105.828700[KHz] Lq 13.994355[nH] C 63.242211[fF] T1 226.351758[μs]

The parallel plate capacitor model of Q3D consists of a 430mm thick sapphire substrate and a parallel plate capacitor, coupling capacitor, pocket, Josephson junction and bridge part on the surface. The Mag_E electric field distribution image is drawn by HFSS, as shown in Figure 5. Since the electric field distribution is related to the size of the capacitor, the larger the size, the weaker the surface loss effect of the quantum bit device. Therefore, the electric field distribution of the parallel plate capacitor is used as a benchmark to compare the changes in the electric field distribution under different capacitor shapes. It can be found from Figure 5 that the electric field range of the parallel plate capacitor is 1.1417-1.4271E+10V/m, which is mainly concentrated in the middle of the two parallel plates, and the closer to the inside, the more obvious the electric field strength.

As shown in Figure 6, the elliptical parallel plate capacitor is rounded to reduce charge noise and energy dissipation and extend the decoherence time, but this is at the expense of capacitance, which affects the miniaturization of the capacitor design volume. In addition to the same parameters as Table 1, other parameters are shown in Table 2. In order to achieve the smooth processing of the capacitor, a semicircle with a radius of 45μm is added to the left and right sides of the rectangular plate with a width of 335μm and a thickness of 90μm (where r = pad_height/2), and the total length is kept at 425μm, which is the same as the basic parallel plate capacitor parameters. If (0,0) is used as the initial position of the rectangular capacitor plate, (0.1675mm, 0) and (-0.1675mm, 0) are used as the positions of the centers of the two semicircles and combined with the parallel plate capacitor. After setting the parameters, call HFSS for simulation, and the calculated capacitance matrix is shown in Table 10:

Table 10 Elliptical parallel plate capacitor simulation capacitance matrix

The capacitance matrix obtained by HFSS simulation can be used to approximate the capacitance value, decoherence time, bit frequency and other parameters of the elliptical parallel plate capacitor using the LOM method. After 15 iterative calculations, the results are shown in Table 11:

Table 11 Calculation results of elliptical parallel plate capacitance parameters

Property parameters value f 5.157391[GHz] EC 324.411849[MHz] EJ 11.671114[GHz] alpha -385.246118[MHz] dispersion 169.977097[KHz] Lq 13.994355[nH] C 59.708757[fF] T1 198.341307[μs]

At the same time, the electric field distribution diagram of the elliptical parallel plate capacitor structure can also be viewed through HFSS, as shown in Figure 7. The electric field is concentrated in the internal Josephson junction, and the electric field distribution in the elliptical parallel plate is 1.1412-1.4265E+10V/m, which is smaller than the electric field range of the parallel plate capacitor 1.1417-1.4271E+10V/m. Due to the excessive reduction in the size of the elliptical capacitor, the capacitance value is greatly affected, thereby changing the properties of the quantum bit.

As shown in Figure 8, the four corners of the parallel plate are rounded into smooth arcs to reduce the area lost during the rounding process, increase the capacitance value, and prevent excessive reduction of the decoherence time. It is based on the basic parallel plate capacitor. In addition to the same parameters as the parallel plate in Table 1, the four rounded corners are set and corrected as shown in Table 3. The four corners of the rectangular plate with a width of 425μm and a thickness of 90μm are rounded: four circles with a radius of 30μm are set and spliced at the four corners of the rectangular plate with a width of 365μm and a thickness of 90μm, and the remaining part is spliced with a long plate with a width of 30μm and a thickness of 30μm. If (0,0) is used as the initial position of the rectangular capacitor plate, (±182.5, ±15)μm is also used as the position of the center of the spliced arc, which is combined with the parallel plate capacitor respectively. After setting the parameters, call HFSS for simulation, and the calculated capacitance matrix is shown in Table 12:

Table 12 Corrected fillet capacitor simulation capacitor matrix

The capacitance matrix obtained by HFSS simulation can be used to approximate the capacitance value, decoherence time, bit frequency and other parameters of the corrected rounded capacitor by using the LOM method. After 15 iterative calculations, the results are shown in Table 13. The T1 time increases from the original 198.341307μs to 211.456076μs, and the capacitance also increases to 61.440766fF:

Table 13 Corrected fillet capacitor parameter calculation results

Property parameters value f 5.089424[GHz] EC 315.266711[MHz] EJ 11.671114[GHz] alpha -373.148807[MHz] dispersion 134.532106[KHz] Lq 13.994355[nH] C 61.440766[fF] T1 211.456076[μs]

The electric field distribution diagram of the modified rounded capacitor structure is viewed through HFSS, as shown in Figure 9. The electric field strength inside the capacitor plate is between 1.1309-1.4136V/m, and the maximum electric field strength is concentrated in the center of the capacitor, which is lower than the 1.1417-1.4271E+10V/m of the parallel plate capacitor. This shows that within a certain range, the parallel plate angle becomes smoother, and the surface loss of the quantum device will become smaller. Since the smoothing process causes a large loss to the capacitor, if the capacitance is kept the same as that of the ordinary parallel plate capacitor, and the length of the rounded capacitor is extended to 440μm, the calculated parameters are shown in Table 4.13, where the decoherence time is 240.200063us, which is 6.12% higher than the 226.351758us of the parallel plate capacitor and 13.59% higher than the 211.456076us of the rounded capacitor.

As shown in Figure 10, a trapezoidal or triangular capacitor protrusion is added to the inside of the two parallel plates to increase the decoherence time. Due to the addition of small triangles inside the rectangle, the surface loss of the quantum bit device can be weakened. Based on the basic parallel plate capacitor, in addition to the same parameters as the parallel plate in Table 1, the internal small triangle setting corrections are shown in Table 4. A pair of isosceles triangles with a side length of s = 20μm and an obtuse angle of 120° are added to the inside of the rectangular plate with a width of 425μm and a thickness of 90μm. If (0,0) is used as the initial position of the rectangular capacitor plate, then (0,0) is also used as the position of the isosceles triangle, which is rotated 90° at a positive angle and combined with the parallel plate capacitor. After setting the parameters, call HFSS for simulation, and the calculated capacitance matrix is shown in Table 14:

Table 14 Inner triangle capacitor simulation capacitor matrix

The capacitance matrix obtained by HFSS simulation can be used to approximate the capacitance value, decoherence time, bit frequency and other parameters of the inner triangle capacitor by using the LOM method. After 15 iterative calculations, the results are shown in Table 15. The T1 time increases from the original 230.865608μs to 237.054564μs, and the capacitance also increases slightly:

Table 15 Calculation results of triangular capacitance parameters in parallel plates

Property parameters value f 4.998405[GHz] EC 303.258391[MHz] EJ 11.671114[GHz] alpha -357.376520[MHz] dispersion 97.364514[KHz] Lq 13.994355[nH] C 63.873676[fF] T1 237.054564[μs]

Using HFSS to view the electric field distribution of the inner triangle capacitor structure, as shown in Figure 11, it is found that the electric field strength inside the capacitor plate is between 1.1567-1.3495E+10V/m, and the maximum electric field strength is only concentrated at the innermost Josephson junction of the capacitor. Adding triangles inside the parallel plate weakens the concentration of the electric field distribution, so it can be used as a reference to improve the capacitor shape.

As shown in Figure 12, the rounded parallel plate inner triangle capacitor is derived from the combination of the inner triangle capacitor and the rounded parallel plate capacitor. Since the simulation results of the above two capacitor shapes are good, the rectangular capacitor plate is rounded to reduce charge noise and energy dissipation. The small triangle inside can reduce the surface loss of the superconducting quantum device, so the decoherence time is greatly increased. Therefore, the two are combined to verify whether the capacitor has a better effect. Based on the extended rounded parallel plate capacitor and the inner triangle capacitor, the parameters are combined with Table 1, Table 3, and Table 4, and the specific implementation is shown in Table 5. On the one hand, the capacitor shape realizes the smooth processing of the capacitor, setting four circles with a radius of 30μm, splicing at the four corners of the rectangular plate with a width of 380μm and a thickness of 90μm, and the remaining part is spliced with a long plate with a width of 30μm and a thickness of 30μm. If (0,0) is used as the initial position of the rectangular capacitor plate, (±190, ±15)μm is also used as the position of the center of the spliced arc, and it is combined with the parallel plate capacitor respectively. On the other hand, a pair of isosceles triangles with a side length of s = 20 μm and an angle of 120° are added inside the rectangular plate. If (0, 0) is taken as the initial position of the rectangular capacitor plate, (0, 0) is also taken as the position of the isosceles triangle to combine with the parallel plate capacitor. After setting the parameters, call HFSS for simulation, and the calculated capacitance matrix is shown in Table 16:

Table 16 Simulated capacitance matrix of triangle capacitors in rounded parallel plates

The capacitance matrix obtained by HFSS simulation can be used to approximate the capacitance value, decoherence time, bit frequency and other parameters of the triangular capacitor in the rounded parallel plate with the help of the LOM method. After 15 iterative calculations, the results are shown in Table 17:

Table 17 Calculation results of the properties of the triangular capacitor in the rounded parallel plate

At the same time, the electric field distribution diagram of the triangular capacitor structure inside the rounded parallel plate can also be viewed through HFSS, as shown in Figure 13. The electric field range inside the capacitor plate is 1.1243-1.4054E+10V/m, which is lower than the 1.1309-1.4136E+10V/m before the small triangle was added.

Because the extension of the rounded capacitor increases the decoherence time, it changes the size of the capacitor. Therefore, two capacitor optimization directions can be summarized: First, the electric field strength distribution becomes weaker as the angle of the capacitor plate becomes smoother, so arcs can be used instead of right angles to reduce losses; second, adding triangular capacitors to the inside of the two plates can improve bit performance, so the capacitor can be optimized internally. Since the smoothness of the capacitor will affect the performance of the quantum bit and the decoherence time, but the lost capacitance is too large, we must find a way to make up for the loss of the capacitor. Try to put the arc on the inside of the two plates like the inner triangular capacitor, so as to avoid the loss of capacitance caused by the optimization of the parallel plate angle. Considering the above, referring to the design drawing of the new extended capacitor shown in Figure 14, the arc is added to the inside of the two plates. The specific parameter design is shown in Table 6. The capacitance matrix obtained by HFSS simulation can be used to approximate the capacitance value, decoherence time, bit frequency and other parameters of the extended capacitor with the help of the LOM method. The calculated simulation results are shown in Table 18:

Table 18 Calculation results of extended shape capacitance parameters

Property parameters value f 4.806487[GHz] EC 278.820648[MHz] EJ 11.671114[GHz] alpha -325.665845[MHz] dispersion 47.263011[KHz] Lq 13.994355[nH] C 69.472000[fF] T1 335.471349[μs]

The decoherence time of the simulation result of this extended shape capacitor increased from 226.35176us to 335.471349us, an increase of more than 100μs. It can also be seen from the current simulation data that the reason why the new shape can increase the decoherence time is that under the same size, this shape increases the capacitance value. Because the large-scale expansion of quantum bits cannot be at the expense of bit performance, it is necessary to maintain a fixed capacitance value and make the capacitor size as small as possible while ensuring the performance of quantum bits. Therefore, the capacitor size is adjusted, such as reducing the plate length, so that the decoherence time of the extended shape capacitor is maintained at about 226μs, which is equivalent to the parallel plate capacitor. The size comparison is: the area of the parallel plate capacitor is 425μm wide * 90μm high; the area of the new shape capacitor is 373μm wide * 90μm high. The width is shortened by 52μm, as shown in Figure 15.

Combining the advantages of the inner triangle capacitor, two small triangles are added to the inner side of the two arcs of the new shape to verify the performance of the coherence time. First, use qiskit-metal to draw a design drawing, as shown in Figure 16. The two plates are symmetrically interlaced with three arcs, and two triangles are set at the vertex of the arc in the center. The specific parameter settings are shown in Table 7. The capacitance matrix obtained by HFSS simulation can be used to approximate the capacitance value, decoherence time, bit frequency and other parameters of the inner triangle capacitor of the extended shape with the help of the LOM method. The calculated simulation results are shown in Table 19:

Table 19 Calculation results of the triangular capacitor parameters in the extended shape

Property parameters value f 4.792311[GHz] EC 277.062560[MHz] EJ 11.671114[GHz] alpha -323.404254[MHz] dispersion 44.701384[KHz] Lq 13.994355[nH] C 69.912832[fF] T1 344.272928[μs]

The decoherence time of the new extended capacitor with a small triangle inside is increased from 335.471349μs to 344.272928μs, and the improvement effect is more obvious. By reducing the plate width of the capacitor and controlling the decoherence time to about 227us, the size of the miniaturized capacitor is 369μm wide × 90μm high. While ensuring the performance of the superconducting quantum bit remains unchanged, the size is reduced by 56μm compared to the parallel plate capacitor, as shown in Figure 17. The electric field distribution of the extended capacitor is simulated using HFSS, as shown in Figure 18, where the maximum intensity electric field is concentrated in the center, about 7.9987E+09V/m-1.1198E+10V/m, which is lower than the electric field strength of other shape capacitors, indicating that this shape can effectively reduce dielectric loss and improve the electric field distribution. It can reduce the size of the parallel plate from 425μm to 369μm while keeping the decoherence time unchanged, thereby realizing the miniaturization of the capacitor.

In summary, in the embodiment of this case, the capacitor shape can be optimized by adopting the capacitor angle smoothing mechanism and the method of reducing dielectric loss to reduce the energy participation ratio, improve the superconducting quantum bit coherence time, and achieve the miniaturization of the capacitor while maintaining the superconducting quantum bit coherence time performance. It can be seen from the experimental data that compared with the parallel plate capacitor, the width of the new capacitor shape in this case is shortened from 425μm to 369μm, and the width is shortened by 56μm, accounting for 13.18% of the original parallel plate size. Based on the influence of the angle correction value, the decoherence time is changed by changing the degree of smoothness of the capacitor angle. When the angle of the parallel capacitor plate is smoother, the dielectric loss is smaller, and the decoherence time performance value is larger; at the same time, considering the lack of capacitor, the rounding treatment is placed on the inner side of the parallel plate, so that on the one hand, the surface size of the parallel plate capacitor is expanded and the dielectric loss is reduced; on the other hand, the capacitance value is increased to a certain extent; finally, combined with the excellent performance of the inner triangle capacitor, a pair of small triangles are added to the inner side of the two arcs, which can achieve smaller dielectric loss and optimize the electric field distribution. The electric field distribution is used to analyze the dielectric loss, and the decoherence time is used as a measure of the performance of the superconducting quantum bit. Through experimental comparison, the maximum electric field distribution can be reduced from 1.4271E+10V/m of the original parallel plate capacitor to 1.1198E+10V/m of the new shape capacitor, which can play a guiding and promoting role in further realizing the miniaturization of superconducting quantum bits.

Unless otherwise specifically stated, the relative steps, numerical expressions and values of the components and steps set forth in these embodiments do not limit the scope of the present invention.

In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

The units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation is not considered to be beyond the scope of the present invention.

Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk or an optical disk. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits, and accordingly, each module/unit in the above embodiment can be implemented in the form of hardware or in the form of software function modules. The present invention is not limited to any specific form of combination of hardware and software.

Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (9)

1. A method for miniaturizing the self-capacitance of a superconducting quantum bit, characterized by comprising the following contents: The capacitor width is used as a capacitor miniaturization criterion, and the basic parameters of the capacitor are set as constant values, the coherence time between the capacitors is set as an optimization index, and the capacitor shape is set as an adjustment optimization parameter, wherein the basic parameters of the capacitor at least include the parallel electrode plate size, the Josephson junction bandwidth, the parallel electrode plate interval, and the Josephson junction equivalent inductance and capacitance value; Use third-party simulation software to obtain the performance parameters of the capacitor under the current shape, change the properties of the superconducting quantum bit by adjusting the capacitor shape, and use the Q3D model simulation to obtain the Maxwell capacitor matrix under the current capacitor shape. According to the capacitor matrix and LOM superconducting quantum bit simulation, the approximate capacitance value and coherence time length are obtained; the electric field distribution and dielectric loss of the capacitor under the current shape are analyzed by establishing an electric field simulation diagram, where the performance parameters at least include: approximate capacitance value, coherence time length and electric field distribution, and the next optimization direction of the capacitor shape is selected according to the performance parameters; Based on the performance parameters before and after capacitor optimization, the capacitor shape with the best coherence time and electric field distribution is screened out, and the miniaturization effect is measured by comparing the size difference between the screened capacitor shape and the parallel plate capacitor. 2. The method for miniaturizing the self-capacitor of a superconducting quantum bit according to claim 1 is characterized in that the capacitor shape optimization direction includes: reducing the width of the parallel electrode plates and adjusting their shapes. 3. The method for miniaturizing the self-capacitor of a superconducting quantum bit according to claim 2 is characterized in that the capacitor shape optimization direction also includes: adjusting the number and shape of protrusions between parallel electrode plates. 4. A superconducting quantum bit self-capacitor, adopting a parallel plate capacitor structure, characterized in that the design is realized by using the method described in claim 1, comprising: a first electrode plate, a second electrode plate, a dielectric located between the first electrode plate and the second electrode plate, and control lines arranged on the first electrode plate and the second electrode plate, and an extended protrusion component that is symmetrically interwoven and used to prevent capacitance loss is arranged at the inner central part of the first electrode plate and the second electrode plate; the extended protrusion component includes protrusions and grooves that are arranged on the inner side surface of the first electrode plate and the inner side surface of the second electrode plate and are arranged correspondingly. 5 . The superconducting quantum bit self-capacitor according to claim 4 , wherein the protrusion has an arc-shaped cross-section. 6. The superconducting quantum bit self-capacitor according to claim 4 is characterized in that the protrusion on the second electrode plate is arranged in the middle of the inner side surface of the second electrode plate, the groove of the first electrode plate is arranged in the middle of the inner side surface of the first electrode plate, and the groove on the second electrode plate is symmetrically arranged along the center line of the protrusion of the second electrode plate, and the protrusion of the first electrode plate is symmetrically arranged along the center line of the groove of the first electrode plate. 7. The superconducting quantum bit self-capacitor according to claim 4 is characterized in that the extended protrusion component also includes: triangular capacitor protrusions respectively arranged on the inner side surfaces of the first electrode plate and the second electrode plate for increasing the decoherence time. 8. The superconducting quantum bit self-capacitor according to claim 7 is characterized in that the triangular capacitor protrusion is respectively arranged at the center of the middle groove on the inner side of the first electrode plate and the center of the middle protrusion on the inner side of the second electrode plate, or respectively arranged at the center of the middle protrusion on the inner side of the first electrode plate and the center of the middle groove on the inner side of the second electrode plate. 9. The superconducting quantum bit self-capacitor according to claim 7 is characterized in that the triangular capacitor protrusion adopts a structure with a cross-section of an isosceles triangle.