CN115965087B - Superconducting qubit self-capacitance miniaturized design method and superconducting qubit self-capacitance - Google Patents
Superconducting qubit self-capacitance miniaturized design method and superconducting qubit self-capacitance Download PDFInfo
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Abstract
The invention belongs to the technical field of superconducting quantum computing, and particularly relates to a superconducting quantum bit self-capacitance miniaturization design method and a superconducting quantum bit self-capacitance, wherein the width of the capacitance is used as a capacitance miniaturization measurement standard, basic parameters of the capacitance are set to be constant values, and the shape of the capacitance is set to be an adjustment optimization parameter; acquiring a capacitive performance parameter under the current shape by means of third-party simulation software, wherein the performance parameter at least comprises: approximating the capacitance value, the coherence time length and the electric field distribution, and selecting a capacitance shape according to the performance parameters for the next optimization direction; and screening out the capacitance shape with optimal coherence time and optimal electric field distribution according to the performance parameters before and after capacitance optimization, and measuring the miniaturization effect by comparing the screened capacitance shape with the size difference between the parallel plate capacitance. The invention can realize the miniaturization design of self capacitance while keeping the coherence time of the superconducting qubit so as to meet the application in the current integration of the superconducting qubit chip.
Description
Technical Field
The invention belongs to the technical field of superconducting quantum computing, and particularly relates to a superconducting quantum bit self-capacitance miniaturized design method and a superconducting quantum bit self-capacitance.
Background
Superconducting qubits have received extensive attention since their proposal and are considered to be one of the best candidate systems for realizing large-scale practical quantum computation in the future. Current superconducting qubit designs employ large coplanar parallel plate capacitors for diluting the energy contribution of the non-crystal interface dielectric. The capacitor structure has the following problems: 1. the large single quantum scale and the complexity of microwave design. Parasitic capacitive coupling between parallel plate capacitances can result in stray quantum bit coupling, increasing coherence errors, and affecting the fidelity of the quantum bit. 2. The integration of superconducting qubit chips is limited. Fault tolerant quantum computing requires a huge number of physical bits to implement, and in the foreseeable future, the number of bits in a superconducting quantum chip will increase rapidly, so that the requirement on the integration level of the superconducting quantum chip is higher. Since the qubits on a single chip are currently limited, the size of the qubits is also limited. 3. Problems with increased integration: charge noise, circuit crosstalk, loss affect the performance of superconducting qubits.
Disclosure of Invention
Therefore, the invention provides a superconducting qubit self-capacitance miniaturization design method and a superconducting qubit self-capacitance, which can realize miniaturization design of the self-capacitance while maintaining the coherent time of superconducting qubits so as to meet the application of the current superconducting qubit chip integration.
According to the design scheme provided by the invention, the superconducting qubit self-capacitance miniaturized design method comprises the following steps:
Taking the width as a capacitance miniaturization measurement standard, setting basic parameters of the capacitance as constant values, setting the coherence time between the capacitances as an optimization index, and setting the shape of the capacitance as an adjustment optimization parameter, wherein the basic parameters of the capacitance at least comprise the dimension of a parallel electrode plate, the broadband of a Josephson junction, the interval of the parallel electrode plate and the equivalent inductance capacitance value of the Josephson junction;
Acquiring a capacitive performance parameter under the current shape by means of third-party simulation software, wherein the performance parameter at least comprises: approximating the capacitance value, the coherence time length and the electric field distribution, and selecting a capacitance shape according to the performance parameters for the next optimization direction;
And screening out the capacitance shape with optimal coherence time and optimal electric field distribution according to the performance parameters before and after capacitance optimization, and measuring the miniaturization effect by comparing the screened capacitance shape with the size difference between the parallel plate capacitance.
As the superconducting qubit self-capacitance miniaturized design method in the invention, further, in the process of obtaining capacitance performance parameters under the current shape by means of third party simulation software, changing the properties of superconducting qubits by adjusting the capacitance shape, obtaining a Max Wei Dianrong matrix under the current capacitance shape by means of Q3D model simulation, and obtaining an approximate capacitance value and a coherence time length according to the capacitance matrix and LOM superconducting qubit simulation; the electric field distribution and dielectric loss of the capacitor in the current shape are analyzed by establishing an electric field simulation diagram.
As the superconducting qubit self-capacitance miniaturization design method in the invention, the optimization direction of the capacitance shape further comprises: the width of the parallel electrode plate is reduced and the shape is adjusted.
As the superconducting qubit self-capacitance miniaturization design method in the invention, the capacitance shape optimization direction further comprises the following steps: and adjusting the number and the shape of the bulges between the parallel electrode plates.
Furthermore, the invention also provides a superconducting qubit self-capacitance, which adopts a parallel plate capacitance structure, and realizes design by using the method, comprising the following steps: the capacitor comprises a first electrode plate, a second electrode plate, a dielectric medium positioned between the first electrode plate and the second electrode plate, and a control line arranged on the first electrode plate and the second electrode plate, wherein extension convex components which are mutually symmetrically interweaved and are used for preventing the loss of capacitance are arranged at the central parts of the inner sides of the first electrode plate and the second electrode plate; the expansion bulge component comprises bulges and grooves which are respectively arranged on the inner side surface of the first electrode plate and the inner side surface of the second electrode plate and are correspondingly arranged.
As the superconducting qubit self-capacitance, the bulge adopts a bulge structure with an arc-shaped section.
As the superconducting qubit self-capacitance, further, the bulges on the second electrode plate are arranged in the middle of the inner side surface of the second electrode plate, the grooves of the first electrode plate are arranged in the middle of the inner side surface of the first electrode plate, the grooves on the second electrode plate are symmetrically arranged along the central line of the bulges of the second electrode plate, and the bulges of the first electrode plate are symmetrically arranged along the central line of the grooves of the first electrode plate.
As the superconducting qubit self-capacitance of the invention, further, the expansion bump component further comprises: triangular capacitor protrusions which are respectively arranged on the inner side surfaces of the first electrode plate and the second electrode plate and used for increasing decoherence time.
As the superconducting qubit self-capacitance, the triangular capacitance bulge is arranged at the center of the middle groove of the inner side surface of the first electrode plate and the center of the middle bulge of the inner side surface of the second electrode plate, or respectively arranged at the center of the middle bulge of the inner side surface of the first electrode plate and the center of the middle groove of the inner side surface of the second electrode plate.
As the superconducting qubit self-capacitance, the triangular capacitor bulge adopts a structure with an isosceles triangle cross section.
The invention has the beneficial effects that:
On the premise of ensuring the properties of superconducting qubits, the invention adds fillets, triangular structures and the like into a large coplanar parallel plate by changing the shape of the capacitor, changes the properties of the superconducting qubits by miniaturizing the shape of the capacitor, and meets the application in the integration of superconducting qubit chips; the superconducting qubit self-capacitance designed in a miniaturized manner can be applied to integration of a quantum chip by enlarging the surface size of a parallel plate capacitor, reducing dielectric loss and increasing the capacitance value to a certain extent on the premise of ensuring the capacitance performance.
Description of the drawings:
FIG. 1 is a schematic flow chart of a superconducting qubit self-capacitance miniaturized design in an embodiment;
FIG. 2 is a schematic diagram of a design principle of capacitor miniaturization in an embodiment;
FIG. 3 is a schematic diagram of a superconducting qubit self-capacitance structure in an embodiment;
FIG. 4 is a schematic diagram of a parallel plate capacitance design in an embodiment;
FIG. 5 is a schematic representation of a parallel plate capacitance electric field profile in an embodiment;
FIG. 6 is a schematic diagram of an elliptical parallel plate capacitance design in an embodiment;
FIG. 7 is a schematic diagram of an elliptical parallel plate capacitive electric field profile in an embodiment;
FIG. 8 is a schematic diagram of a parallel plate capacitor corner rounding scheme in an embodiment;
FIG. 9 is a schematic diagram showing an electric field distribution diagram of a parallel plate capacitor after four corners of the parallel plate capacitor are rounded in an embodiment;
FIG. 10 is a schematic diagram of a design in which triangular protrusions are added to parallel plates in an embodiment;
FIG. 11 is a schematic diagram showing an electric field distribution diagram of a parallel plate with triangular protrusions added thereto in the embodiment;
FIG. 12 is a schematic diagram of a design for adding delta capacitance to a rounded parallel plate in an embodiment;
FIG. 13 is a graph showing the electric field distribution after adding delta capacitance to the rounded parallel plates in the example;
FIG. 14 is a schematic diagram of a novel extended capacitance design with the addition of circular arc protrusions in an embodiment;
FIG. 15 is a comparative illustration of the dimensions of two capacitive products with the addition of circular arc protrusions in the example;
FIG. 16 is a schematic diagram of a design for adding triangular capacitor bumps and circular arc bumps in an embodiment;
FIG. 17 is a comparative illustration of the dimensions of two capacitive products with triangular capacitive bumps and circular arc bumps added in the example;
Fig. 18 is a schematic diagram showing an electric field distribution diagram after adding triangular capacitor bumps and arc bumps in the embodiment.
In the drawings, reference numeral 1 denotes a first electrode plate, reference numeral 2 denotes a second electrode plate, reference numeral 3 denotes a dielectric, and reference numeral 4 denotes a control line pin.
The specific embodiment is as follows:
The present invention will be described in further detail with reference to the drawings and the technical scheme, in order to make the objects, technical schemes and advantages of the present invention more apparent.
Referring to fig. 1, an embodiment of the present invention provides a superconducting qubit self-capacitance miniaturized design method, including:
s101, taking the width as a capacitance miniaturization measurement standard, setting basic parameters of the capacitance as constant values, setting the coherence time between the capacitances as an optimization index, and setting the shape of the capacitance as an adjustment optimization parameter, wherein the basic parameters of the capacitance at least comprise the dimension of a parallel electrode plate, the broadband of a Josephson junction, the interval of the parallel electrode plate and the equivalent inductance capacitance value of the Josephson junction;
S102, acquiring a capacitance performance parameter under the current shape by means of third-party simulation software, wherein the performance parameter at least comprises: approximating the capacitance value, the coherence time length and the electric field distribution, and selecting a capacitance shape according to the performance parameters for the next optimization direction;
and S103, screening out a capacitance shape with optimal coherence time and optimal electric field distribution according to performance parameters before and after capacitance optimization, and measuring the miniaturization effect by comparing the screened capacitance shape with the size difference between parallel plate capacitances.
Setting each parameter of the capacitor to be a constant value, adding fillets, triangular structures and the like into a large coplanar parallel plate by changing the shape of the capacitor, changing the property of the superconducting quantum bit by miniaturizing the shape of the capacitor, and meeting the application of the superconducting quantum bit chip integration. Further, in the process of acquiring the capacitance performance parameters under the current shape by means of third-party simulation software, changing the superconducting qubit property by adjusting the capacitance shape, acquiring a Max Wei Dianrong matrix under the current capacitance shape by means of Q3D model simulation, and acquiring an approximate capacitance value and a coherence time length according to the capacitance matrix and LOM superconducting qubit simulation; the electric field distribution and dielectric loss of the capacitor in the current shape are analyzed by establishing an electric field simulation diagram.
Referring to fig. 2, since the miniaturization of the capacitor takes the coherence time as a measurement standard, the coherence time of the novel capacitor and the parallel capacitor can be compared, and the control variable method is adopted to keep the parameters except the shape constant; on the premise of ensuring bit properties, the properties of superconducting quantum bits are changed by changing the shape of a capacitor and adding fillets, triangular structures and the like into a large coplanar parallel plate. For example, the parallel plate capacitance can be set according to the parameters shown in table 1, there are three control lines, there can be three corresponding plates connected, the width and equivalent inductance of the josephson junction, the parallel plate height, the plate width, etc. are set as follows:
Table 1 basic parameter setting table
| Parameter name | Value of | |
| Parallel plate capacitance spacing | pad_gap | 30um |
| Josephson junction width | inductor_width | 20um |
| Width of parallel plate facing | pad_width | 425um |
| Height of parallel plate | pad_height | 90um |
| Bag width | pocket_width | 650um |
| Bag height | pocket_height | 650um |
| Offset of x-axis | pos_x | 0.5mm |
| Offset of y-axis | pos_y | 0.5mm |
| readout pad | pad_gap | 15um |
| cl pad | pad_width | 125um |
| bus pad | pad_heigh | 30um |
| Josephson junction inductance | Lj | 14nH |
| Josephson junction capacitance | Cj | 2fF |
| Resonant cavity readout frequency | freq_readout | 7.0GHz |
The specific design parameters for elliptical capacitance different from the base parameters can be as shown in table 2:
Table 2 elliptic capacitance parameter table
The specific design parameters of the fillet capacitor after the oval capacitor is optimized can be shown in table 3:
TABLE 3 fillet capacitance correction parameter Table
The specific design parameters for the inner delta capacitance different from the base parameters can be as shown in table 4:
Table 4 inner triangle capacitance parameter table
| Parameter name | Value of | |
| Triangle side length | s | 20μm |
| Triangle obtuse angle | a | 120° |
The specific design parameters of the capacitor after the combination of the inner triangular capacitor and the rounded corner capacitor is optimized can be shown in table 5:
TABLE 5 fillet combined inner triangle capacitance parameter table
The specific design parameters of the miniaturized design of the capacitor different from the basic parameters in this embodiment can be shown in table 6:
TABLE 6 extended shape capacitance parameter table
| Parameter name | Value of | |
| Radius of circle | radius | 10μm |
| Number of circular arcs | n | 3 |
The parameter adjustment of the capacitance after the optimization of the new shape capacitance can be as follows in table 7:
TABLE 7 extended shape inner triangle capacitance parameter table
| Parameter name | Value of | |
| Radius of circle | radius | 30μm |
| Number of circular arcs | n | 3 |
| Triangle side length | s | 10μm |
| Triangular offset | pad_gap/2+radius | 45μm |
By adjusting the shape of the capacitor, a design diagram is drawn, and the shape can be finely adjusted by qiskit-metal, so that preparation is made for the next step of simulation analysis of the capacitor and calculation of coherence time; the Max Wei Dianrong matrix can be obtained by means of Q3D model simulation, and the approximate capacitance value and the coherence time length can be obtained by means of capacitance matrix and LOM superconducting quantum bit simulation calculation; establishing an electric field simulation image by means of an HFSS simulation method, and analyzing electric field distribution and dielectric loss of the capacitor, so that a basis is provided for further design of capacitor miniaturization; the capacitance value, the coherence time and the electric field distribution result are combined and analyzed, the advantages and disadvantages of each shape are measured, and the optimization direction of the next capacitor shape is selected by combining the advantages of each shape; and continuously updating and perfecting the capacitance shape, and screening the capacitance with optimal coherence time and best electric field distribution condition, thereby obtaining the capacitance shape with optimal superconducting quantum bit performance under the current capacitance parameter setting. The miniaturisation effect can be measured by comparing the size difference between the novel capacitance shape and the parallel plate capacitance.
Based on the above method, the embodiment of the present invention further provides a superconducting qubit self-capacitance, which adopts a parallel plate capacitance structure, and includes: the capacitor comprises a first electrode plate, a second electrode plate, a dielectric medium positioned between the first electrode plate and the second electrode plate, and a control line arranged on the first electrode plate and the second electrode plate, wherein extension convex components which are mutually symmetrically interweaved and are used for preventing the loss of capacitance are arranged at the central parts of the inner sides of the first electrode plate and the second electrode plate; the expansion bulge component comprises bulges and grooves which are respectively arranged on the inner side surface of the first electrode plate and the inner side surface of the second electrode plate and are correspondingly arranged.
Referring to the structure shown in fig. 3, the electric field distribution can be optimized, wherein the protrusions adopt a protrusion structure with an arc-shaped cross section. The protrusion on the second electrode plate is arranged in the middle of the inner side surface of the second electrode plate, the groove of the first electrode plate is arranged in the middle of the inner side surface of the first electrode plate, the groove on the second electrode plate is symmetrically arranged along the protrusion center line of the second electrode plate, and the protrusion of the first electrode plate is symmetrically arranged along the groove center line of the first electrode plate. The expansion protrusion assembly further comprises: triangular capacitor protrusions which are respectively arranged on the inner side surfaces of the first electrode plate and the second electrode plate and used for increasing decoherence time. The triangular capacitor bulge is respectively arranged at the center of the middle groove of the inner side surface of the first electrode plate and the center of the middle bulge of the inner side surface of the second electrode plate, or respectively arranged at the center of the middle bulge of the inner side surface of the first electrode plate and the center of the middle groove of the inner side surface of the second electrode plate. The triangular capacitor protrusions can be of a structure with isosceles triangle cross sections.
To verify the validity of this protocol, the following is further explained in connection with experimental data:
the design based on classical parallel plate capacitance is shown in fig. 4, where three control lines line two sides of a large parallel plate place the capacitance in the center of the pocket. The GDS file of the parallel plate capacitance is imported into HFSS software for simulation, and a capacitance matrix of the parallel plate capacitance is obtained and is shown in a table 8, wherein diagonal lines represent capacitance values of the plates per se and are constant positive; the off-diagonal line represents the coupling capacitance value of any two parts, which is constant negative:
TABLE 8 parallel plate capacitance simulation capacitance matrix
The capacitance matrix obtained through HFSS simulation can be used for approximately solving parameters such as bit capacitance, decoherence time, bit frequency and the like by means of an LOM method, and after 15 iterative calculations, the results are shown in Table 9:
TABLE 9 parallel plate capacitance parameter calculation results
| Property parameter | Value of |
| f_Q | 5.021551[GHz] |
| EC | 306.286385[MHz] |
| EJ | 11.671114[GHz] |
| alpha | -361.341682[MHz] |
| dispersion | 105.828700[KHz] |
| Lq | 13.994355[nH] |
| Cq | 63.242211[fF] |
| T1 | 226.351758[μs] |
The Q3D parallel plate capacitance model consists of a 430mm thick sapphire substrate and surface parallel plate capacitance, coupling capacitance, pocket, josephson junction and bridge section. The mag_e field distribution image is plotted by HFSS as in fig. 5. Since the electric field distribution is related to the size of the capacitor, the larger the size, the weaker the surface loss effect of the qubit device. Therefore, the electric field distribution of the parallel plate capacitance is used as a reference, and the electric field distribution changes in different capacitance shapes are compared. As can be seen from FIG. 5, the intra-plate electric field of the parallel plate capacitor ranges from 1.1417 to 1.4271E+10V/m, focusing mainly on the middle of the two parallel plates, the closer to the internal electric field strength is more pronounced.
The elliptical parallel plate capacitor shown in fig. 6, the rectangular capacitor plate is rounded to reduce charge noise and energy dissipation and to extend decoherence time, but this affects miniaturization of the capacitor design volume at the expense of the capacitor. The other parameters are shown in table 2, except for the same parameters as in table 1. To achieve smooth processing of the capacitor, a semicircle with a radius of 45 μm (where r=pad_height/2) is added to the left and right sides of a rectangular plate with a width of 335 μm and a thickness of 90 μm, respectively, and the total length is kept to be 425 μm, which is the same as the capacitance parameter of the basic parallel plate. If (0, 0) is used as the initial position of the rectangular capacitor plate, the positions of the centers of the two semicircles are used as (0.1675 mm, 0) and (-0.1675 mm, 0), and the two semicircles are combined with the parallel plate capacitor. After setting the parameters, the HFSS is called for simulation, and the calculated capacitance matrix is shown in table 10:
table 10 simulation capacitance matrix of elliptical parallel plate capacitance
The capacitance matrix obtained through HFSS simulation can be used for approximately solving the parameters such as the capacitance value, decoherence time, bit frequency and the like of the elliptical parallel plate capacitance by means of an LOM method, and the results are shown in table 11 after 15 iterative calculations:
TABLE 11 calculation of elliptical parallel plate capacitance parameters
| Property parameter | Value of |
| f_Q | 5.157391[GHz] |
| EC | 324.411849[MHz] |
| EJ | 11.671114[GHz] |
| alpha | -385.246118[MHz] |
| dispersion | 169.977097[KHz] |
| Lq | 13.994355[nH] |
| Cq | 59.708757[fF] |
| T1 | 198.341307[μs] |
Meanwhile, the electric field distribution diagram of the elliptical parallel plate capacitance structure can also be checked through HFSS, as shown in FIG. 7. The electric field concentration is distributed in the internal Josephson junction, and the electric field distribution in the plate of the elliptical parallel plate is 1.1412-1.4265E+10V/m, which is reduced compared with the electric field range 1.1417-1.4271E+10V/m of the parallel plate capacitance. Due to the excessive reduction of the elliptical capacitance size, the capacitance value is greatly affected, thereby changing the properties of the qubit.
Referring to FIG. 8, four corners of the parallel plate are changed into smooth arc shapes, so that the area lost in the smooth process is reduced, the capacitance value is increased, and the decoherence time is prevented from being excessively reduced. It is based on the basic parallel plate capacitance, and the four fillet settings are modified as shown in table 3, except for the same parameters as the parallel plates in table 1. Four corners of a rectangular plate 425 μm wide and 90 μm thick were rounded: four circles with the radius of 30 μm are arranged, the four corners of a rectangular plate with the width of 365 μm and the thickness of 90 μm are spliced, and the spare parts are spliced by a long plate with the width of 30 μm and the thickness of 30 μm. If (0, 0) is used as the initial position of the rectangular capacitor plate, the position of the center of the spliced arc is also used as (+ -182.5, +/-15) mu m, and the positions are respectively combined with the parallel plate capacitors. After setting the parameters, the HFSS is called for simulation, and the calculated capacitance matrix is shown in table 12:
table 12 modified fillet capacitance simulation capacitance matrix
The capacitance matrix obtained through HFSS simulation can be used for approximately solving parameters such as the capacitance value, decoherence time, bit frequency and the like of the corrected fillet capacitance by means of an LOM method, and after 15 iterative calculations, the result is shown in a table 13, the time T1 is increased from the original 198.341307 mu s to 211.456076 mu s, and the capacitance is also increased to 61.440766fF:
Table 13 calculation results of fillet capacitance parameters after correction
| Property parameter | Value of |
| f_Q | 5.089424[GHz] |
| EC | 315.266711[MHz] |
| EJ | 11.671114[GHz] |
| alpha | -373.148807[MHz] |
| dispersion | 134.532106[KHz] |
| Lq | 13.994355[nH] |
| Cq | 61.440766[fF] |
| T1 | 211.456076[μs] |
Looking at the electric field distribution diagram of the modified rounded capacitor structure through HFSS, as shown in FIG. 9, the electric field intensity inside the capacitor plate is 1.1309-1.4136V/m, and the maximum electric field intensity is concentrated in the center inside the capacitor, which is reduced compared with 1.1417-1.4271E+10V/m of the parallel plate capacitor. It is explained that the parallel plate angle becomes smooth in a certain range, and the surface loss of the quantum device becomes small. Because the loss of capacitance is larger in the rounding process, if the holding capacitance is the same as the common parallel plate capacitance, the length of the rounded capacitance is prolonged to 440 mu m, and the calculated parameters are shown in table 4.13, wherein the decoherence time is 240.200063us, which is increased by 6.12% compared with 226.351758us of the parallel plate capacitance and is increased by 13.59% compared with 211.456076us of the rounded capacitance.
Referring to fig. 10, a capacitor bump having a trapezoid or triangle shape is added inside two parallel plates to increase decoherence time. The surface loss of the qubit device can be weakened due to the fact that the small triangle inside the rectangle is added. Based on the base parallel plate capacitance, the internal small triangle setup was modified as shown in table 4, except for the same parameters as the parallel plates in table 1. A pair of isosceles triangles with sides s=20μm and obtuse angles of 120 degrees are added in a rectangular plate with a width of 425 μm and a thickness of 90 μm, and if (0, 0) is taken as the initial position of the rectangular capacitor plate, the position of the isosceles triangle is also taken as the position of the (0, 0), and the isosceles triangle is rotated by 90 degrees in the forward direction and then combined with the parallel plate capacitor. After setting the parameters, the HFSS is called for simulation, and the calculated capacitance matrix is shown in table 14:
table 14 inner triangle capacitance simulation capacitance matrix
The capacitance matrix obtained through HFSS simulation can be used for approximately solving parameters such as the capacitance value, decoherence time, bit frequency and the like of the inner triangular capacitance by means of an LOM method, and after 15 iterative calculations, the result is shown in a table 15, the time T1 is increased from the original 230.865608 mu s to 237.054564 mu s, and the capacitance is slightly increased:
TABLE 15 calculation of parallel plate internal triangle capacitance parameters
| Property parameter | Value of |
| f_Q | 4.998405[GHz] |
| EC | 303.258391[MHz] |
| EJ | 11.671114[GHz] |
| alpha | -357.376520[MHz] |
| dispersion | 97.364514[KHz] |
| Lq | 13.994355[nH] |
| Cq | 63.873676[fF] |
| T1 | 237.054564[μs] |
Looking at the electric field profile of the inner delta capacitance structure by HFSS, as shown in FIG. 11, the electric field strength inside the capacitive plate was found to be between 1.1567-1.3495E+10V/m, with the maximum electric field strength only concentrated at the Josephson junction at the innermost part of the capacitance. The addition of triangles in the parallel plates reduces the concentration of the electric field distribution, thus allowing for reference to improve the capacitance shape.
As shown in FIG. 12, the rounded parallel plate inner triangle capacitor is derived from the combination of the inner triangle capacitor and the rounded parallel plate capacitor, and because the simulation result effect of the two capacitor shapes is better, the rectangular capacitor plate is smoothly processed, so that the charge noise and the energy dissipation can be reduced, the surface loss of the superconducting quantum device can be reduced by adding a small triangle inside, and the decoherence time is greatly increased, so that the two capacitors are combined to verify whether the capacitor has a better effect. Based on the extended rounded parallel plate capacitance and the inner triangular capacitance, the parameters are combined with tables 1, 3, and 4, and the specific implementation is shown in table 5. On the other hand, the capacitor shape realizes smooth treatment of the capacitor, four circles with the radius of 30 μm are arranged, the four corners of a rectangular plate with the width of 380 μm and the thickness of 90 μm are spliced, and the spare parts are spliced by a long plate with the width of 30 μm and the thickness of 30 μm. If (0, 0) is used as the initial position of the rectangular capacitor plate, the position of the center of the spliced arc is also used as the position of the circle center of (+ -190, +/-15) mu m, and the positions are respectively combined with the parallel plate capacitors. On the other hand, a pair of isosceles triangles with side lengths s=20μm and angles of 120 ° are added inside the rectangular plate, and if (0, 0) is taken as the initial position of the rectangular capacitor plate, the position where (0, 0) is also taken as the isosceles triangle is combined with the parallel plate capacitor. After setting the parameters, the HFSS is called for simulation, and the calculated capacitance matrix is shown in table 16:
table 16 fillet parallel plate inner triangle capacitance simulation capacitance matrix
The capacitance matrix obtained through HFSS simulation can be used for approximately solving parameters such as capacitance value, decoherence time, bit frequency and the like of the triangular capacitance in the circular-angle parallel plate by means of an LOM method, and after 15 iterative calculations, the results are shown in Table 17:
TABLE 17 calculation of delta capacitance bit property parameters in rounded parallel plates
Meanwhile, the electric field distribution diagram of the triangular capacitance structure in the circular-angle parallel plate can be also checked through HFSS, as shown in FIG. 13, the electric field range in the capacitance plate is 1.1243-1.4054E+10V/m, and compared with 1.1309-1.4136E+10V/m before the small triangle is added, the electric field distribution diagram is reduced.
Because of the extension of the corner capacitance, the size of the capacitance is changed, although the decoherence time is increased. Thus, two capacitance optimization directions can be summarized: firstly, the electric field intensity distribution is weaker along with the smoother angle of the capacitor plate, and the circular arc can be used for replacing a right angle, so that the loss is weakened; secondly, the triangular capacitor is added on the inner sides of the two plates, so that the bit performance can be improved, and the capacitor can be internally optimized. The smoothness of the capacitor can influence the performance of the qubit and the decoherence time, but the lost capacitor is too large, and a method for compensating the capacitor is also required. Attempts to place the circular arc inside both plates like an inner triangle capacitor can avoid the lack of capacitance due to the optimization of parallel plate angle. To sum up, referring to the new design drawing of the extended capacitor shown in fig. 14, the circular arc is added to the inner sides of the two plates, the specific parameter design is shown in table 6, the capacitance value, decoherence time, bit frequency and other parameters of the extended capacitor can be approximately obtained by means of the LOM method through the capacitance matrix obtained by HFSS simulation, and the simulation result obtained by calculation is shown in table 18:
table 18 expanded shape capacitance parameter calculation results
| Property parameter | Value of |
| f_Q | 4.806487[GHz] |
| EC | 278.820648[MHz] |
| EJ | 11.671114[GHz] |
| alpha | -325.665845[MHz] |
| dispersion | 47.263011[KHz] |
| Lq | 13.994355[nH] |
| Cq | 69.472000[fF] |
| T1 | 335.471349[μs] |
The decoherence time of the capacitance simulation result of the extended shape is increased from 226.35176us to 335.471349us, and the decoherence time is increased by more than 100 mu s. From the data of the current simulation, it can also be seen that the new shape can increase the decoherence time because: this shape increases the capacitance value with the same size. Because of the large-scale expansion of the qubits, the capacitor value needs to be kept constant on the premise of ensuring the performance of the qubits at the cost of losing the bit performance, so that the capacitor size is as small as possible. The capacitance size is adjusted, e.g. the plate length is reduced, so that the decoherence time of the extended shape capacitance is kept around 226 mus, which is comparable to the parallel plate capacitance. The size contrast is: the area of the parallel plate capacitance is 425 μm wide by 90 μm high; the area of the newly shaped capacitor is 373 μm wide by 90 μm high. The width is shortened by 52 μm as shown in fig. 15.
And by combining the advantages of the inner triangular capacitor, two opposite small triangles are added on the inner sides of two circular arcs of the new shape, and the performance of the coherence time is verified. The design is first drawn using qiskit-metal, as in FIG. 16. Wherein the two plates are respectively and symmetrically interwoven with three circular arcs, two triangles are set up at the circular arc vertexes at the center, specific parameter settings are shown in table 7, the capacitance matrix obtained through HFSS simulation can be approximately obtained by means of LOM method to obtain parameters such as capacitance value, decoherence time, bit frequency and the like of the triangular capacitor in the extended shape, and the simulation results obtained through calculation are shown in table 19:
TABLE 19 calculation of triangular capacitance parameters within the expanded shape
| Property parameter | Value of |
| f_Q | 4.792311[GHz] |
| EC | 277.062560[MHz] |
| EJ | 11.671114[GHz] |
| alpha | -323.404254[MHz] |
| dispersion | 44.701384[KHz] |
| Lq | 13.994355[nH] |
| Cq | 69.912832[fF] |
| T1 | 344.272928[μs] |
The decoherence time of the expansion capacitor with the new shape after the small triangle is internally added is increased from 335.471349 mu s to 344.272928 mu s, and the improvement effect is more obvious. The width of the capacitor was reduced, and the decoherence time was controlled to be about 227us, so that the size of the resulting miniaturized capacitor was 369 μm wide by 90 μm high. The size of the parallel plate capacitor is reduced by 56 μm with the guarantee of constant superconducting qubit performance, as shown in fig. 17. The electric field distribution of the extended capacitance was simulated by using HFSS, as shown in FIG. 18, in which the maximum electric field intensity is concentrated at the center, and the electric field intensity is about 7.9987E+09V/m-1.1198E+10V/m, which is lower than that of the capacitance of other shapes, indicating that the shape can effectively reduce dielectric loss, improve the electric field distribution condition, and reduce the size of the parallel plate from 425 μm to 369 μm under the condition of keeping the decoherence time unchanged, thereby realizing the miniaturization of the capacitance.
In summary, in the embodiment of the present disclosure, the capacitance shape may be optimized by adopting a capacitance angle smoothing mechanism and a method for reducing dielectric loss, so as to reduce the energy participation ratio, improve the coherence time of the superconducting qubit, and achieve miniaturization of the capacitance under the condition of keeping the coherence time of the superconducting qubit. As shown by experimental data, compared with a parallel plate capacitor, the width of the novel shape of the capacitor is shortened from 425 micrometers to 369 micrometers, and the width is shortened by 56 micrometers, so that the novel shape of the capacitor accounts for 13.18 percent of the size of the original parallel plate. Based on the influence of the angle correction value, the decoherence time is changed by changing the smoothness of the capacitance angle, and the smaller the angle of the parallel capacitance plate is, the smaller the dielectric loss is, and the larger the decoherence time representation value is; meanwhile, considering the defect of the capacitor, the smoothing treatment is arranged on the inner side of the parallel plate, so that the surface size of the parallel plate capacitor is enlarged and the dielectric loss is reduced; on the other hand, the capacitance value is increased to a certain extent; finally, in combination with the excellent performance of the inner triangular capacitor, a pair of small triangles are added on the inner sides of the two circular arcs, so that smaller dielectric loss can be realized, and the electric field distribution condition is optimized. The dielectric loss is analyzed by adopting electric field distribution, the performance of decoherence time is used as a measure of superconducting quantum bit performance, and the maximum electric field distribution can be reduced from 1.4271E+10V/m of the original parallel plate capacitance to 1.1198E+10V/m of the new shape capacitance through experimental comparison, so that the superconducting quantum bit performance can be further miniaturized, and the superconducting quantum bit performance is guided and promoted.
The relative steps, numerical expressions and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
The elements and method steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or a combination thereof, and the elements and steps of the examples have been generally described in terms of functionality in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Those of ordinary skill in the art may implement the described functionality using different methods for each particular application, but such implementation is not considered to be beyond the scope of the present invention.
Those of ordinary skill in the art will appreciate that all or a portion of the steps in the above methods may be performed by a program that instructs associated hardware, and that the program may be stored on a computer readable storage medium, such as: read-only memory, magnetic or optical disk, etc. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits, and accordingly, each module/unit in the above embodiments may be implemented in hardware or may be implemented in a software functional module. The present invention is not limited to any specific form of combination of hardware and software.
Finally, it should be noted that: the above examples are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, but it should be understood by those skilled in the art that the present invention is not limited thereto, and that the present invention is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A superconducting qubit self-capacitance miniaturized design method is characterized by comprising the following steps:
Taking the width of the capacitor as a capacitance miniaturization measurement standard, setting basic parameters of the capacitor as constant values, setting the coherence time between the capacitors as an optimization index, and setting the shape of the capacitor as an adjustment optimization parameter, wherein the basic parameters of the capacitor at least comprise the dimension of a parallel electrode plate, the broadband of a Josephson junction, the interval of the parallel electrode plate and the equivalent inductance-capacitance value of the Josephson junction;
Acquiring capacitance performance parameters under the current shape by means of third-party simulation software, changing superconducting qubit properties by adjusting the capacitance shape, acquiring a Max Wei Dianrong matrix under the current capacitance shape by means of Q3D model simulation, and acquiring an approximate capacitance value and a coherence time length according to the capacitance matrix and LOM superconducting qubit simulation; and analyzing the electric field distribution and dielectric loss of the capacitor under the current shape by establishing an electric field simulation diagram, wherein the performance parameters at least comprise: approximating the capacitance value, the coherence time length and the electric field distribution, and selecting a capacitance shape according to the performance parameters for the next optimization direction;
And screening out the capacitance shape with optimal coherence time and optimal electric field distribution according to the performance parameters before and after capacitance optimization, and measuring the miniaturization effect by comparing the screened capacitance shape with the size difference between the parallel plate capacitance.
2. The method for miniaturized design of superconducting qubit self-capacitance according to claim 1, wherein the capacitance shape optimization direction comprises: the width of the parallel electrode plate is reduced and the shape is adjusted.
3. The superconducting qubit self-capacitance miniaturization design method according to claim 2, wherein the capacitance shape optimization direction further comprises: and adjusting the number and the shape of the bulges between the parallel electrode plates.
4. A superconducting qubit self-capacitance using a parallel plate capacitance structure, wherein the design is achieved using the method of claim 1, comprising: the capacitor comprises a first electrode plate, a second electrode plate, a dielectric medium positioned between the first electrode plate and the second electrode plate, and a control line arranged on the first electrode plate and the second electrode plate, wherein extension convex components which are mutually symmetrically interweaved and are used for preventing the loss of capacitance are arranged at the central parts of the inner sides of the first electrode plate and the second electrode plate; the expansion bulge component comprises bulges and grooves which are respectively arranged on the inner side surface of the first electrode plate and the inner side surface of the second electrode plate and are correspondingly arranged.
5. The superconducting qubit self-capacitor of claim 4 wherein the bump adopts a bump structure with an arc-shaped cross section.
6. The superconducting qubit self-capacitor of claim 4 wherein the protrusions on the second electrode plate are disposed in the middle of the inner side of the second electrode plate, the grooves of the first electrode plate are disposed in the middle of the inner side of the first electrode plate, and the grooves on the second electrode plate are symmetrically disposed along the protrusion center line of the second electrode plate, and the protrusions of the first electrode plate are symmetrically disposed along the groove center line of the first electrode plate.
7. The superconducting qubit self-capacitance of claim 4 wherein the expansion bump assembly further comprises: triangular capacitor protrusions which are respectively arranged on the inner side surfaces of the first electrode plate and the second electrode plate and used for increasing decoherence time.
8. The superconducting qubit self-capacitor of claim 7 wherein the triangular capacitor protrusions are respectively arranged at the center of the middle groove of the inner side surface of the first electrode plate and the center of the middle protrusion of the inner side surface of the second electrode plate or respectively arranged at the center of the middle protrusion of the inner side surface of the first electrode plate and the center of the middle groove of the inner side surface of the second electrode plate.
9. The superconducting qubit self-capacitor according to claim 7, wherein the triangular capacitor protrusions are of a structure with isosceles triangle cross sections.
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