CN115955295A - Device compatible with various fec, defec and crc algorithms - Google Patents
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Abstract
The invention discloses a device compatible with various fec, defec and crc algorithms, which comprises: the device comprises a fec module, a defec module, a crc module and a bit flow control module, wherein the fec module comprises a self-adding counter and an algorithm device; the defec module comprises a self-adding counter and an algorithm device; the bit flow control module comprises a self-decreasing counter, a self-increasing counter and a control module. According to the device compatible with various fec, defec and crc algorithms, different algorithm processing of data bit streams is carried out through register configuration fec and crc, compatibility and data algorithm control such as defec error correction, crc check and communication coding are achieved for transmitted data packets, and the requirements of high compatibility, high universality, low power consumption, low cost and the like can be met.
Description
Technical Field
The invention relates to the technical field of data processing of dual-mode Bluetooth or multiple wireless RF protocols for receiving and transmitting, in particular to a device compatible with multiple fec, defec and crc algorithms.
Background
In the technical fields of AIOT wireless intelligent sensing integration technology, wireless communication technology, wireless MCU \ SoC product application, wireless transmission control home, intelligent household appliances, intelligent health monitoring, intelligent Internet of things and the like, the control application of a fec/crc algorithm, error correction, communication coding of data bit streams and the like is more and more extensive, and the existing algorithm control devices are low in compatibility, lack of generality, high in power consumption and high in cost.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a device compatible with various fec, defec and crc algorithms, which can perform communication coding processing according to a configured communication coding mode based on a transmitted and received data bit stream, and perform fec error correction algorithm transmission control and crc algorithm check processing of the transmitted data bit stream and the received data bit stream according to a register configured with an algorithm mode, and has the advantages of low power consumption, low cost, high integration degree and strong universality.
To achieve the above object, an embodiment of the present invention provides an apparatus compatible with multiple fec, defec, and crc algorithms, including:
the fec module is used for carrying out different fec algorithm processing on the transmitted bit stream data based on the configuration of the register;
the fec module comprises a fec23 self-adding counter and a fec23 algorithm device for realizing the processing of a fec23 algorithm, a fec13 self-adding counter and a fec13 algorithm device for realizing the processing of a fec13 algorithm, and a fec12 self-adding counter and a fec12 algorithm device for realizing a fec12 algorithm;
the device module is used for carrying out different device error correction algorithm processing on the transmitted bit stream data based on the configuration of the register;
the device comprises a device for realizing the error correction algorithm processing of the device 23, a device for realizing the error correction algorithm processing of the device 13, a device for realizing the error correction algorithm processing of the device 23, and a device for realizing the error correction algorithm processing of the device 12, wherein the device for realizing the error correction algorithm processing of the device 23 comprises a device for realizing the error correction algorithm processing of the device 23, a device for realizing the error correction algorithm processing of the device 13, and a device for realizing the error correction algorithm processing of the device 12;
the crc module is used for carrying out crc algorithm processing on the received bit stream data based on the configuration of the register;
the bit flow control module is used for carrying out communication coding control processing on bit stream data based on the configuration of the register and the first control signal output by the fec module;
the bit flow control module comprises a self-decreasing counter, a self-increasing counter and a control module, wherein the self-decreasing counter performs self-decreasing counting of different initial values based on an initial value control signal, different coding modes and a first control signal to output a first counting value, the control module outputs a second control signal and an initial value control signal based on the configuration of a register, the first counting value of the self-decreasing counter and the first control signal, and the self-increasing counter performs self-increasing counting based on the second control signal to output a second counting value.
In one or more embodiments of the present invention, the defec23 algorithm apparatus includes an algorithm processing module, a shift register, and an error correction module, the algorithm processing module is configured to calculate raw data to obtain a calculated value, the shift register is configured to shift and store the raw data and the calculated value to obtain a final value, and the error correction module is configured to output a characterization signal for characterizing whether the raw data is erroneous or not based on the raw data, the calculated value, and the final value, and process the raw data based on the characterization signal.
In one or more embodiments of the present invention, the error correction module includes a judgment module for outputting a characterization signal for characterizing whether the original data is erroneous or not based on the original data, the calculated value and the final value, and a correction module for processing the original data based on the characterization signal.
In one or more embodiments of the present invention, the determining module includes a first exclusive or gate, a second exclusive or gate, a third exclusive or gate, a fourth exclusive or gate, and a fifth exclusive or gate;
the first input end of the first exclusive or gate is configured to receive original data, the second input end of the first exclusive or gate, the second input end of the second exclusive or gate, the second input end of the third exclusive or gate, the second input end of the fourth exclusive or gate, and the second input end of the fifth exclusive or gate are respectively configured to receive different calculated values, the first input end of the second exclusive or gate, the first input end of the third exclusive or gate, the first input end of the fourth exclusive or gate, and the first input end of the fifth exclusive or gate are respectively configured to receive different final values, the output end of the first exclusive or gate is configured to output a fifth characterization signal, the output end of the second exclusive or gate is configured to output a fourth characterization signal, the output end of the third exclusive or gate is configured to output a third characterization signal, the output end of the fourth exclusive or gate is configured to output a second characterization signal, and the output end of the fifth exclusive or gate is configured to output a first characterization signal.
In one or more embodiments of the present invention, the correction module includes a first and gate, a second and gate, a third and gate, a fourth and gate, a fifth and gate, a sixth and gate, a seventh and gate, an eighth and gate, a ninth and gate, a tenth and gate, a first not gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, a sixth not gate, a seventh not gate, an eighth not gate, a ninth not gate, a tenth not gate, an eleventh not gate, a twelfth not gate, a thirteenth not gate, a fourteenth not gate, a fifteenth not gate, a sixteenth not gate, a seventeenth not gate, an eighteenth not gate, a sixth exclusive or gate, a seventh exclusive or gate, an eighth exclusive or gate, a ninth exclusive or gate, a tenth exclusive or gate, an eleventh exclusive or gate, a twelfth exclusive or gate, a thirteenth exclusive or gate, a fourteenth exclusive or gate, and a fifteenth exclusive or gate;
the output end of the first NOT gate is connected with the third input end of the first AND gate, the output end of the second NOT gate is connected with the fifth input end of the first AND gate, the output end of the third NOT gate is connected with the first input end of the second AND gate, the output end of the fourth NOT gate is connected with the fourth input end of the second AND gate, the output end of the fifth NOT gate is connected with the fourth input end of the third AND gate, the output end of the sixth NOT gate is connected with the fifth input end of the third AND gate, the output end of the seventh NOT gate is connected with the first input end of the fourth AND gate, the output end of the eighth NOT gate is connected with the fifth input end of the fourth AND gate, and the output end of the ninth NOT gate is connected with the first input end of the fifth AND gate, the output end of the tenth NOT gate is connected with the second input end of the fifth AND gate, the output end of the eleventh NOT gate is connected with the third input end of the sixth AND gate, the output end of the twelfth NOT gate is connected with the fourth input end of the sixth AND gate, the output end of the thirteenth NOT gate is connected with the second input end of the seventh AND gate, the output end of the fourteenth NOT gate is connected with the fifth input end of the seventh AND gate, the output end of the fifteenth NOT gate is connected with the first input end of the eighth AND gate, the output end of the sixteenth NOT gate is connected with the third input end of the eighth AND gate, the output end of the seventeenth NOT gate is connected with the second input end of the tenth AND gate, and the output end of the eighteenth NOT gate is connected with the fourth input end of the tenth AND gate;
the first input end of the first AND gate, the second input end of the first AND gate, the input end of the first NOT gate, the third input end of the first AND gate and the input end of the second NOT gate are sequentially used for receiving first to fifth characterization signals; the input end of the third NOT gate, the second input end of the second AND gate, the third input end of the second AND gate, the input end of the fourth NOT gate and the fifth input end of the second AND gate are sequentially used for receiving the first to fifth characterization signals; the first input end of the third AND gate, the second input end of the third AND gate, the third input end of the third AND gate, the input end of the fifth NOT gate and the input end of the sixth NOT gate are sequentially used for receiving the first to fifth characterization signals; the input end of the seventh NOT gate, the second input end of the fourth AND gate, the third input end of the fourth AND gate, the fourth input end of the fourth AND gate and the input end of the eighth NOT gate are sequentially used for receiving the first to fifth characterization signals; the input end of the ninth not gate, the input end of the tenth not gate, the third input end of the fifth and gate, the fourth input end of the fifth and gate and the fifth input end of the fifth and gate are sequentially used for receiving first to fifth characterization signals; the first input end of the sixth AND gate, the second input end of the sixth AND gate, the input end of the eleventh NOT gate, the input end of the twelfth NOT gate and the fifth input end of the sixth AND gate are sequentially used for receiving the first to fifth characterization signals; the first input end of the seventh AND gate, the input end of the thirteenth NOT gate, the third input end of the seventh AND gate, the fourth input end of the seventh AND gate and the input end of the fourteenth NOT gate are sequentially used for receiving the first to fifth characterization signals; the input end of the fifteenth NOT gate, the second input end of the eighth AND gate, the input end of the sixteenth NOT gate, the fourth input end of the eighth AND gate and the fifth input end of the eighth AND gate are sequentially used for receiving the first to fifth characterization signals; the first input end, the second input end, the third input end, the fourth input end and the fifth input end of the ninth AND gate are sequentially used for receiving the first to fifth characterization signals; the first input end of the tenth AND gate, the input end of the seventeenth NOT gate, the third input end of the tenth AND gate, the input end of the eighteenth NOT gate and the fifth input end of the tenth AND gate are sequentially used for receiving first to fifth characterization signals;
the first input terminal of the sixth exclusive or gate, the first input terminal of the seventh exclusive or gate, the first input terminal of the eighth exclusive or gate, the first input terminal of the ninth exclusive or gate, the first input terminal of the tenth exclusive or gate, the first input terminal of the eleventh exclusive or gate, the first input terminal of the twelfth exclusive or gate, the first input terminal of the thirteenth exclusive or gate, the first input terminal of the fourteenth exclusive or gate, and the first input terminal of the fifteenth exclusive or gate are configured to receive original data;
and the output end of the sixth exclusive or gate, the output end of the seventh exclusive or gate, the output end of the eighth exclusive or gate, the output end of the ninth exclusive or gate, the output end of the tenth exclusive or gate, the output end of the eleventh exclusive or gate, the output end of the twelfth exclusive or gate, the output end of the thirteenth exclusive or gate, the output end of the fourteenth exclusive or gate and the output end of the fifteenth exclusive or gate are used for outputting the correction value.
In one or more embodiments of the invention, the crc algorithm includes a crc24 algorithm, a crc16 algorithm and a crc8 algorithm, and the crc24 algorithm uses a 3byte crc polynomial as: x24+ X10+ X9+ X6+ X4+ X3+ X +1, and the 2byte crc polynomial used by the crc16 algorithm is: x16+ X12+ X5+1, and the 1byte crc polynomial adopted by the crc8 algorithm is: x8+ X2+ X +1.
In one or more embodiments of the invention, the fec13 algorithm is a bit data stream of 3 repeated fec codes; the fec23 algorithm is implemented as a hamming code and the fec12 algorithm is implemented as a convolutional code.
In one or more embodiments of the present invention, the polynomial adopted by the fec23 algorithm is G (D) = (D + 1) (D4 + D + 1), and the polynomial adopted by the fec12 algorithm is G0 (x) =1+ x2+ x3, G1 (x) =1+ x2+ x3.
In one or more embodiments of the present invention, the raw data includes a0, a1, a2, a3, a4, a5, a6, a7, a8, and a9, and the calculation formula for the algorithm processing module to obtain the calculated value includes:
fec23_data_reg[4] =a0+a2+a5+a6+a8+a9；
fec23_data_reg[3] =a0+a1+a2+a3+a5+a7+a8；
fec23_data_reg[2] =a1+a2+a3+a4+a6+a8+a9；
fec23_data_reg[1] =a0+a3+a4+a6+a7+a8；
fec23_data_reg[0]=a1+a4+a5+a7+a8+a9。
in one or more embodiments of the present invention, the control module includes an eleventh and gate, a twelfth and gate, a thirteenth and gate, a fourteenth and gate, a fifteenth and gate, a nineteenth not gate, a first or gate, and a second or gate;
the second input end of the twelfth AND gate is connected with the output end of the nineteenth NOT gate, the first input end of the first OR gate is connected with the output end of the eleventh AND gate, the second input end of the first OR gate is connected with the output end of the twelfth AND gate, the third input end of the first OR gate is connected with the output end of the thirteenth AND gate, the first input end of the fourteenth AND gate is connected with the output end of the first OR gate, the second input end of the fourteenth AND gate is used for receiving the first control signal, the output end of the fourteenth AND gate is used for outputting the second control signal, the second input end of the second OR gate is connected with the output end of the fifteenth AND gate, and the output end of the second OR gate is used for outputting the initial value control signal.
Compared with the prior art, the device compatible with various fec, defec and crc algorithms according to the embodiment of the invention can be used as a baseband protocol characteristic which needs to be compatible with dual-mode Bluetooth, various wireless RF transmission and various wireless protocol compatible transmission.
And controlling data transmission according to a bit flow control module, performing communication coding control on serial data after reading the data, performing a fec algorithm and a crc algorithm on the transmitted serial data bit stream, and performing decoding control on the fec algorithm, the crc algorithm and the communication coding on the received serial data bit stream.
Different algorithm processing of data bit streams is carried out through a register configuration fec algorithm and a crc algorithm, compatibility and data algorithm control such as fec error correction, crc check, communication coding and the like are achieved on transmitted data packets, different wireless devices are controlled, and various wireless data transmission is compatible with receiving, so that the requirements of strong compatibility, strong universality, low power consumption, low cost and the like can be met.
Codes and algorithms in baseband control compatible with dual-mode Bluetooth and various RF protocols can be used as a universal IP module which can be configured and compatible with various communication codes, a fec/defec algorithm and a crc algorithm to be integrated in an SoC or MCU circuit, and the method has the advantages of low power consumption, strong universality, small occupied area and cost saving.
Drawings
Fig. 1 is a block diagram of a fec module compatible with various fec algorithms according to the present invention.
Fig. 2 is an internal structural view of a fec module according to the present invention.
Fig. 3 is a block diagram of a bit flow control module according to the present invention.
Fig. 4 is a schematic diagram of the structure of a self-decreasing counter and a self-increasing counter according to the present invention.
Fig. 5 is a schematic diagram of the structure of a control module according to the present invention.
Fig. 6 is a schematic structural diagram of a crc module compatible with various crc algorithms according to the present invention.
Fig. 7 is a block diagram of a device module compatible with various device algorithms according to the present invention.
Fig. 8 is a schematic diagram of the internal structure of the defec module according to the present invention.
Fig. 9 is a schematic diagram of the structure of an algorithm processing module and a shift register according to the present invention.
Fig. 10 is a schematic diagram of the defec algorithm according to the present invention.
FIG. 11 is a schematic diagram of a determining module according to the present invention.
FIG. 12 is a schematic diagram of a correction module according to the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
The terms "coupled" or "connected" in this specification encompass both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as a connection made through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as connections through switches, follower circuits, etc., that serve the same or similar functional purpose. In addition, in the present invention, words such as "first", "second", and the like are mainly used for distinguishing one technical feature from another technical feature, and do not necessarily require or imply any actual relationship, number, or order between the technical features.
An apparatus compatible with multiple fec, defec and crc algorithms, comprising: the device comprises a fec module, a defec module, a crc module and a bit flow control module.
The fec module is used for performing different fec algorithm processing on the transmitted bit stream data based on the configuration of the register; the fec module is used for performing different fec error correction algorithm processing on the transmitted bit stream data based on the configuration of the register; the crc module is used for carrying out crc algorithm processing on the received bit stream data based on the configuration of the register; and the bit flow control module is used for carrying out communication coding control processing on bit flow data based on the configuration of the register and the first control signal output by the fec module.
Fig. 1 is a structural diagram of a fec module compatible with various fec algorithms, wherein, fec _ init is an initialization control signal of the fec algorithm module; the fec _ en is an enabling signal of the fec algorithm module; tx _ datain is serial input data of the fec algorithm module; clk is a clock signal of the fec algorithm module; reset is the reset signal of the fec algorithm module.
The fec _ type [1] is configured by a register and used as a configuration signal of the fec algorithm module, as shown in the following table 1, the fec _ type [1] is configured as 00 and then is a no fec algorithm, the fec _ type [1] is configured as 01 and then is a fec13 algorithm, the fec _ type [1] is configured as 10 and then is a fec23 algorithm, and the fec _ type [1] is configured as 11 and then is a fec12 algorithm.
As shown in fig. 2, the fec module includes a fec23 self-adding counter and fec23 algorithm device for implementing the fec23 algorithm, a fec13 self-adding counter and fec13 algorithm device for implementing the fec13 algorithm, and a fec12 self-adding counter and fec12 algorithm device for implementing the fec12 algorithm.
The fec13 algorithm, the fec23 algorithm, and the fec12 algorithm may select the configuration. The fec13 algorithm is a bit data stream of 3 repetitive fec codes; the fec23 algorithm is implemented in hamming code, and the polynomial adopted is g (D) = (D + 1) (D4 + D + 1); the fec12 algorithm is implemented by convolutional codes, and the polynomial adopted is G0 (x) =1+ x2+ x3, G1 (x) =1+ x2+ x3; wherein G0 (a 0) is transmitted before and G1 (a 1) is transmitted after.
Fig. 3 shows a bit stream control module for serial data output, which is used to control the data read from the first-in first-out data buffer or RAM to perform the control of serial output bit stream data of the transmission data and perform the communication coding control process. The coding modes comprise non-return-to-zero coding, manchester coding, 8b/10b coding and data interleaving coding. As shown in fig. 3, the input signals of the bit stream control module respectively have init _ cnt, fec _ ready, data _ type [ 1; the output signals of the bit flow control module are respectively provided with a bit _ cnt [4], a data _ bit _ cnt [3], a data _ bit _ cnt _ en; wherein data _ type [1] is a configuration signal of the communication coding mode register, and the meaning thereof is shown in table 2 below. The init _ cnt is an initialization signal for calculating the bit _ cnt inside the fec module for data transmission control, the fec _ ready is a first control signal output by the fec module, namely, when each fec _ ready is valid, valid counting of the internal bit stream is carried out. reset is a reset signal for controlling an internal counter of the fec module, and clk is a clock signal for effectively counting bit streams inside the fec module.
The bit flow control module comprises a self-decreasing counter, a self-increasing counter and a control module.
Fig. 4 shows a self-decreasing counter and a self-increasing counter, the self-decreasing counter performing self-decreasing counting of different initial values based on the initial value control signal, different encoding modes, and the first control signal fec _ ready to output a first count value bit _ cnt [4:0], when the load _ bit _ cnt is valid, the bit _ cnt performs a load initial value, and for data _ type [1 [0] of different inputs, the bit _ cnt performs a load different initial value. The self-adding counter performs self-adding counting based on the second control signal and outputs a second counting value. The input signals of the self-adding counter comprise init _ cnt, data _ bit _ cnt _ en, reset and clk; when the external input signal init _ cnt is 1, the initialization value of the output signal data _ bit _ cnt is 0, and when the data _ bit _ cnt _ en is valid. The output signal data _ bit _ cnt performs a self-counting. In fig. 4, clk is a clock signal of the counter, and reset is a reset signal of the counter.
Fig. 5 shows a control module which, based on the configuration of the register, decrements the first count value of the counter, bit _ cnt [4:0] and the first control signal fec _ ready output the second control signal data _ bit _ cnt _ en and the initial value control signal load _ bit _ cnt.
The control module comprises an eleventh AND gate, a twelfth AND gate, a thirteenth AND gate, a fourteenth AND gate, a fifteenth AND gate, a nineteenth NOT gate, a first OR gate and a second OR gate. A first input of the eleventh and gate is configured to receive the logic value of bit _ cnt non-16 'h00 \/16' h05 \/16 'h0a \/16' h0f, a second input of the eleventh and gate is configured to receive data8b/10b, an input of the nineteenth not gate is configured to receive bit _ cnt [0], a first input of the twelfth and gate is configured to receive data _ man, a second input of the twelfth and gate is coupled to the output of the nineteenth not gate, a first input of the thirteenth and gate is configured to receive data _ nrz, a second input of the thirteenth and gate is configured to receive data _ interleave, a first input of the first or gate is coupled to the output of the eleventh and gate, a second input of the first or gate is coupled to the output of the twelfth and gate, a third input of the first or gate is coupled to the output of the thirteenth and gate, a first input of the fourteenth and gate is coupled to the output of the first or gate, a second input of the fourteenth and gate is configured to receive the first and gate control signal, and outputs the second control signal bit _ y _ control signal. A first input terminal of the fourteenth and gate is configured to receive bit _ cnt = =5' b0000, a second input terminal of the fourteenth and gate is configured to receive fec _ ready, a first input terminal of the second or gate is configured to receive init _ cnt, a second input terminal of the second or gate is connected to an output terminal of the fifteenth and gate, and an output terminal of the second or gate is configured to output the initial value control signal load _ bit _ cnt.
Referring to fig. 4 and 5, the first count value bit _ cnt [4:0] and a different data _ type [1] of the register configuration generates data _ bit _ cnt _ en. Specifically, data _ type [1] is configured as 00: NRZ law data (i.e., data _ NRZ data type), and the corresponding data _ NRZ in FIG. 5 is 1; data _ type [ 1; data _ type [ 1; data _ type [ 1. When the input signal init _ cnt is 1, or the bit _ cnt count value is zero and the fec _ ready is 1, both of the above two cases make the load _ bit _ cnt be 1.
Fig. 6 shows a crc module compatible with multiple crc algorithms. The crc _ md [1] is configured by a register and used as a configuration signal of crc algorithm selection output, crc _ init _ sel is used for controlling initialization of a crc module, datain is a serial input signal of the crc module, data _ en is a data stream enabling signal for selecting a data serial data stream to carry out the crc algorithm, data _ bit _ cnt _ en is a logic control signal generated in fig. 5, namely when the logic control signal is valid, the data stream is selected to carry out the crc algorithm, and the fec _ ready is the same as a fec ready signal generated in fig. 1; crc _ en is an enable signal for controlling the crc module to perform the crc algorithm, clk is a clock signal of an internal counter of the crc module, and reset is a reset signal of the internal counter of the crc module; crc _ data [ 23.
From the serial data output from the register, serial _ data _ crc selects a different crc _ data output, specifically, when a configuration value of crc _ md [1] 0 is 2' b10, crc _ data [23] is selected; when the configuration value of crc _ md [1] is 2' b01, crc _ data [15] is selected; when the configuration value of crc _ md [1] is 2' b00, crc _ data [7] is selected.
The crc module performs crc algorithm calculation for both transmitting and receiving data, and a crc check logic circuit for receiving data is arranged in the crc module. As shown in fig. 6, the crc check logic circuit includes a sixteenth exclusive or gate, a sixteenth and gate, a twentieth and gate, a seventeenth and gate, and a D flip-flop. A first input terminal of the sixteenth exclusive-or gate is configured to receive datain, a second input terminal of the sixteenth exclusive-or gate is configured to receive serial _ data _ crc, a first input terminal of the sixteenth and gate is configured to receive rx _ en, a second input terminal of the sixteenth and gate is configured to receive fec _ ready, a third input terminal of the sixteenth and gate is configured to receive crc _ en, a fourth input terminal of the sixteenth and gate is configured to receive data _ bit _ cnt _ en, a fifth input terminal of the sixteenth and gate is connected to an output terminal of the sixteenth exclusive-or gate, an input terminal of the twentieth and gate is configured to receive crc _ init, a first input terminal of the seventeenth and gate is connected to an output terminal of the twentieth and gate, a second input terminal of the seventeenth and gate is connected to an output terminal of the seventeenth and gate, a D input terminal of the D flip-flop is connected to an output terminal of the seventeenth and gate, and a Q output terminal of the D flip-flop is configured to output rx _ crc _ err.
In this embodiment, when crc _ init is valid, rx _ crc _ err is 0; when crc _ init is 0, the logic datain xors the value output by serial _ data _ crc with the logic rx _ en, fec _ ready, crc _ en and data _ bit _ cnt _ en to generate the rx _ crc _ err signal.
In addition, the crc24 algorithm uses a 3byte crc polynomial as: x24+ X10+ X9+ X6+ X4+ X3+ X +1; the 2byte crc polynomial used by the crc16 algorithm is: x16+ X12+ X5+1; the 1byte crc polynomial used by the crc8 algorithm is: x8+ X2+ X +1.
Fig. 7 shows a defec module compatible with multiple defec algorithms. For signals generated by the fec algorithm, to perform the fec operation, input signals include fec _ init, fec _ en, fec _ type [1], rx _ datain, reset and clk, and output signals include fec _ ready and fec _ dataout signals.
As shown in fig. 8, the fec module includes a fec23 self-adding counter and fec23 algorithm device for implementing fec23 error correction algorithm processing, a fec13 self-adding counter and fec13 algorithm device for implementing fec13 algorithm processing, and a fec12 self-adding counter and fec12 algorithm device for implementing fec12 algorithm.
Different fec algorithms are performed according to configured fec _ type, wherein, fec13 algorithm corrects errors of continuous 3 bit streams, and two bit values with the same value are taken as valid values in 3 bits. The fec12 algorithm adopts a convolution Viterbi error correction decoding circuit to decode and correct errors, a currently universal module is still adopted in the Viterbi error correction decoding circuit, the Viterbi error correction decoding circuit mainly comprises 3 modules, namely an addition module, a comparison module and a selection module, and the minimum path is selected to output after 32 bits of calculation at each time; the defec23 algorithm is realized by a Hamming code error correction decoding circuit.
As shown in fig. 9, 10, 11 and 12, the defec23 algorithm device includes an algorithm processing module, a shift register and an error correction module. The algorithm processing module is used for calculating original data to obtain a calculated value, the shift register is used for shifting and storing the original data and the calculated value to obtain a final value, and the error correction module is used for outputting a characterization signal for characterizing whether the original data is wrong or not based on the original data, the calculated value and the final value and processing the original data based on the characterization signal.
The fec23 algorithm and the sent fec23 algorithm perform the fec23 algorithm on the received data datain to obtain a calculated value fec23_ data _ reg [4]. Fig. 10 specifically introduces a schematic diagram of the fec algorithm, in which 15 bits are used as a set of effective data for originally transmitted data, the first 10 bits, i.e., a0 to a9, are used as original data, and a10 to a14 are hamming codes generated according to the polynomial of the fec23 algorithm based on (a 0, a1, a2, a 9):
a10= fec23_data_reg[4]=a0+a2+a5+a6+a8+a9；
a11= fec23_data_reg[3]=a0+a1+a2+a3+a5+a7+a8；
a12= fec23_data_reg[2]=a1+a2+a3+a4+a6+a8+a9；
a13= fec23_data_reg[1]=a0+a3+a4+a6+a7+a8；
a14= fec23_data_reg[0]=a1+a4+a5+a7 +a8+a9。
the received data is shifted and enabled by fec _ en, and the serially input data is subjected to the fec23 algorithm, that is, fec23_ data _ reg [ 4.
In addition, the bit stream received over the air is stored in the buffer in a serial manner, that is, the bit stream is stored in the datain, rxd _ dly [10: 4, performing a fec23 algorithm through received (a 0, a1, a2, a 9), and when the received a 0-a 9 has errors, receiving a value stored in the shift register from the transmission follower, namely the value is different from the valid data a 0-a 9, namely the received data is judged to have errors, because the same fec23 algorithm is performed on the received data.
The error correction module comprises a judgment module and a correction module, wherein the judgment module is used for outputting a representation signal for representing whether the original data datain is wrong or not based on the original data datain, the calculated value and the final value, and the correction module is used for processing the original data based on the representation signal.
As shown in fig. 11, the determining module includes a first exclusive or gate, a second exclusive or gate, a third exclusive or gate, a fourth exclusive or gate, and a fifth exclusive or gate.
A first input of the first exclusive-or gate is arranged to receive the original data datain, a second input of the first exclusive-or gate is arranged to receive the count value fec23_ data _ reg [0], a second input of the second exclusive-or gate is arranged to receive the count value fec23_ data _ reg [1], a second input of the third exclusive-or gate is arranged to receive the count value fec23_ data _ reg [2], a second input of the fourth exclusive-or gate is arranged to receive the count value fec23_ data _ reg [3] and a second input of the fifth exclusive-or gate is arranged to receive the count value fec23_ data _ reg [4], a first input of the second exclusive-or gate is arranged to receive the final value rxd _ dly [14], the first input of the third exclusive-or gate is used to receive the final value rxd _ dly [13], the first input of the fourth exclusive-or gate is used to receive the final value rxd _ dly [12], the first input of the fifth exclusive-or gate is used to receive the final value rxd _ dly [11], the output of the first exclusive-or gate is used to output the fifth characterization signal c [4], the output of the second exclusive-or gate is used to output the fourth characterization signal c [3], the output of the third exclusive-or gate is used to output the third characterization signal c [2], the output of the fourth exclusive-or gate is used to output the second characterization signal c [1], and the output of the fifth exclusive-or gate is used to output the first characterization signal c [0].
As shown in fig. 12, the correcting module includes a first and gate, a second and gate, a third and gate, a fourth and gate, a fifth and gate, a sixth and gate, a seventh and gate, an eighth and gate, a ninth and gate, a tenth and gate, a first not gate, a second not gate, a third not gate, a fourth not gate, a fifth not gate, a sixth not gate, a seventh not gate, an eighth not gate, a ninth not gate, a tenth not gate, an eleventh not gate, a twelfth not gate, a thirteenth not gate, a fourteenth not gate, a fifteenth not gate, a sixteenth not gate, a seventeenth not gate, an eighteenth not gate, a sixth exclusive or gate, a seventh exclusive or gate, an eighth exclusive or gate, a ninth exclusive or gate, a tenth exclusive or gate, an eleventh exclusive or gate, a twelfth exclusive or gate, a thirteenth exclusive or gate, a fourteenth exclusive or gate and a fifteenth exclusive or gate.
The output end of the first NOT gate is connected with the third input end of the first AND gate, the output end of the second NOT gate is connected with the fifth input end of the first AND gate, the output end of the third NOT gate is connected with the first input end of the second AND gate, the output end of the fourth NOT gate is connected with the fourth input end of the second AND gate, the output end of the fifth NOT gate is connected with the fourth input end of the third AND gate, the output end of the sixth NOT gate is connected with the fifth input end of the third AND gate, the output end of the seventh NOT gate is connected with the first input end of the fourth AND gate, the output end of the eighth NOT gate is connected with the fifth input end of the fourth AND gate, and the output end of the ninth NOT gate is connected with the first input end of the fifth AND gate, the output end of the tenth NOT gate is connected with the second input end of the fifth AND gate, the output end of the eleventh NOT gate is connected with the third input end of the sixth AND gate, the output end of the twelfth NOT gate is connected with the fourth input end of the sixth AND gate, the output end of the thirteenth NOT gate is connected with the second input end of the seventh AND gate, the output end of the fourteenth NOT gate is connected with the fifth input end of the seventh AND gate, the output end of the fifteenth NOT gate is connected with the first input end of the eighth AND gate, the output end of the sixteenth NOT gate is connected with the third input end of the eighth AND gate, the output end of the seventeenth NOT gate is connected with the second input end of the tenth AND gate, and the output end of the eighteenth NOT gate is connected with the fourth input end of the tenth AND gate.
The first input of the first AND-gate is arranged to receive the first characterizing signal c [0], the second input of the first AND-gate is arranged to receive the second characterizing signal c [1], the input of the first NOT-gate is arranged to receive the third characterizing signal c [2], the third input of the first AND-gate is arranged to receive the fourth characterizing signal c [3], and the input of the second NOT-gate is arranged to receive the fifth characterizing signal c [4].
The input of the third not-gate is arranged to receive the first characterizing signal c [0], the second input of the second and-gate is arranged to receive the second characterizing signal c [1], the third input of the second and-gate is arranged to receive the third characterizing signal c [2], the input of the fourth not-gate is arranged to receive the fourth characterizing signal c [3], and the fifth input of the second and-gate is arranged to receive the fifth characterizing signal c [4].
The first input of the third AND-gate is arranged to receive the first characterizing signal c [0], the second input of the third AND-gate is arranged to receive the second characterizing signal c [1], the third input of the third AND-gate is arranged to receive the third characterizing signal c [2], the input of the fifth NOT-gate is arranged to receive the fourth characterizing signal c [3], and the input of the sixth NOT-gate is arranged to receive the fifth characterizing signal c [4].
The input of the seventh not-gate is arranged to receive the first characterizing signal c [0], the second input of the fourth and-gate is arranged to receive the second characterizing signal c [1], the third input of the fourth and-gate is arranged to receive the third characterizing signal c [2], the fourth input of the fourth and-gate is arranged to receive the fourth characterizing signal c [3], and the input of the eighth not-gate is arranged to receive the fifth characterizing signal c [4].
The ninth not-gate has an input for receiving the first characterizing signal c [0], the tenth not-gate has an input for receiving the second characterizing signal c [1], the fifth and-gate has a third input for receiving the third characterizing signal c [2], the fifth and-gate has a fourth input for receiving the fourth characterizing signal c [3], and the fifth and-gate has a fifth input for receiving the fifth characterizing signal c [4].
The first input of the sixth AND-gate is arranged to receive the first characterizing signal c [0], the second input of the sixth AND-gate is arranged to receive the second characterizing signal c [1], the input of the eleventh NOT-gate is arranged to receive the third characterizing signal c [2], the input of the twelfth NOT-gate is arranged to receive the fourth characterizing signal c [3], and the fifth input of the sixth AND-gate is arranged to receive the fifth characterizing signal c [4].
The first input terminal of the seventh AND-gate is arranged to receive the first characterizing signal c [0], the input terminal of the thirteenth NOT-gate is arranged to receive the second characterizing signal c [1], the third input terminal of the seventh AND-gate is arranged to receive the third characterizing signal c [2], the fourth input terminal of the seventh AND-gate is arranged to receive the fourth characterizing signal c [3], and the input terminal of the fourteenth NOT-gate is arranged to receive the fifth characterizing signal c [4].
The input of the fifteenth not-gate is arranged to receive the first characterizing signal c [0], the second input of the eighth and-gate is arranged to receive the second characterizing signal c [1], the input of the sixteenth not-gate is arranged to receive the third characterizing signal c [2], the fourth input of the eighth and-gate is arranged to receive the fourth characterizing signal c [3], and the fifth input of the eighth and-gate is arranged to receive the fifth characterizing signal c [4].
The first input of the ninth AND-gate is arranged to receive the first characterizing signal c [0], the second input of the ninth AND-gate is arranged to receive the second characterizing signal c [1], the third input of the ninth AND-gate is arranged to receive the third characterizing signal c [2], the fourth input of the ninth AND-gate is arranged to receive the fourth characterizing signal c [3], and the fifth input of the ninth AND-gate is arranged to receive the fifth characterizing signal c [4].
The first input of the tenth AND-gate is arranged to receive the first characterizing signal c [0], the input of the seventeenth NOT-gate is arranged to receive the second characterizing signal c [1], the third input of the tenth AND-gate is arranged to receive the third characterizing signal c [2], the input of the eighteenth NOT-gate is arranged to receive the fourth characterizing signal c [3], and the fifth input of the tenth AND-gate is arranged to receive the fifth characterizing signal c [4].
A first input terminal of the sixth exclusive or gate is configured to receive the original data a0, a first input terminal of the seventh exclusive or gate is configured to receive the original data a1, a first input terminal of the eighth exclusive or gate is configured to receive the original data a2, a first input terminal of the ninth exclusive or gate is configured to receive the original data a3, a first input terminal of the tenth exclusive or gate is configured to receive the original data a4, a first input terminal of the eleventh exclusive or gate is configured to receive the original data a5, a first input terminal of the twelfth exclusive or gate is configured to receive the original data a6, a first input terminal of the thirteenth exclusive or gate is configured to receive the original data a7, a first input terminal of the fourteenth exclusive or gate is configured to receive the original data a8, and a first input terminal of the fifteenth exclusive or gate is configured to receive the original data a9.
The output end of the sixth exclusive-or gate is used for outputting a correction value a0_ flip, the output end of the seventh exclusive-or gate is used for outputting a correction value a1_ flip, the output end of the eighth exclusive-or gate is used for outputting a correction value a2_ flip, the output end of the ninth exclusive-or gate is used for outputting a correction value a3_ flip, the output end of the tenth exclusive-or gate is used for outputting a correction value a4_ flip, the output end of the eleventh exclusive-or gate is used for outputting a correction value a5_ flip, the output end of the twelfth exclusive-or gate is used for outputting a correction value a6_ flip, the output end of the thirteenth exclusive-or gate is used for outputting a correction value a7_ flip, the output end of the fourteenth exclusive-or gate is used for outputting a correction value a8_ flip, and the output end of the fifteenth exclusive-or gate is used for outputting a correction value a9_ flip.
In this embodiment, the calculation formula for obtaining the calculated value by the algorithm processing module includes:
fec23_data_reg[4]=a0+a2+a5+a6+a8+a9；
fec23_data_reg[3]=a0+a1+a2+a3+a5+a7+a8；
fec23_data_reg[2]=a1+a2+a3+a4+a6+a8+a9；
fec23_data_reg[1]=a0+a3+a4+a6+a7+a8；
fec23_data_reg[0]=a1+a4+a5+a7+a8+a9。
from the above equation, when one or more of a0, a1, a2, a3, a4, a5, a6, a7, a8, a9 has an error, the corresponding fec23_ data _ reg will be in error, and the corresponding characterization signals in c [0], c [1], c [2], c [3], c [4] will be in error by combining with fig. 11.
For example, if a0 goes wrong, then fec23_ data _ reg [4], fec23_ data _ reg [3] and fec23_ data _ reg [1] go wrong, so that c [0], c [1] and c [3] go wrong, and a corrected value a0_ flip is obtained by combining the sixth exclusive or gate in fig. 12 after error correction is obtained by a0 according to exclusive or logic, the error correction algorithm of the data a0 is a0_ flip = a0+ (c [0] c [1] (-c [2 ])) c [3] (-c [4 ])), wherein "+" represents an or logic operation, "+" represents an and logic operation, and "-" represents a non-logic operation; the error correction algorithm for other data is the same. As shown in fig. 12, a1_ flip corresponds to a correction value when the data a1 has an error, a2_ flip corresponds to a correction value when the data a2 has an error, a3_ flip corresponds to a correction value when the data a3 has an error, a4_ flip corresponds to a correction value when the data a4 has an error, a5_ flip corresponds to a correction value when the data a5 has an error, a6_ flip corresponds to a correction value when the data a6 has an error, a7_ flip corresponds to a correction value when the data a7 has an error, a8_ flip corresponds to a correction value when the data a8 has an error, and a9_ flip corresponds to a correction value when the data a9 has an error.
In the present embodiment, the fec algorithm includes fec13, fec23, fec12 and corresponding fec algorithm; according to the Bluetooth protocol, basic Rate data transmission uses fec13, fec23 coding and decoding algorithm, while BLE5.2 uses fec12 coding and decoding algorithm. The Basic Rate compatible with the bluetooth protocol uses the crc16 bit algorithm g (D) = D16+ D12+ D5+1. The crc24 bit algorithm g (D) = D24+ D10+ D9+ D6+ D4+ D3+ D +1 used by the Low Energy Controller protocol compatible with the bluetooth protocol. The method is compatible with various wireless RF structures, and the used fec algorithm is fec13 and fec23 coding and decoding algorithms; the crc algorithm polynomial is used with a variety of wireless RF packet structures that are compatible: 1byte crc g (D) = D8 + D2 + D +1; 2byte crc g (D) = D16+ D12+ D5+1.
In wireless communication, data coding is often used in baseband transmission for correct transmission of data. The method can realize the transmission of four coding modes which can be selected by Non-Return-to-Zero coding Non-Return-Zero (NRZ), manchester coding, 8b/10b coding 8/10 bits line code and Data Interleaving coding for a transmitted Data bit stream through a configuration register.
The device compatible with various fec/fec algorithms and crc algorithms supports fec/fec algorithm mode processing and crc algorithm mode processing of a data bit stream through an algorithm mode configured by register programming, and can start and end the data bit stream algorithm according to a control enabling signal and a control enabling mode of the algorithm device.
In order to achieve the purpose, the technical scheme adopted by the invention is to design a device compatible with the fec13, fec23 and fec12 algorithms and used for transmitting data according to the fec mode and the enabling signal, and design a device compatible with the corresponding fec13, fec23 and fec12 algorithms and used for performing the fec algorithm according to the fec mode and the enabling signal; a device was devised to perform the crc8/crc16/crc24 algorithm on transmit and receive data via a register configuration according to the crc pattern. A device for realizing Non-Return-to-Zero coding Non-Return-Zero (NRZ), manchester coding, 8b/10b coding 8/10 bits line code and Data Interleaving coding for the transmitted Data bit stream in one coding mode which can be selected is designed. Because the transmitted data bit stream needs serial operation for communication coding, a fec/fec algorithm and a crc algorithm, a device for serial communication coding, a fec/fec algorithm and a crc algorithm on the data bit stream is designed, and the device can be used for a communication coding, a fec decoding, a crc check and other data bit flow control and processing devices of bit stream data of a baseband protocol transceiving data packet compatible with dual-mode bluetooth and multiple wireless transmissions.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. An apparatus compatible with multiple fec, defec and crc algorithms, comprising:
the fec module is used for carrying out different fec algorithm processing on the transmitted bit stream data based on the configuration of the register;
the fec module comprises a fec23 self-adding counter and a fec23 algorithm device for realizing the processing of a fec23 algorithm, a fec13 self-adding counter and a fec13 algorithm device for realizing the processing of a fec13 algorithm, and a fec12 self-adding counter and a fec12 algorithm device for realizing a fec12 algorithm;
the device module is used for carrying out different device error correction algorithm processing on the transmitted bit stream data based on the configuration of the register;
the device comprises a device for realizing the error correction algorithm processing of the device 23, a device for realizing the error correction algorithm processing of the device 13, a device for realizing the error correction algorithm processing of the device 23, and a device for realizing the error correction algorithm processing of the device 12, wherein the device for realizing the error correction algorithm processing of the device 23 comprises a device for realizing the error correction algorithm processing of the device 23, a device for realizing the error correction algorithm processing of the device 13, and a device for realizing the error correction algorithm processing of the device 12;
the crc module is used for carrying out crc algorithm processing on the received bit stream data based on the configuration of the register;
the bit flow control module is used for carrying out communication coding control processing on bit flow data based on the configuration of the register and the first control signal output by the fec module;
the bit flow control module comprises a self-decreasing counter, a self-increasing counter and a control module, wherein the self-decreasing counter performs self-decreasing counting of different initial values based on an initial value control signal, different coding modes and a first control signal to output a first counting value, the control module outputs a second control signal and an initial value control signal based on the configuration of a register, the first counting value of the self-decreasing counter and the first control signal, and the self-increasing counter performs self-increasing counting based on the second control signal to output a second counting value.
2. The apparatus of claim 1, wherein the fec algorithm apparatus comprises an algorithm processing module, a shift register and an error correction module, the algorithm processing module is configured to calculate a calculated value from raw data, the shift register is configured to shift and store the raw data and the calculated value to obtain a final value, and the error correction module is configured to output a characterization signal for characterizing whether the raw data is erroneous based on the raw data, the count value and the final value and process the raw data based on the characterization signal.
3. The apparatus of claim 2, wherein the error correction module comprises a decision module for outputting a characterization signal for characterizing whether the raw data is erroneous based on the raw data, the calculated value and the final value, and a correction module for processing the raw data based on the characterization signal.
4. The apparatus of claim 3, wherein the determining module comprises a first XOR gate, a second XOR gate, a third XOR gate, a fourth XOR gate, and a fifth XOR gate;
the first input end of the first exclusive or gate is configured to receive original data, the second input end of the first exclusive or gate, the second input end of the second exclusive or gate, the second input end of the third exclusive or gate, the second input end of the fourth exclusive or gate, and the second input end of the fifth exclusive or gate are respectively configured to receive different calculated values, the first input end of the second exclusive or gate, the first input end of the third exclusive or gate, the first input end of the fourth exclusive or gate, and the first input end of the fifth exclusive or gate are respectively configured to receive different final values, the output end of the first exclusive or gate is configured to output a fifth characterization signal, the output end of the second exclusive or gate is configured to output a fourth characterization signal, the output end of the third exclusive or gate is configured to output a third characterization signal, the output end of the fourth exclusive or gate is configured to output a second characterization signal, and the output end of the fifth exclusive or gate is configured to output a first characterization signal.
5. The apparatus of claim 3 compatible with a plurality of fec, defec and crc algorithms, wherein the correction module comprises a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, a ninth AND gate, a tenth AND gate, a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, an eighth NOT gate, a ninth NOT gate, a tenth NOT gate, an eleventh NOT gate, a twelfth NOT gate, a thirteenth NOT gate, a fourteenth NOT gate, a fifteenth NOT gate, a sixteenth NOT gate, a seventeenth NOT gate, an eighteenth NOT gate, a sixth XOR gate, a seventh XOR gate, an eighth XOR gate, a ninth XOR gate, a tenth XOR gate, an eleventh XOR gate, a twelfth XOR gate, a thirteenth XOR gate, a fifteenth NOT gate and a fifteenth NOT OR gate;
the output end of the first NOT gate is connected with the third input end of the first AND gate, the output end of the second NOT gate is connected with the fifth input end of the first AND gate, the output end of the third NOT gate is connected with the first input end of the second AND gate, the output end of the fourth NOT gate is connected with the fourth input end of the second AND gate, the output end of the fifth NOT gate is connected with the fourth input end of the third AND gate, the output end of the sixth NOT gate is connected with the fifth input end of the third AND gate, the output end of the seventh NOT gate is connected with the first input end of the fourth AND gate, the output end of the eighth NOT gate is connected with the fifth input end of the fourth AND gate, and the output end of the ninth NOT gate is connected with the first input end of the fifth AND gate, the output end of the tenth NOT gate is connected with the second input end of the fifth AND gate, the output end of the eleventh NOT gate is connected with the third input end of the sixth AND gate, the output end of the twelfth NOT gate is connected with the fourth input end of the sixth AND gate, the output end of the thirteenth NOT gate is connected with the second input end of the seventh AND gate, the output end of the fourteenth NOT gate is connected with the fifth input end of the seventh AND gate, the output end of the fifteenth NOT gate is connected with the first input end of the eighth AND gate, the output end of the sixteenth NOT gate is connected with the third input end of the eighth AND gate, the output end of the seventeenth NOT gate is connected with the second input end of the tenth AND gate, and the output end of the eighteenth NOT gate is connected with the fourth input end of the tenth AND gate;
the first input end of the first AND gate, the second input end of the first AND gate, the input end of the first NOT gate, the third input end of the first AND gate and the input end of the second NOT gate are sequentially used for receiving first to fifth characterization signals; the input end of the third NOT gate, the second input end of the second AND gate, the third input end of the second AND gate, the input end of the fourth NOT gate and the fifth input end of the second AND gate are sequentially used for receiving the first to fifth characterization signals; the first input end of the third AND gate, the second input end of the third AND gate, the third input end of the third AND gate, the input end of the fifth NOT gate and the input end of the sixth NOT gate are sequentially used for receiving the first to fifth characterization signals; the input end of the seventh NOT gate, the second input end of the fourth AND gate, the third input end of the fourth AND gate, the fourth input end of the fourth AND gate and the input end of the eighth NOT gate are sequentially used for receiving the first to fifth characterization signals; the input end of the ninth not gate, the input end of the tenth not gate, the third input end of the fifth and gate, the fourth input end of the fifth and gate and the fifth input end of the fifth and gate are sequentially used for receiving the first to fifth characterization signals; the first input end of the sixth AND gate, the second input end of the sixth AND gate, the input end of the eleventh NOT gate, the input end of the twelfth NOT gate and the fifth input end of the sixth AND gate are sequentially used for receiving the first to fifth characterization signals; the first input end of the seventh AND gate, the input end of the thirteenth NOT gate, the third input end of the seventh AND gate, the fourth input end of the seventh AND gate and the input end of the fourteenth NOT gate are sequentially used for receiving the first to fifth characterization signals; the input end of the fifteenth NOT gate, the second input end of the eighth AND gate, the input end of the sixteenth NOT gate, the fourth input end of the eighth AND gate and the fifth input end of the eighth AND gate are sequentially used for receiving the first to fifth characterization signals; the first input end, the second input end, the third input end, the fourth input end and the fifth input end of the ninth AND gate are sequentially used for receiving first to fifth characterization signals; the first input end of the tenth AND gate, the input end of the seventeenth NOT gate, the third input end of the tenth AND gate, the input end of the eighteenth NOT gate and the fifth input end of the tenth AND gate are sequentially used for receiving the first to fifth characterization signals;
the first input end of the sixth exclusive-or gate, the first input end of the seventh exclusive-or gate, the first input end of the eighth exclusive-or gate, the first input end of the ninth exclusive-or gate, the first input end of the tenth exclusive-or gate, the first input end of the eleventh exclusive-or gate, the first input end of the twelfth exclusive-or gate, the first input end of the thirteenth exclusive-or gate, the first input end of the fourteenth exclusive-or gate and the first input end of the fifteenth exclusive-or gate are used for receiving original data;
and the output end of the sixth exclusive or gate, the output end of the seventh exclusive or gate, the output end of the eighth exclusive or gate, the output end of the ninth exclusive or gate, the output end of the tenth exclusive or gate, the output end of the eleventh exclusive or gate, the output end of the twelfth exclusive or gate, the output end of the thirteenth exclusive or gate, the output end of the fourteenth exclusive or gate and the output end of the fifteenth exclusive or gate are used for outputting the correction value.
6. The apparatus of claim 1, compatible with multiple fec, defec and crc algorithms, wherein the crc algorithm includes a crc24 algorithm, a crc16 algorithm and a crc8 algorithm, and the crc24 algorithm uses a 3byte crc polynomial as: x24+ X10+ X9+ X6+ X4+ X3+ X +1, and the 2byte crc polynomial used by the crc16 algorithm is: x16+ X12+ X5+1, and the 1byte crc polynomial adopted by the crc8 algorithm is: x8+ X2+ X +1.
7. The apparatus of claim 1, wherein the fec13 algorithm is a bit stream of 3 repetitive fec codes; the fec23 algorithm is implemented as a hamming code and the fec12 algorithm is implemented as a convolutional code.
8. The apparatus as claimed in claim 7, wherein the polynomial adopted by the fec23 algorithm is G (D) = (D + 1) (D4 + D + 1), and the polynomial adopted by the fec12 algorithm is G0 (x) =1+ x + 2+ x3, G1 (x) =1+ x + 2+ x3.
9. The apparatus of claim 2, wherein the raw data comprises a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, and the calculation formula of the algorithm processing module to obtain the calculated value comprises:
fec23_data_reg[4] =a0+a2+a5+a6+a8+a9；
fec23_data_reg[3] =a0+a1+a2+a3+a5+a7+a8；
fec23_data_reg[2] =a1+a2+a3+a4+a6+a8+a9；
fec23_data_reg[1] =a0+a3+a4+a6+a7+a8；
fec23_data_reg[0]=a1+a4+a5+a7+a8+a9。
10. the apparatus of claim 1, wherein the control module comprises an eleventh and gate, a twelfth and gate, a thirteenth and gate, a fourteenth and gate, a fifteenth and gate, a nineteenth not gate, a first or gate, and a second or gate;
the second input end of the twelfth AND gate is connected with the output end of the nineteenth NOT gate, the first input end of the first OR gate is connected with the output end of the eleventh AND gate, the second input end of the first OR gate is connected with the output end of the twelfth AND gate, the third input end of the first OR gate is connected with the output end of the thirteenth AND gate, the first input end of the fourteenth AND gate is connected with the output end of the first OR gate, the second input end of the fourteenth AND gate is used for receiving the first control signal, the output end of the fourteenth AND gate is used for outputting the second control signal, the second input end of the second OR gate is connected with the output end of the fifteenth AND gate, and the output end of the second OR gate is used for outputting the initial value control signal.
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| CN101938332A (en) * | 2007-07-20 | 2011-01-05 | 华为技术有限公司 | Method and device for synchronizing blocks and frames |
| US8687751B1 (en) * | 2010-04-02 | 2014-04-01 | Marvell International Ltd. | Multiple-input multiple-output receivers using successive interference cancellation based on cyclic redundancy check |
| CN114157728A (en) * | 2021-11-22 | 2022-03-08 | 苏州聚元微电子股份有限公司 | Link layer data control method suitable for multiple wireless protocols |
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| CN101938332A (en) * | 2007-07-20 | 2011-01-05 | 华为技术有限公司 | Method and device for synchronizing blocks and frames |
| US8687751B1 (en) * | 2010-04-02 | 2014-04-01 | Marvell International Ltd. | Multiple-input multiple-output receivers using successive interference cancellation based on cyclic redundancy check |
| CN114157728A (en) * | 2021-11-22 | 2022-03-08 | 苏州聚元微电子股份有限公司 | Link layer data control method suitable for multiple wireless protocols |
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