CN117792587A

CN117792587A - CRC (cyclic redundancy check) calculation method for realizing dynamic change of effective bit width of interface data based on FPGA (field programmable gate array)

Info

Publication number: CN117792587A
Application number: CN202311762564.4A
Authority: CN
Inventors: 吴美荣
Original assignee: MILKY WAY ELECTRONIC EQUIPMENT FACTORY SHANXI PROVINCE
Current assignee: MILKY WAY ELECTRONIC EQUIPMENT FACTORY SHANXI PROVINCE
Priority date: 2023-12-20
Filing date: 2023-12-20
Publication date: 2024-03-29

Abstract

The invention relates to the technical field of data communication safety, in particular to a CRC (cyclic redundancy check) calculation method for realizing dynamic change of effective bit width of interface data based on an FPGA (field programmable gate array), which solves the technical problems that the prior FPGA realization method converts the data into data with fixed bit width to carry out CRC calculation according to a specific protocol, has relatively poor compatibility and low calculation efficiency and relatively complicated logic realization, and comprises the steps of carrying out CRC calculation on communication packet data to be transmitted according to interface input information at an interface transmitting end to obtain a first CRC code, and integrating the transmitted communication packet data and the first CRC code into data to be transmitted to an interface receiving end; at the interface receiving end, according to the interface input information, carrying out CRC calculation on the received communication packet data carrying the first CRC code to obtain a second CRC code, comparing the second CRC code with the first CRC code carried in the data to be transmitted to obtain a CRC check result, and when the second CRC code is the same as the first CRC code carried in the data to be transmitted, the CRC check result is correct, otherwise, the CRC check result is incorrect.

Description

CRC (cyclic redundancy check) calculation method for realizing dynamic change of effective bit width of interface data based on FPGA (field programmable gate array)

Technical Field

The invention relates to the technical field of data communication safety, in particular to a CRC (cyclic redundancy check) calculation method for realizing dynamic change of effective bit width of interface data based on an FPGA (field programmable gate array).

Background

The cyclic redundancy check (Cyclic RedundancyCheckCRC) is a hash function that generates a short fixed-bit check code from data, and is mainly used to detect or verify errors that may occur after data transmission or storage. CRC is the most commonly used error checking code in the field of data communication, polynomial computation is performed on the data, the obtained result is attached to the back of the frame, and the receiving device also executes a similar algorithm to ensure the correctness and integrity of data transmission.

In the logic implementation in the field of data communication technology, CRC checking of data content based on the data communication interface format is required. The minimum unit of the data communication length is bytes, the effective data bit width of the data communication interface is fixed according to different application environments, but the effective data which needs to calculate CRC check under each clock is not fixed when the FPGA is realized according to the change of a communication protocol, and the effective data can change at any time. The existing FPGA implementation method is to convert the data into fixed bit width data for CRC calculation according to a specific protocol, and has the disadvantages of poor compatibility, low calculation efficiency and complex logic implementation.

Therefore, a CRC calculation implementation method capable of supporting real-time variation of a plurality of effective data bit widths is provided.

Disclosure of Invention

The invention provides a CRC (cyclic redundancy check) calculation method for realizing dynamic change of effective bit width of interface data based on an FPGA (field programmable gate array), which aims to solve the technical problems that the existing FPGA (field programmable gate array) realization methods are all based on a specific protocol and are converted into data with fixed bit width to carry out CRC calculation, and the compatibility is relatively poor, the calculation efficiency is low and the logic realization is relatively complicated.

The invention provides a CRC (cyclic redundancy check) calculation method for realizing dynamic change of effective bit width of interface data based on an FPGA (field programmable gate array), wherein input information of the interface data comprises an input clock i_clk, a start mark i_start, an input data enable i_dv, input data i_data, an input effective byte number i_lsb, an input CRC initial VALUE C_INIT_VALUE and an input polynomial VALUE XOR, and output information of the interface data comprises an output CRC calculation VALUE o_crc; the CRC calculation method comprises the following steps:

s1, at an interface transmitting end, according to interface input information, CRC calculation is carried out on communication packet data to be transmitted to obtain a first CRC code, and then the transmitted communication packet data and the first CRC code are integrated into data to be transmitted and transmitted to an interface receiving end;

and S2, at the interface receiving end, carrying out CRC calculation on the received communication packet data carrying the first CRC code according to the interface input information to obtain a second CRC code, comparing the second CRC code with the first CRC code carried in the data to be transmitted to obtain a CRC check result, and if the second CRC code is the same as the first CRC code carried in the data to be transmitted, the CRC check result is correct, otherwise, the CRC check result is incorrect.

Preferably, the sub-steps of performing CRC calculation at the interface transmitting end or the interface receiving end are:

1. before receiving effective data, presetting a CRC initial register when a start mark i_start is 1, and carrying out initialization configuration, wherein the initialization configuration supports all 0 or all 1, namely the CRC initial register value is hexadecimal 0000 or FFFF, and n CRC registers are required to be preset, and the serial numbers are 0,1 and 2.

2. When the width of the input data i_data is 64 bits, exclusive OR is carried out on the upper 8 bits i_data [63:56] of the input data i_data and the upper 8 bits of the CRC initial register, the result is put into the upper bits of the CRC register 0, and the lower 8 bits of the CRC initial register are put into the lower bits of the CRC register 0;

3. shifting the content of the CRC register 0 one bit to the left, filling the least significant bit with 0, checking the shifted bit after the left shift, if the shifted bit is 0, putting the shifted data into the CRC register 1, if the shifted bit is 1, xoring the shifted data with the input polynomial value XOR, and putting the result into the CRC register 1;

4. repeating the third step until shifting left 8 times, thus the input data i_data [63:56] 8-bit data are processed, and the result is put into a CRC register 8;

5. exclusive OR of the input data i_data [55:48] with the upper 8 bits of CRC register 8, putting the result to the upper bits of CRC register 9, and putting the lower 8 bits of CRC register 8 with the lower bits of CRC register 9;

6. shifting the content of the CRC register 9 one bit left, filling the least significant bit with 0, checking the shifted-out bit after left shifting, if the shifted-out bit is 0, putting the shifted data into the CRC register 10, if the shifted-out bit is 1, xoring the shifted data with the input polynomial value XOR, and putting the result into the CRC register 10;

7. repeating the step six until shifting left 8 times, thus the input data i_data [55:48]8 bits of data are processed, and the result is put into the CRC register 17;

8. and so on, according to the above steps, until the input data i_data [7:0]8 bits are processed, the result is put into the CRC register 71, and the content of the CRC register 71 is put into the CRC initial register;

9. repeating the steps two to eight until all data needing to calculate CRC in the communication packet are processed, and taking the CRC register 71 as an output CRC calculated value o_crc;

10. if the input data i_data [63:0] does not need all CRC calculation, selecting calculation can be carried out by inputting the number i_lsb of valid bytes; if the number of the input valid bytes i_lsb is 1, only i_data [63:56] is needed to be calculated, and only the CRC register 8 is needed to be used as an output CRC calculated value o_crc; if the number of the input valid bytes i_lsb is 2, only i_data [63:48] is needed to be calculated, and only the CRC register 17 is needed to be used as an output CRC calculated value o_crc; similarly, if the number of input valid bytes i_lsb is 7, then only i_data [63:8] need to be calculated, only CRC register 62 needs to be used as output CRC calculated value o_crc; if the number of input valid bytes i_lsb is 0, then only i_data [63:0] need be calculated, and only CRC register 71 need be used as the output CRC calculated value o_crc.

Compared with the prior art, the technical scheme provided by the invention has the following advantages: the invention adopts the number of the input effective bytes on the premise of the fixed bit width of the data communication interface, and can dynamically compatible with the data with low bit width when calculating CRC, thereby simplifying the bit width conversion before CRC calculation, simultaneously directly calculating the CRC check value of multi-byte data in one beat, and improving the calculation efficiency.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

Fig. 1 is a schematic diagram of input information and output information of interface data according to an embodiment of the invention.

Description of the embodiments

In order that the above objects, features and advantages of the invention will be more clearly understood, a further description of the invention will be made. It should be noted that, without conflict, the embodiments of the present invention and features in the embodiments may be combined with each other.

In the description, it should be noted that the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. It should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms described above will be understood by those of ordinary skill in the art as the case may be.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the invention.

Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

In one embodiment, as shown in fig. 1, a CRC check calculation method for dynamically changing the effective bit width of interface data is implemented based on an FPGA, where input information of the interface data includes an input clock i_clk, a start flag i_start, an input data enable i_dv, an input data i_data, an input effective byte number i_lsb, an input CRC check initial VALUE c_init_value, and an input polynomial VALUE XOR, and output information of the interface data includes an output CRC calculation VALUE o_crc; the CRC calculation method comprises the following steps:

Based on the above embodiments, in a preferred embodiment, the sub-steps of performing CRC calculation at the interface transmitting end or the interface receiving end are:

In a specific embodiment, the interface bit width is 8 bytes (64 bits), the whole packet data is 256 bytes, the crc check is calculated from the 11 th byte, and the last two bytes are check values. The calculation is started from the 11 th byte, which is just the intermediate value of the second beat data, the previous implementation mode needs to convert the interface into one byte and then perform the crc calculation. The specific implementation steps are as follows:

before receiving effective data, presetting a CRC initial register when a start mark i_start is 1, carrying out initialization configuration, wherein the initialization configuration is all 1, namely the CRC initial register value is hexadecimal FFFF, simultaneously presetting 71 CRC registers, and the serial numbers are 0,1 and 2.

Since the calculation is started from the 11 th byte, the calculation is just the intermediate value of the second beat of data, so that the second beat of data of 6 bytes, of which the CRC needs to be calculated, needs to be used as input data i_data [63:16], i_data [15:0] to be supplemented with 0, the number i_lsb of the input valid bytes is 6, the calculation is carried out according to the steps two to eight in the technical scheme, and the content of a CRC register 53 is placed in a CRC initial register;

and repeating the second to eighth steps to calculate 17 to 248 bytes of intermediate data, wherein the input data i_data [63:0] is valid, the number i_lsb of the input valid bytes is 0, and the second to eighth steps are repeated to calculate according to the technical scheme, and the content of the CRC register 71 is put into the CRC initial register.

Since the last two bytes are check values and are not calculated, the number of valid bytes i_lsb of the last beat of data input is 6, namely, the 249 th to 254 th bytes are used as input data i_data [63:16], i_data [15:0] are supplemented with 0, the calculation is performed according to the steps two to eight in the technical scheme, and the content of the CRC register 53 is used as an output CRC calculated value o_crc.

The specific implementation codes of the method are shown as follows.

module i_64b_crc16#(

parameter C_INIT_VALUE = 16'hffff,

XOR = 16'h8005

)(

input i_clk ,

input i_start ,

input i_dv ,

input [2:0] i_lsb ,

input [63:0] i_data ,

output reg [15:0] o_crc

);

reg [15:0] crc;

wire [15:0] crc_tmp0 ;

wire [15:0] crc_tmp1 ;

wire [15:0] crc_tmp2 ;

wire [15:0] crc_tmp3 ;

wire [15:0] crc_tmp4 ;

wire [15:0] crc_tmp5 ;

wire [15:0] crc_tmp6 ;

wire [15:0] crc_tmp7 ;

wire [15:0] crc_tmp8 ;

wire [15:0] crc_tmp9 ;

wire [15:0] crc_tmp10 ;

wire [15:0] crc_tmp11 ;

wire [15:0] crc_tmp12 ;

wire [15:0] crc_tmp13 ;

wire [15:0] crc_tmp14 ;

wire [15:0] crc_tmp15 ;

wire [15:0] crc_tmp16 ;

wire [15:0] crc_tmp17 ;

wire [15:0] crc_tmp18 ;

wire [15:0] crc_tmp19 ;

wire [15:0] crc_tmp20 ;

wire [15:0] crc_tmp21 ;

wire [15:0] crc_tmp22 ;

wire [15:0] crc_tmp23 ;

wire [15:0] crc_tmp24 ;

wire [15:0] crc_tmp25 ;

wire [15:0] crc_tmp26 ;

wire [15:0] crc_tmp27 ;

wire [15:0] crc_tmp28 ;

wire [15:0] crc_tmp29 ;

wire [15:0] crc_tmp30 ;

wire [15:0] crc_tmp31 ;

wire [15:0] crc_tmp32 ;

wire [15:0] crc_tmp33 ;

wire [15:0] crc_tmp34 ;

wire [15:0] crc_tmp35 ;

wire [15:0] crc_tmp36 ;

wire [15:0] crc_tmp37 ;

wire [15:0] crc_tmp38 ;

wire [15:0] crc_tmp39 ;

wire [15:0] crc_tmp40 ;

wire [15:0] crc_tmp41 ;

wire [15:0] crc_tmp42 ;

wire [15:0] crc_tmp43 ;

wire [15:0] crc_tmp44 ;

wire [15:0] crc_tmp45 ;

wire [15:0] crc_tmp46 ;

wire [15:0] crc_tmp47 ;

wire [15:0] crc_tmp48 ;

wire [15:0] crc_tmp49 ;

wire [15:0] crc_tmp50 ;

wire [15:0] crc_tmp51 ;

wire [15:0] crc_tmp52 ;

wire [15:0] crc_tmp53 ;

wire [15:0] crc_tmp54 ;

wire [15:0] crc_tmp55 ;

wire [15:0] crc_tmp56 ;

wire [15:0] crc_tmp57 ;

wire [15:0] crc_tmp58 ;

wire [15:0] crc_tmp59 ;

wire [15:0] crc_tmp60 ;

wire [15:0] crc_tmp61 ;

wire [15:0] crc_tmp62 ;

wire [15:0] crc_tmp63 ;

wire [15:0] crc_tmp64 ;

wire [15:0] crc_tmp65 ;

wire [15:0] crc_tmp66 ;

wire [15:0] crc_tmp67 ;

wire [15:0] crc_tmp68 ;

wire [15:0] crc_tmp69 ;

wire [15:0] crc_tmp70 ;

wire [15:0] crc_tmp71 ;

reg [7:0] data ;

reg cv ;

always@(*)begin

if(i_dv)begin

if(i_lsb == 0 )begin

o_crc = crc_tmp71 ;

end

else if(i_lsb == 7 )begin

o_crc = crc_tmp62 ;

end

else if(i_lsb == 6 )begin

o_crc = crc_tmp53 ;

end

else if(i_lsb == 5 )begin

o_crc = crc_tmp44 ;

end

else if(i_lsb == 4 )begin

o_crc = crc_tmp35 ;

end

else if(i_lsb == 3 )begin

o_crc = crc_tmp26 ;

end

else if(i_lsb == 2 )begin

o_crc = crc_tmp17 ;

end

else if(i_lsb == 1 )begin

o_crc = crc_tmp8 ;

end

else

o_crc = crc ;

end

always@(posedge i_clk)begin

if(i_start)begin

crc <= C_INIT_VALUE;

end

else begin

if(i_dv)begin

if(i_lsb == 0 )begin

crc <= crc_tmp71 ;

end

else if(i_lsb == 7 )begin

crc <= crc_tmp62 ;

end

else if(i_lsb == 6 )begin

crc <= crc_tmp53 ;

end

else if(i_lsb == 5 )begin

crc <= crc_tmp44 ;

end

else if(i_lsb == 4 )begin

crc <= crc_tmp35 ;

end

else if(i_lsb == 3 )begin

crc <= crc_tmp26 ;

end

else if(i_lsb == 2 )begin

crc <= crc_tmp17 ;

end

else if(i_lsb == 1 )begin

crc <= crc_tmp8 ;

end

else begin

crc <= crc;

end

assign crc_tmp0 = {i_data[63:56] ^ crc[15:8],crc[7:0]};

assign crc_tmp1 = crc_tmp0[15] ? {crc_tmp0[14:0],1'b0} ^ XOR : {crc_tmp0[14:0],1'b0};

assign crc_tmp2 = crc_tmp1[15] ? {crc_tmp1[14:0],1'b0} ^ XOR : {crc_tmp1[14:0],1'b0};

assign crc_tmp3 = crc_tmp2[15] ? {crc_tmp2[14:0],1'b0} ^ XOR : {crc_tmp2[14:0],1'b0};

assign crc_tmp4 = crc_tmp3[15] ? {crc_tmp3[14:0],1'b0} ^ XOR : {crc_tmp3[14:0],1'b0};

assign crc_tmp5 = crc_tmp4[15] ? {crc_tmp4[14:0],1'b0} ^ XOR : {crc_tmp4[14:0],1'b0};

assign crc_tmp6 = crc_tmp5[15] ? {crc_tmp5[14:0],1'b0} ^ XOR : {crc_tmp5[14:0],1'b0};

assign crc_tmp7 = crc_tmp6[15] ? {crc_tmp6[14:0],1'b0} ^ XOR : {crc_tmp6[14:0],1'b0};

assign crc_tmp8 = crc_tmp7[15] ? {crc_tmp7[14:0],1'b0} ^ XOR : {crc_tmp7[14:0],1'b0};

assign crc_tmp9 = {i_data[55:48] ^ crc_tmp8[15:8],crc_tmp8[7:0]};

assign crc_tmp10 = crc_tmp9 [15] ? {crc_tmp9 [14:0],1'b0} ^ XOR : {crc_tmp9 [14:0],1'b0};

assign crc_tmp11 = crc_tmp10[15] ? {crc_tmp10[14:0],1'b0} ^ XOR : {crc_tmp10[14:0],1'b0};

assign crc_tmp12 = crc_tmp11[15] ? {crc_tmp11[14:0],1'b0} ^ XOR : {crc_tmp11[14:0],1'b0};

assign crc_tmp13 = crc_tmp12[15] ? {crc_tmp12[14:0],1'b0} ^ XOR : {crc_tmp12[14:0],1'b0};

assign crc_tmp14 = crc_tmp13[15] ? {crc_tmp13[14:0],1'b0} ^ XOR : {crc_tmp13[14:0],1'b0};

assign crc_tmp15 = crc_tmp14[15] ? {crc_tmp14[14:0],1'b0} ^ XOR : {crc_tmp14[14:0],1'b0};

assign crc_tmp16 = crc_tmp15[15] ? {crc_tmp15[14:0],1'b0} ^ XOR : {crc_tmp15[14:0],1'b0};

assign crc_tmp17 = crc_tmp16[15] ? {crc_tmp16[14:0],1'b0} ^ XOR : {crc_tmp16[14:0],1'b0};

assign crc_tmp18 = {i_data[47:40] ^ crc_tmp17[15:8],crc_tmp17[7:0]};

assign crc_tmp19 = crc_tmp18[15] ? {crc_tmp18[14:0],1'b0} ^ XOR : {crc_tmp18[14:0],1'b0};

assign crc_tmp20 = crc_tmp19[15] ? {crc_tmp19[14:0],1'b0} ^ XOR : {crc_tmp19[14:0],1'b0};

assign crc_tmp21 = crc_tmp20[15] ? {crc_tmp20[14:0],1'b0} ^ XOR : {crc_tmp20[14:0],1'b0};

assign crc_tmp22 = crc_tmp21[15] ? {crc_tmp21[14:0],1'b0} ^ XOR : {crc_tmp21[14:0],1'b0};

assign crc_tmp23 = crc_tmp22[15] ? {crc_tmp22[14:0],1'b0} ^ XOR : {crc_tmp22[14:0],1'b0};

assign crc_tmp24 = crc_tmp23[15] ? {crc_tmp23[14:0],1'b0} ^ XOR : {crc_tmp23[14:0],1'b0};

assign crc_tmp25 = crc_tmp24[15] ? {crc_tmp24[14:0],1'b0} ^ XOR : {crc_tmp24[14:0],1'b0};

assign crc_tmp26 = crc_tmp25[15] ? {crc_tmp25[14:0],1'b0} ^ XOR : {crc_tmp25[14:0],1'b0};

assign crc_tmp27 = {i_data[39:32] ^ crc_tmp26[15:8],crc_tmp26[7:0]};

assign crc_tmp28 = crc_tmp27[15] ? {crc_tmp27[14:0],1'b0} ^ XOR : {crc_tmp27[14:0],1'b0};

assign crc_tmp29 = crc_tmp28[15] ? {crc_tmp28[14:0],1'b0} ^ XOR : {crc_tmp28[14:0],1'b0};

assign crc_tmp30 = crc_tmp29[15] ? {crc_tmp29[14:0],1'b0} ^ XOR : {crc_tmp29[14:0],1'b0};

assign crc_tmp31 = crc_tmp30[15] ? {crc_tmp30[14:0],1'b0} ^ XOR : {crc_tmp30[14:0],1'b0};

assign crc_tmp32 = crc_tmp31[15] ? {crc_tmp31[14:0],1'b0} ^ XOR : {crc_tmp31[14:0],1'b0};

assign crc_tmp33 = crc_tmp32[15] ? {crc_tmp32[14:0],1'b0} ^ XOR : {crc_tmp32[14:0],1'b0};

assign crc_tmp34 = crc_tmp33[15] ? {crc_tmp33[14:0],1'b0} ^ XOR : {crc_tmp33[14:0],1'b0};

assign crc_tmp35 = crc_tmp34[15] ? {crc_tmp34[14:0],1'b0} ^ XOR : {crc_tmp34[14:0],1'b0};

assign crc_tmp36 = {i_data[31:24] ^ crc_tmp35[15:8],crc_tmp35[7:0]};

assign crc_tmp37 = crc_tmp36[15] ? {crc_tmp36[14:0],1'b0} ^ XOR : {crc_tmp36[14:0],1'b0};

assign crc_tmp38 = crc_tmp37[15] ? {crc_tmp37[14:0],1'b0} ^ XOR : {crc_tmp37[14:0],1'b0};

assign crc_tmp39 = crc_tmp38[15] ? {crc_tmp38[14:0],1'b0} ^ XOR : {crc_tmp38[14:0],1'b0};

assign crc_tmp40 = crc_tmp39[15] ? {crc_tmp39[14:0],1'b0} ^ XOR : {crc_tmp39[14:0],1'b0};

assign crc_tmp41 = crc_tmp40[15] ? {crc_tmp40[14:0],1'b0} ^ XOR : {crc_tmp40[14:0],1'b0};

assign crc_tmp42 = crc_tmp41[15] ? {crc_tmp41[14:0],1'b0} ^ XOR : {crc_tmp41[14:0],1'b0};

assign crc_tmp43 = crc_tmp42[15] ? {crc_tmp42[14:0],1'b0} ^ XOR : {crc_tmp42[14:0],1'b0};

assign crc_tmp44 = crc_tmp43[15] ? {crc_tmp43[14:0],1'b0} ^ XOR : {crc_tmp43[14:0],1'b0};

assign crc_tmp45 = {i_data[23:16] ^ crc_tmp44[15:8],crc_tmp44[7:0]};

assign crc_tmp46 = crc_tmp45[15] ? {crc_tmp45[14:0],1'b0} ^ XOR : {crc_tmp45[14:0],1'b0};

assign crc_tmp47 = crc_tmp46[15] ? {crc_tmp46[14:0],1'b0} ^ XOR : {crc_tmp46[14:0],1'b0};

assign crc_tmp48 = crc_tmp47[15] ? {crc_tmp47[14:0],1'b0} ^ XOR : {crc_tmp47[14:0],1'b0};

assign crc_tmp49 = crc_tmp48[15] ? {crc_tmp48[14:0],1'b0} ^ XOR : {crc_tmp48[14:0],1'b0};

assign crc_tmp50 = crc_tmp49[15] ? {crc_tmp49[14:0],1'b0} ^ XOR : {crc_tmp49[14:0],1'b0};

assign crc_tmp51 = crc_tmp50[15] ? {crc_tmp50[14:0],1'b0} ^ XOR : {crc_tmp50[14:0],1'b0};

assign crc_tmp52 = crc_tmp51[15] ? {crc_tmp51[14:0],1'b0} ^ XOR : {crc_tmp51[14:0],1'b0};

assign crc_tmp53 = crc_tmp52[15] ? {crc_tmp52[14:0],1'b0} ^ XOR : {crc_tmp52[14:0],1'b0};

assign crc_tmp54 = {i_data[15:8] ^ crc_tmp53[15:8],crc_tmp53[7:0]};

assign crc_tmp55 = crc_tmp54[15] ? {crc_tmp54[14:0],1'b0} ^ XOR : {crc_tmp54[14:0],1'b0};

assign crc_tmp56 = crc_tmp55[15] ? {crc_tmp55[14:0],1'b0} ^ XOR : {crc_tmp55[14:0],1'b0};

assign crc_tmp57 = crc_tmp56[15] ? {crc_tmp56[14:0],1'b0} ^ XOR : {crc_tmp56[14:0],1'b0};

assign crc_tmp58 = crc_tmp57[15] ? {crc_tmp57[14:0],1'b0} ^ XOR : {crc_tmp57[14:0],1'b0};

assign crc_tmp59 = crc_tmp58[15] ? {crc_tmp58[14:0],1'b0} ^ XOR : {crc_tmp58[14:0],1'b0};

assign crc_tmp60 = crc_tmp59[15] ? {crc_tmp59[14:0],1'b0} ^ XOR : {crc_tmp59[14:0],1'b0};

assign crc_tmp61 = crc_tmp60[15] ? {crc_tmp60[14:0],1'b0} ^ XOR : {crc_tmp60[14:0],1'b0};

assign crc_tmp62 = crc_tmp61[15] ? {crc_tmp61[14:0],1'b0} ^ XOR : {crc_tmp61[14:0],1'b0};

assign crc_tmp63 = {i_data[7:0] ^ crc_tmp62[15:8],crc_tmp62[7:0]};

assign crc_tmp64 = crc_tmp63[15] ? {crc_tmp63[14:0],1'b0} ^ XOR : {crc_tmp63[14:0],1'b0};

assign crc_tmp65 = crc_tmp64[15] ? {crc_tmp64[14:0],1'b0} ^ XOR : {crc_tmp64[14:0],1'b0};

assign crc_tmp66 = crc_tmp65[15] ? {crc_tmp65[14:0],1'b0} ^ XOR : {crc_tmp65[14:0],1'b0};

assign crc_tmp67 = crc_tmp66[15] ? {crc_tmp66[14:0],1'b0} ^ XOR : {crc_tmp66[14:0],1'b0};

assign crc_tmp68 = crc_tmp67[15] ? {crc_tmp67[14:0],1'b0} ^ XOR : {crc_tmp67[14:0],1'b0};

assign crc_tmp69 = crc_tmp68[15] ? {crc_tmp68[14:0],1'b0} ^ XOR : {crc_tmp68[14:0],1'b0};

assign crc_tmp70 = crc_tmp69[15] ? {crc_tmp69[14:0],1'b0} ^ XOR : {crc_tmp69[14:0],1'b0};

assign crc_tmp71 = crc_tmp70[15] ? {crc_tmp70[14:0],1'b0} ^ XOR : {crc_tmp70[14:0],1'b0}。

The foregoing is only a specific embodiment of the invention to enable those skilled in the art to understand or practice the invention. Although described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the embodiments, and they should be construed as covering the scope of the appended claims.

Claims

1. The CRC calculation method for realizing dynamic change of the effective bit width of the interface data based on the FPGA is characterized in that the input information of the interface data comprises an input clock i_clk, a start mark i_start, an input data enable i_dv, input data i_data, an input effective byte number i_lsb, an input CRC initial VALUE C_INIT_VALUE and an input polynomial VALUE XOR, and the output information of the interface data comprises an output CRC calculation VALUE o_crc; the CRC calculation method comprises the following steps:

2. The method for implementing CRC calculation based on FPGA according to claim 1, wherein the sub-steps of performing CRC calculation at the interface transmitting end or the interface receiving end are as follows: