CN114726482B - SPI data transmission method - Google Patents
SPI data transmission method Download PDFInfo
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- CN114726482B CN114726482B CN202210403772.4A CN202210403772A CN114726482B CN 114726482 B CN114726482 B CN 114726482B CN 202210403772 A CN202210403772 A CN 202210403772A CN 114726482 B CN114726482 B CN 114726482B
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- 230000005540 biological transmission Effects 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 15
- 238000004891 communication Methods 0.000 claims abstract description 20
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000012795 verification Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/009—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location arrangements specific to transmitters
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
- H04L1/0091—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location arrangements specific to receivers, e.g. format detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/1607—Details of the supervisory signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/12—Arrangements for detecting or preventing errors in the information received by using return channel
- H04L1/16—Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
- H04L1/18—Automatic repetition systems, e.g. Van Duuren systems
- H04L1/1867—Arrangements specially adapted for the transmitter end
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
The invention discloses an SPI data transmission method, which is used for communication between a master device and a slave device through SPI, and comprises the following steps: a. transmitting data; b. generating a slave device side checksum; c. generating a master device end checksum; d. and comparing the master equipment end checksum with the equipment end checksum and judging the correctness of the transmission according to the comparison result. The invention can effectively detect the error of data transmission, solve the problem of data packet loss in the conventional SPI communication and improve the accuracy and stability of the communication.
Description
Technical Field
The invention relates to a communication technology, in particular to an SPI data transmission checking method.
Background
SPI (Serial Peripheral Interfacer serial peripheral interface) is a synchronous serial communication interface developed by Motorola, inc. for serial connection between a microprocessor and a controller and peripheral expansion chip.
SPI is a high-speed, full duplex, synchronous communication bus, and only occupies four wires on the pin of chip, has practiced thrift the pin of chip, saves space on the overall arrangement of PCB simultaneously, provides the convenience, just because of this kind of simple easy-to-use characteristic, and this kind of communication protocol has been integrated to the chip of increasing now.
The SPI interface is used for synchronous serial data transmission between the CPU and the peripheral low-speed device, under the shift pulse of the main device, the data is transmitted according to the bit, the high bit is in front, the low bit is in back, and the full duplex communication is performed, so that the data transmission speed is generally faster than that of the I2C bus, and the speed can reach several Mbps.
The prior art has the defects that SPI communication is directly carried out between the processors through a digital isolation chip, and the following defects are caused: in the case of too fast data transmission or other interference, the data may be lost, resulting in communication data errors and software BUG.
Disclosure of Invention
In order to overcome the defects, the invention aims to provide an SPI data transmission method which is used for master equipment and slave equipment to realize SPI communication, so that the problem of data packet loss in the conventional SPI communication can be solved, and the accuracy and stability of the communication are improved.
In order to achieve the above purpose, the invention is realized by adopting the following technical scheme:
the SPI data transmission method disclosed by the invention is used for the communication between the master equipment and the slave equipment through the SPI, and comprises the following steps:
a. transmitting data: the method comprises the steps that a master device sends first data to a slave device and the first data are stored locally in the master device;
b. generating a slave device side checksum: after receiving the received value of the first data, the slave device sends second data related to the received value of the first data to the master device; calculating to generate third data according to a preset operation rule through the received value of the first data and the second data, and sending the third data to the main equipment;
c. generating a master device side checksum: after receiving the received value of the second data and the received value of the third data, the main equipment calculates the received values of the first data and the second data according to the preset operation rule to generate fourth data;
d. comparing the master device side checksum with the device side checksum: and comparing the received value of the third data with the fourth data, and judging that the transmitted data is correct when the received value of the third data is the same as the fourth data.
The third data is the check sum of the slave equipment end, and the fourth data is the check sum of the master equipment end.
Further, in step d, the method further comprises:
and c, when the received value of the third data is different from the fourth data, judging that the transmitted data is incorrect, and re-executing the step a.
Of course, after detecting the error of data transmission, the data can be retransmitted until the data is detected to be correct, and then the next group of data is transmitted.
Preferably, the receiving values of the first data and the first data are both 8-bit data, and the receiving values of the second data and the second data are both 16-bit data.
For a 16-bit microprocessor, the data transferred is typically in bytes or words.
Further preferably, the received value of the first data is address information of a register, and the second data is data information of the register. For accomplishing the master to read the register data in the slave, the data is typically buffered for transmission through the registers.
Preferably, the predetermined operation rule is as follows:
and exclusive-or the 8bit data with the high 8 bits of the 16bit data and exclusive-or the low 8 bits of the 16bit data. By adopting the operation rule, when the received value of the first data and/or the received value of the second data and/or the received value of the third data are incorrect, the received value of the third data is inconsistent with the received value of the fourth data, and errors in data transmission can be effectively detected.
Further preferably, the predetermined operation rule is enhanced as follows:
and performing AND operation on the result generated after the 8bit data is exclusive-or and the upper 8 bits of the 16bit data are exclusive-or and the lower 8 bits of the 16bit data and 0x 400.
The AND operation can effectively avoid the situation that the data at the two ends of the master equipment and the slave equipment are simultaneously misplaced to cause verification to pass, and further ensures the correctness of communication.
Preferably, clocks of the master device and the slave device are synchronized.
Further preferably, the master device and the slave device use the same clock.
The invention can effectively detect the error of data transmission, solve the problem of data packet loss in the prior SPI communication, and improve the accuracy and stability of the communication; and software BUG can be avoided.
Drawings
FIG. 1 is a flow chart of the present invention.
Fig. 2 is a schematic diagram of a data format of embodiment 3.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
Example 1
As shown in fig. 1, this embodiment discloses an SPI data transmission method, which is used for communicating between a master device and a slave device through an SPI, and includes the following steps:
a. the method comprises the steps that a master device sends first data to a slave device and the first data are stored locally in the master device;
b. after receiving the received value of the first data, the slave device sends second data related to the received value of the first data to the master device; calculating to generate third data according to a preset operation rule through the received value of the first data and the second data, and sending the third data to the main equipment;
c. after receiving the received value of the second data and the received value of the third data, the main equipment calculates the received values of the first data and the second data according to the preset operation rule to generate fourth data;
d. and comparing the received value of the third data with the fourth data, and judging that the transmitted data is correct when the received value of the third data is the same as the fourth data.
And c, when the received value of the third data is different from the fourth data, judging that the transmitted data is incorrect, and re-executing the step a.
The clocks of the master device and the slave device are synchronous, and preferably the same clock is adopted by the master device and the slave device. The receiving values of the first data and the first data are both 8-bit data, and the receiving values of the second data and the second data are both 16-bit data.
The predetermined operation rule is as follows:
and performing exclusive OR operation on the 8-bit data and the upper 8 bits and the lower 8 bits of the 16-bit data respectively.
Example 2
The present embodiment differs from embodiment 1 in that a predetermined operation rule is adopted as follows:
and performing exclusive OR operation on the 8-bit data and the upper 8 bits and the lower 8 bits of the 16-bit data respectively, and performing AND operation on the result generated after the exclusive OR operation and the 0x 400.
Example 3
As shown in fig. 2, on the basis of embodiment 2, this embodiment discloses an example of SPI data transmission, specifically as follows:
the host A and the slave B communicate through SPI and use the same clock, the host A sends the register information reg_num needed by 8 bits to the slave B, meanwhile, the host A stores the sending information locally, after the slave B receives the 8bit information reg_num, the register information needed by the host A is sent to the host 16bit-value, and then a checksum_sum is automatically calculated and sent to the host A, and the specific calculation method is as follows:
8bit information reg_num received from the slave B is exclusive or the upper 8 bits of the upper value, exclusive or the lower 8 bits of the upper value, and finally, the upper 0x400 is used as a tag bit, and the following formula is adopted:
check_sum=（reg_num~⊕valueH8⊕valueL8）＆0x400
in the above formula: value H8 is the upper 8 bits of value and value L8 is the lower 8 bits of value.
After receiving the 16bit_value, the host calculates whether the checksum of the local reg_sum and the received value is consistent with the checksum sent by the slave B through the same algorithm. If so, the set of data is deemed correct, otherwise, the set of data is retransmitted.
The purpose of the above 0x400 is to prevent the data on both sides from being misplaced at the same time, which results in verification passing, but the actual data has problems.
The invention can effectively detect the error of data transmission, solve the problem of data packet loss in the prior SPI communication, and improve the accuracy and stability of the communication; and software BUG can be avoided.
Of course, the present invention is capable of other various embodiments and its several details are capable of modification and variation in light of the present invention by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (4)
1. The SPI data transmission method is used for the communication between the master device and the slave device through the SPI and is characterized by comprising the following steps:
a. transmitting data: the method comprises the steps that a master device sends first data to a slave device and the first data are stored locally in the master device;
b. generating a slave device side checksum: after receiving the received value of the first data, the slave device sends second data related to the received value of the first data to the master device; calculating to generate third data according to a preset operation rule through the received value of the first data and the second data, and sending the third data to the main equipment;
c. generating a master device side checksum: after receiving the received value of the second data and the received value of the third data, the main equipment calculates the received values of the first data and the second data according to the preset operation rule to generate fourth data;
d. comparing the master device side checksum with the device side checksum: comparing the received value of the third data with the fourth data, and judging that the transmitted data is correct when the received value of the third data is the same as the fourth data;
the receiving values of the first data and the first data are 8-bit data, and the receiving values of the second data and the second data are 16-bit data;
the receiving value of the first data is the address information of a register, and the second data is the data information of the register;
the predetermined operation rule is as follows:
exclusive-or the 8bit data with the high 8bit of the 16bit data and exclusive-or the low 8bit of the 16bit data;
alternatively, the predetermined operation rule is as follows:
and performing AND operation on the result generated after the 8bit data is exclusive-or and the upper 8 bits of the 16bit data are exclusive-or and the lower 8 bits of the 16bit data and 0x 400.
2. The SPI data transmission method according to claim 1, characterized in that: in step d, further comprising:
and c, when the received value of the third data is different from the fourth data, judging that the transmitted data is incorrect, and re-executing the step a.
3. The SPI data transmission method according to claim 1, characterized in that: the clocks of the master device and the slave device are synchronous.
4. A SPI data transmission method according to claim 3, characterized in that: the master device and the slave device adopt the same clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210403772.4A CN114726482B (en) | 2022-04-18 | 2022-04-18 | SPI data transmission method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210403772.4A CN114726482B (en) | 2022-04-18 | 2022-04-18 | SPI data transmission method |
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| Publication Number | Publication Date |
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| CN114726482A CN114726482A (en) | 2022-07-08 |
| CN114726482B true CN114726482B (en) | 2024-03-22 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1930814A (en) * | 2004-01-16 | 2007-03-14 | Zih公司 | Method and system for calculating and verifying the integrity of data in a data transmission system |
| CN105183690A (en) * | 2015-09-02 | 2015-12-23 | 北京航天控制仪器研究所 | Double buffering data transmission method based on serial peripheral interface (SPI) bus communication protocol |
| CN113176966A (en) * | 2021-03-12 | 2021-07-27 | 青芯半导体科技(上海)有限公司 | System and method for checking validity of SPI (Serial peripheral interface) received data |
| CN114128180A (en) * | 2019-06-27 | 2022-03-01 | 奥斯兰姆奥普托半导体股份有限两合公司 | Electronic device with CRC generator and method for transmitting data from electronic device to control unit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI310638B (en) * | 2004-04-09 | 2009-06-01 | Hon Hai Prec Ind Co Ltd | System and method for checking validity of data transmission |
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- 2022-04-18 CN CN202210403772.4A patent/CN114726482B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1930814A (en) * | 2004-01-16 | 2007-03-14 | Zih公司 | Method and system for calculating and verifying the integrity of data in a data transmission system |
| CN105183690A (en) * | 2015-09-02 | 2015-12-23 | 北京航天控制仪器研究所 | Double buffering data transmission method based on serial peripheral interface (SPI) bus communication protocol |
| CN114128180A (en) * | 2019-06-27 | 2022-03-01 | 奥斯兰姆奥普托半导体股份有限两合公司 | Electronic device with CRC generator and method for transmitting data from electronic device to control unit |
| CN113176966A (en) * | 2021-03-12 | 2021-07-27 | 青芯半导体科技(上海)有限公司 | System and method for checking validity of SPI (Serial peripheral interface) received data |
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