CN115955234B - Majority decision circuit energy consumption optimizing device and optimizing method - Google Patents
Majority decision circuit energy consumption optimizing device and optimizing method Download PDFInfo
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Abstract
The invention discloses a majority decision circuit energy consumption optimizing device and an optimizing method, wherein the majority decision circuit energy consumption optimizing device comprises a decision module and a plurality of majority decision circuits with different structure types, the plurality of the majority decision circuits with different structure types are mutually connected in parallel, the majority decision circuits respond to at least three input logic signals and are used for generating majority voting output signals, the decision module is used for calculating and comparing the extra total energy consumption caused by the nonreciprocal calculation of each majority decision circuit according to the probability that each logic signal is at a high level, and enabling the majority decision circuit with the lowest extra total energy consumption to receive each logic signal and enabling the rest majority decision circuits to pause receiving each logic signal. According to the input data characteristics, the optimal majority decision circuit topological structure is selected, so that the energy consumption of the target majority decision circuit is reduced to be lower, and the method is simple and easy to implement.
Description
Technical Field
The invention belongs to the field of digital circuits, and particularly relates to an energy consumption optimizing device and an optimizing method for a majority decision circuit.
Background
Global mobile data traffic has shown an exponentially increasing trend as the fifth generation mobile communication systems began to be commercially deployed. Massive data processing can result in significant energy consumption and greenhouse gas emissions, exacerbating global warming. The continuous rise of energy consumption will seriously obstruct the energy saving and emission reduction of the digital communication system and the green and healthy development of future information and communication industry. In order to reduce the energy consumption of the digital communication system, the power information and communication industry are green and healthy to develop, and most decision circuits serving as physical carriers of the digital communication system face low energy consumption challenges.
Studies have shown that the energy consumption caused by the calculation of the error rate will take the dominant role of the energy consumption of the digital communication circuit, and that most decision circuits are one of the digital communication circuits, the energy consumption of which is also affected by the calculation of the error rate, whereas the prior art has rarely considered the influence of the calculation of the error rate on the energy consumption of most decision circuits.
Disclosure of Invention
The invention aims to provide an energy consumption optimizing device of a majority decision circuit, which is used for calculating extra energy consumption caused by nonreciprocal calculation of each logic circuit in the majority decision circuit to obtain extra total energy consumption caused by nonreciprocal calculation of the majority decision circuit, so that the selection of the structure of the majority decision circuit in information processing is controlled by a control signal, and the energy consumption of the majority decision circuit is reduced.
The technical scheme of the invention is as follows: the device comprises a judging module and a plurality of majority judgment circuits with different structure types, wherein the plurality of the majority judgment circuits with different structure types are connected in parallel, the majority judgment circuits respond to at least three input logic signals and are used for generating majority voting output signals, the judging module is used for calculating and comparing the extra total energy consumption caused by the non-reciprocity calculation of each of the plurality of the judgment circuits according to the probability that each logic signal is at a high level, and enabling the majority judgment circuit with the lowest extra total energy consumption to receive each logic signal and enabling the rest of the plurality of the judgment circuits to pause receiving each logic signal.
The energy consumption optimizing device for multiple decision circuits is characterized in that the additional total energy consumption is the sum of the additional energy consumption caused by all two-input exclusive-OR gates and two-input AND gate nonreciprocal computation in each multiple decision circuit.
The majority decision circuit energy consumption optimizing device comprises the following energy consumption caused by the non-reciprocity calculation of each two-input exclusive-OR gate:
(1-[P x P y +(1-P x )(1-P y )] 2 -[(1-P x )P y +P x (1-P y )] 2 )In(ε -1 )
the energy consumption caused by each two-input AND gate nonreciprocal calculation is as follows:
(1-(1-P x P y ) 2 -(P x P y ) 2 )In(ε -1 )
wherein the method comprises the steps ofP x AndP y for inputting the probability that the logic signals of the exclusive-or gates or the AND gates of the two inputs are high level, the calculated error rates epsilon of all the exclusive-or gates of the two inputs and the AND gates of the two inputs in the majority decision circuit are the same;
when the input signal to each two-input exclusive-or gate or two-input and gate is the logic signal to which the majority decision circuit responds,P x andP y the FPGA calculates the input logic signals after statistics;
when the input signal inputted into each two-input exclusive-or gate or two-input and gate is the output signal of the other two-input exclusive-or gate or two-input and gate,P x andP y the probability of a high level is output for the other two-input exclusive-or gate or two-input and gate.
The probability of the two-input exclusive-OR gate outputting a high level isP x (1-P y )+P y (1-P x ) The probability of the two-input AND gate outputting a high level isP x P y 。
The invention also provides an energy consumption optimization method of the majority decision circuit, wherein the majority decision circuit comprises a plurality of majority decision circuits with different structure types, and the energy consumption optimization method comprises the following steps:
s1, collecting the probability that all logic signals input into various majority decision circuits are respectively high level;
s2, calculating and comparing the extra total energy consumption caused by the non-reciprocity calculation of each majority decision circuit;
s3, enabling the majority decision circuit with the lowest additional total energy consumption to receive each logic signal, and enabling the rest majority decision circuits to stop receiving each logic signal.
The beneficial effects of the invention are as follows: the invention uses the judging module to judge the energy consumption of the majority decision circuit under different topological structures by analyzing the probability distribution of the input logic signals, and controls the selection of the structure of the majority decision circuit during information processing by the control signals, thereby reducing the energy consumption of the majority decision circuit. According to the input data characteristics, the optimal majority decision circuit topological structure is selected, so that the energy consumption of the target majority decision circuit is reduced to be lower, and the method is simple and easy to implement.
Drawings
FIG. 1 is a schematic diagram of two topologies of a majority decision circuit;
fig. 2 is a schematic diagram of a majority decision circuit topology selection module.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The energy consumption caused by the calculation of the error rate will dominate the energy consumption of the digital communication circuit, most decision circuits being one of the digital communication circuits, which energy consumption is also affected by the calculation of the error rate. The energy consumption caused by calculating the error rate can be counted by the reciprocity (reciprocity) of the calculation process. The one-time computation process to satisfy reciprocity can be described by the following formula:
ƒ(ƒ(m))=m（1）
i.e. inputmThe obtained calculation result is used as input to perform the same calculation again, and the output is stillm. If a computation process has non-reciprocity, i.e., ƒ (ƒ (m)). Noteq.m, then the input-output state transition process in this computation generates additional energy consumption (in use)DRepresented by "Riechers P M, boyd A B, wimsatt G W, et al Balancing error and d)issipation in computing[J]Physical Review Research, 2020, 2 (3): 033524. "the following formula is given:
wherein [ is Ai Fosen brackets, the conditions in brackets are satisfied with 1, and the conditions are not satisfied with 0.
Representing the desire under a distribution that the input m satisfies. Epsilon is the probability of calculating an error. For example, for a clock frequency of 3GHz, the calculated error rate is 10 -26 The energy consumption caused by the error rate at the time of each operation is 30kT (where k is boltzmann constant and T is kelvin temperature) or more.
Taking a two-input single exclusive-or gate and an and gate as an example, the initial and final states of the two-input exclusive-or gate calculation process are shown in table 1,x i 、y i two input level signals respectively being two input exclusive-or gates,z i for output level signals of two-input exclusive-OR gate, the scribe line region represents a calculation process in which the output signals do not satisfy reciprocity, i.ez 0 Andz 1 inconsistent, this process generates additional energy consumption. The initial and final states of the two-input and gate calculation process are shown in table 2,x i 、y i the level signals of the two inputs of the two-input AND gate,z i for output level signals of two-input AND gates, the scribe area represents a calculation process in which the output signals do not satisfy reciprocity, i.ez 0 Andz 1 inconsistent, this process generates additional energy consumption.
TABLE 1 initial and final states of two-input exclusive-OR gate computation
TABLE 2 initial and final states of two-input AND gate calculations
For a two-input exclusive-or gate, in order to avoid the situation of the four non-reciprocal calculation processes, it is necessary to ensurez 0 Andz 1 i.e.: only (0, 0) or (1, 1) can be input after (x, y) = (0, 0) or (1, 1) is input, and only (1, 0) or (0, 1) can be input after (x, y) = (0, 1) or (1, 0) is input.
For a two-input AND gate, in order to avoid the situation of the four non-reciprocal calculation processes, it is necessary to ensurez 0 Andz 1 i.e.: after (x, y) = (0, 0) or (0, 1) or (1, 0), only (0, 0) or (0, 1) or (1, 0) can be input continuously, and after (x, y) = (1, 1) only (1, 1) can be input continuously.
Considering that the sequences of single logic gate input at two inputs are mutually independent in time and space, the probability of 1 input at two ends isp x Andp y and calculating the probability of the non-reciprocity calculation of the two-input exclusive-OR gate according to the definition of the non-reciprocity calculation of the two-input exclusive-OR gate. The probability of the two-input exclusive-or gate continuing to input (0, 0) or (1, 1) after inputting (x, y) = (0, 0) or (1, 1) is: [p x p y +(1-p x )(1-p y )] 2 . The probability of the two-input exclusive-OR gate continuing to input (1, 0) or (0, 1) after inputting (x, y) = (0, 1) or (1, 0) is [ (1 ]p x )p y +p x (1-p y )] 2 . The probability of the two-input xor gate being non-reciprocal is thus (1-p x p y +(1-p x )(1-p y )] 2 -[(1-p x )p y +p x (1-p y )] 2 ) The energy consumption caused by the two-input exclusive-OR gate nonreciprocal calculation is as follows:
(1-[p x p y +(1-p x )(1-p y )] 2 -[(1-p x )p y +p x (1-p y )] 2 )In(ε -1 )（3）
similarly, according to the definition of the two-input AND gate nonreciprocal computation, the probability of the two-input AND gate nonreciprocal computation is computed. The probability of the two-input AND gate continuing to input (0, 0) or (0, 1) or (1, 0) after input (x, y) = (0, 0) or (0, 1) or (1, 0) is: (1-p x p y ) 2 . The probability of the two-input and gate continuing to input (1, 1) after input (x, y) = (1, 1) is: (p x p y ) 2 . Therefore, the probability of the two-input AND gate generating nonreciprocal computation is (1-p x p y ) 2 -(p x p y ) 2 ) The energy consumption caused by the two-input AND gate nonreciprocal calculation is as follows:
(1-(1-p x p y ) 2 -(p x p y ) 2 )In(ε -1 )(4)
thus, according to equations (3) (4), the energy consumption at the time of the two-input exclusive-or gate and the two-input and gate nonreciprocal computation can be calculated.
Examples
As shown in fig. 2, the energy consumption optimizing device of the majority decision circuit includes a decision module, a plurality of majority decision circuits of different structure types, wherein the plurality of majority decision circuits of different structure types are connected in parallel, the majority decision circuit responds to at least three logic signals input for generating a majority vote output signal, the decision module is used for calculating and comparing the extra total energy consumption caused by the non-reciprocal calculation of each of the plurality of decision circuits according to the probability that each logic signal is at a high level, and enabling the majority decision circuit with the lowest extra total energy consumption to receive each logic signal, and enabling the rest of the plurality of decision circuits to pause receiving each logic signal.
The additional energy consumption is the sum of the additional energy consumption caused by the non-reciprocal calculation of all the two-input exclusive-OR gates and the two-input AND gates in the majority decision circuit.
The energy consumption caused by each two-input exclusive-OR gate nonreciprocal calculation is as follows:
(1-[P x P y +(1-P x )(1-P y )] 2 -[(1-P x )P y +P x (1-P y )] 2 )In(ε -1 ) （5）
the energy consumption caused by each two-input AND gate nonreciprocal calculation is as follows:
(1-(1-P x P y ) 2 -(P x P y ) 2 )In(ε -1 ) （6）
wherein the method comprises the steps ofP x AndP y the probability that the logic signal of each two-input exclusive-or gate or and gate is high is input.
When the input signal to each two-input exclusive-or gate or two-input and gate is the logic signal to which the majority decision circuit responds,P x andP y the FPGA calculates the input logic signals after statistics;
when the input signal inputted into each two-input exclusive-or gate or two-input and gate is the output signal of the other two-input exclusive-or gate or two-input and gate,P x andP y the probability of a high level is output for the other two-input exclusive-or gate or two-input and gate.
The probability of the two-input exclusive-OR gate outputting a high level isP x (1-P y )+P y (1-P x ) The probability of the two-input AND gate outputting a high level isP x P y 。
The calculated error rate epsilon of all the two-input exclusive-or gates and the two-input and gates in the majority decision circuit is the same.
When the majority decision circuit is a three-input coincidence voter circuit, also called a three-input decision circuit, the decision module is used for calculating and comparing the additional total energy consumption caused by the non-reciprocity calculation of various three-input decision circuits according to the probability that the input X, Y, Z logic signals are high, and enabling the three-input decision circuit with the lowest additional total energy consumption to receive the three logic signals and enabling the rest three-input decision circuits to suspend receiving the logic signals.
The majority decision circuit energy consumption optimizing device comprises a three-input decision circuit of the following two topological structure types, such as a three-input decision circuit of (a) in fig. 1, which consists of 2 AND gates AND1/2 AND2 exclusive OR gates XOR1/2, AND a three-input decision circuit of (b) in fig. 1, which consists of 1 AND gate AND1 AND 3 exclusive OR gates XOR 1/2/3.
From the above, it can be seen that the probabilities of the three input terminals X, Y, Z respectively inputting 1 are respectivelyp x 、p y 、p z The extra energy consumption caused by the nonreciprocal computation of the majority decision circuit shown in fig. 1 (a) can be expressed as the sum of all two-input exclusive-or gates and the extra energy consumption caused by the nonreciprocal computation of the two-input and gate in the majority decision circuit a ：
W a =W AND1 +W XOR1 +W AND2 +W XOR2 （7）
Wherein W is AND1 、W XOR1 、W AND2 、W XOR2 The additional power consumption of AND1, XOR1, AND2, XOR2 in (a) of FIG. 1 due to the nonreciprocal computation can be represented by either equation (5) or equation (5), respectively. The probabilities of inputs x, y of AND1 AND XOR1 being 1 are respectivelyP x =p x 、P y =p y The inputs of AND2 are z AND the output of XOR1, the probabilities of z input being 1 are respectivelyp z ，p x 、p y 、p z After the input level is counted by the FPGACalculated, XOR1 is a two-input exclusive OR gate, and when the input is (0, 1) or (1, 0), the probability of the output being 1 isp x (1-p y )+p y (1-p x ) When the AND1 output is 1, the input is (1, 1), AND the probability of the AND1 output being 1 isp x p y The probabilities of the two inputs of AND2 inputting 1 are respectivelyP x =p x (1-p y )+p y (1-p x )、P y =p z The probability of an AND2 output of 1 isp z (p x (1-p y )+p y (1-p x ) The probability of the two inputs of XOR2 inputting 1 is respectivelyP x =p x p y 、P y =p z (p x (1-p y )+p y (1-p x )). The calculated error rates epsilon of all the two-input exclusive-OR gates AND the two-input AND gates in the majority decision circuit are the same, AND finally the energy consumption of the AND1, the XOR2 AND the AND2 can be calculated.
The total energy consumption of the majority decision circuit shown in fig. 1 (b) due to the non-reciprocal calculation can be expressed as the sum of all two-input exclusive-or gates and the additional energy consumption of the two-input and gate due to the non-reciprocal calculation in the majority decision circuit b ：
W b =W* AND1 +W* XOR1 +W* AND2 +W* XOR2 （8）
Wherein W is AND1 、W* XOR1 、W* AND2 、W* XOR2 The additional power consumption due to the nonreciprocal computation of AND1, XOR2, XOR3 in fig. 1 (b), respectively, can be represented by either equation (5) or equation (6). The input of XOR1 is x and y, and the probabilities of the two inputs being 1 are respectivelyP x =p x 、P y =p y The inputs of XOR2 are y and z, and the probabilities of the two inputs being 1 are respectivelyP x =p y 、P y =p z ，p x 、p y 、p z The input level is counted by the FPGA to obtain that the input of the AND1 is the output of the XOR1 AND the XOR2, AND the probability that the two inputs of the AND1 are 1 is respectivelyP x =p x (1-p y )+p y (1-p x )、P y =p y (1-p z )+p z (1-p y ) The inputs of XOR3 are the output of AND1 AND y, AND the probabilities of the two inputs being 1 are respectivelyP x =(p x (1-p y )+p y (1-p x ))(p y (1-p z )+p z (1-p y ))、P y =p y The calculated error rates epsilon of all the two-input exclusive-OR gates AND the two-input AND gates in the majority decision circuit are the same, AND finally the energy consumption of the AND1, the XOR2 AND the XOR3 can be calculated.
If W is a ≥W b Control signal selection structure b, if W a ≤W b The control signal selects structure a. The functions can be realized through the FPGA, the input logic signals comprise clock signals, reset signals, input data sequence signals and output signals comprise control signals.
Claims (2)
1. The energy consumption optimizing device for the majority decision circuit is characterized by comprising a decision module and a plurality of majority decision circuits with different structure types, wherein the plurality of the majority decision circuits with different structure types are connected in parallel, the majority decision circuits respond to at least three input logic signals and are used for generating a majority voting output signal, the decision module is used for calculating and comparing the extra total energy consumption caused by the non-reciprocal calculation of each of the plurality of the decision circuits according to the probability that each logic signal is at a high level, and enabling the majority decision circuit with the lowest extra total energy consumption to receive each logic signal and enabling the rest of the plurality of the decision circuits to pause receiving each logic signal;
the additional total energy consumption is the sum of additional energy consumption caused by the non-reciprocal calculation of all the two-input exclusive-OR gates and the two-input AND gates in each majority decision circuit;
the energy consumption caused by the non-reciprocity calculation of the exclusive or gate with two inputs is as follows:
(1-[ PxPy +(1- Px )(1- Py )] 2 -[(1- Px ) Py + Px (1- Py )] 2 )In(ε -1 )；
the energy consumption caused by each two-input AND gate nonreciprocal calculation is as follows:
(1-(1- PxPy ) 2 -( PxPy ) 2 )In(ε -1 )；
wherein the probability of logic signal received at one input of each two-input exclusive-OR gate or AND gate is high Px Representing the probability that the logic signal received at the other input terminal is high Py Indicating that the calculated error rate epsilon of all the two-input exclusive-or gates and the two-input AND gates in the majority decision circuit are the same;
when the input signals of each two-input exclusive-OR gate or two-input AND gate are logic signals responded by a majority decision circuit, the probability that the logic signals are high level is calculated by the FPGA after statistics of the input logic signals;
when the input signal received by the input end of each two-input exclusive-or gate or the two-input and gate is the output signal of the other two-input exclusive-or gate or the two-input and gate, the probability that the other two-input exclusive-or gate or the two-input and gate outputs a high level is calculated by the following formula:
the probability of the other two-input exclusive-OR gate outputting a high level is Px (1- Py )+ Py (1- Px ) The probability of the other two-input AND gate outputting high level is PxPy 。
2. A method of optimizing power consumption of a majority decision circuit comprising a plurality of different architecture types of the majority decision circuit of claim 1, comprising the steps of:
s1, collecting the probability that all logic signals input into various majority decision circuits are respectively high level;
s2, calculating and comparing the extra total energy consumption caused by the non-reciprocity calculation of each majority decision circuit;
s3, enabling the majority decision circuit with the lowest additional total energy consumption to receive each logic signal, and enabling the rest majority decision circuits to stop receiving each logic signal.
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