CN115955218A

CN115955218A - Stable on-chip clock generation circuit

Info

Publication number: CN115955218A
Application number: CN202211579695.4A
Authority: CN
Inventors: 李泽宏; 刘雨; 张一帆
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2022-12-09
Filing date: 2022-12-09
Publication date: 2023-04-11

Abstract

The invention belongs to the technical field of integrated circuits, and relates to a stable on-chip clock generation circuit. The invention comprises a charging and discharging circuit, a comparator and a sequential logic circuit. Four switches are used in the charging and discharging circuit to jointly control charging and discharging of the charging capacitor C1, and a triangular wave signal which rises linearly is generated. And a compensation capacitor C2 in the charging and discharging circuit is used for counteracting negative pressure mutation caused by capacitor turnover, so that the waveform and the frequency of the triangular wave at the charging node VC are effectively stabilized. The comparator compares the charging triangular wave signal VC with a reference voltage source VREF, and outputs a signal to be supplied to the sequential logic circuit. The sequential logic circuit is connected with the output of the comparator and is used for generating a first clock SW and a second clock SW _ B which are non-overlapped clock signals. The invention can realize the rapid discharge of the charge on the capacitor by exchanging the charge and discharge of the upper and lower polar plates of the capacitor C1 and combining the compensation capacitor C2, and has the advantages of stable output clock frequency, simple circuit structure and less power consumption.

Description

Stable on-chip clock generation circuit

Technical Field

The invention belongs to the technical field of integrated circuit design, and particularly relates to a stable on-chip clock generation circuit.

Background

The clock source is an important module of many electronic systems, for example, in a switching power supply, the switching-off and switching-on of a power tube are controlled by using a clock signal, so that energy is transferred in a chopping mode; analog to Digital Converters (ADCs) sample Analog signals using a clock signal, with the clock frequency determining the sampling frequency. Therefore, the quality of the clock source will directly affect the overall performance of the electronic system.

Referring to fig. 1, a schematic structural diagram of a conventional on-chip clock generation circuit is shown, and specifically includes two comparators COMP1 and COMP2, and a current source I _N And a current source I _P The circuit comprises two switches S1 and S2, a charging capacitor C and an RS trigger. The on-chip clock source shown in fig. 1 works in the following manner: the on and off of the switches S1 and S2 are controlled by the output signals CLK and CLK _ B of the RS flip-flop and by the current source I _N And a current source I _P The charging and discharging of the charging capacitor C are repeated.

The working process of a conventional on-chip clock generation circuit shown in fig. 1 is as follows:

when the output signal CLK of the RS trigger is at low level and the output signal CLK _ B is at high level, the switch S1 is turned on, the switch S2 is turned off, and the current source I is turned on _P The capacitor C is charged, when the voltage VC on the capacitor C rises and exceeds the reference voltage VH of the inverting terminal of the comparator COMP1, the output signal of the comparator COMP1 is at a high level, the RS trigger is in a set state, the output signal CLK is changed into a high level, and the output signal CLK _ B is changed into a low level. At this time, the switch S1 is turned off, the switch S2 is turned on, and the current source I _N Discharging the capacitor C, enabling the potential VC on the capacitor to start to fall, enabling the comparator COMP2 to output a high level when the potential VC falls to a reference voltage VL connected with the same-phase end of the comparator COMP2, enabling the RS trigger to be in a reset state, enabling the output signal CLK to be changed into a low level, enabling the CLK _ B to be changed into a high level, enabling the circuit to continuously repeat the above process, and enabling the voltage VC on the capacitor C to repeatedly oscillate back and forth between VH and VL.

Two major problems with a conventional on-chip clock generation circuit as shown in fig. 1 are: firstly, the double comparators are structurally adopted, so that large power consumption loss is brought; the mismatch between the two comparators adversely affects the clock frequency stability. Conventional on-chip clock generation circuits therefore have room for continued progress and optimization in power consumption and frequency stability.

Disclosure of Invention

In view of the above problems of the on-chip clock generating circuit, the present invention is directed to provide a stable on-chip clock generating circuit.

In order to solve the above purpose, the invention adopts the following technical scheme:

a stable on-chip clock generation circuit comprises a charge and discharge circuit, a comparator and a sequential logic circuit, wherein:

the charging and discharging circuit receives a first clock SW and a second clock SW _ B from the sequential logic circuit, controls a reference current source Iref to repeatedly charge the left and right polar plates of a charging capacitor C1 according to a feedback clock signal, and generates a stable triangular wave signal VC;

the comparator compares a triangular wave signal VC generated by the charge-discharge circuit with a reference voltage source VREF, and outputs a comparison signal VO;

the sequential logic circuit receives the comparator output signal VO and generates non-overlapping first and second clocks SW and SW _ B.

Specifically, the charging/discharging circuit includes a reference current source Iref, a charging capacitor C1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a compensation capacitor C2, wherein,

one end of the charging current source Iref is connected with the compensation capacitor C2, the first switch S1 and the second switch S2, and the other end is connected with the power supply VDD;

one end of the compensation capacitor C2 is connected with one end of the first switch S1 and one end of the second switch S2, one end of the compensation capacitor C is grounded, and the other ends of the first switch S1 and the second switch S2 are respectively connected with the left port and the right port of the charging capacitor C1;

the left end of the charging capacitor C1 is also connected with a third switch S3, the right end of the charging capacitor C1 is also connected with a fourth switch S4, and the other ends of the third switch S3 and the fourth switch S4 are grounded together;

the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are all composed of an NMOS transistor and two PMOS transistors, taking the first switch S1 as an example, wherein,

the source electrodes and the drain electrodes of the PM1_ A and the PM1_ B are in short circuit, the drain electrode of the PM1_ A is also connected with the drain electrode of the NMOS tube NM1, the source electrode of the PM1_ B is also connected with the source electrode of the NMOS tube, the grid electrodes of the PM1_ A, the PM1_ B and the NM1 are connected, the PM1_ A and the PM1_ B are identical in size, and the width-to-length ratio is half of the NM 1;

the second switch S2, the third switch S3, and the fourth switch S4 have the same structure as the first switch S1, and are not described herein again;

the first switch S1 and the fourth switch S4 are controlled by a first clock SW, and the second switch S2 and the third switch S3 are controlled by a second clock SW _ B;

the non-inverting port of the comparator is connected with one end of a reference voltage source VREF, the inverting port of the comparator is connected with a compensation capacitor C2, a first switch S1 and a second switch S2, the output of the comparator is connected with the input of a first inverter, and the other end of the reference voltage source VREF is grounded;

the sequential logic circuit comprises a D flip-flop, two AND gates and six inverters, wherein the input of the first inverter is connected with the output VO of the comparator, the output of the first inverter is connected with the clock clk port of the D flip-flop, and the D end of the D flip-flop is connected with the output of the D flip-flop

The Q end is connected with the input of a second inverter and the input of a first AND gate, the other input of the first AND gate is connected with the output of a fourth inverter, one input of the second AND gate is connected with the output of the second inverter, the other input of the second AND gate is connected with the output of a third inverter, the input of the third inverter is connected with the output of the first AND gate, the input of the fourth inverter is connected with the output of the second AND gate, the input of the fifth inverter is connected with the output of the third inverter, the output of the fifth inverter is a first clock SW, the input of the sixth inverter is connected with the output of the fourth inverter, and the output of the sixth inverter is a second clock SW _ B;

compared with the prior art, the invention has the following advantages:

the on-chip clock generation circuit structure only uses a single comparator, so that the power consumption is effectively reduced; the cyclic charging of the left and right polar plates of the charging capacitor C1 by the reference current source and the instant discharging of the capacitor are realized by the switch, the negative pressure sudden change caused by the instant discharging of the capacitor is counteracted by the compensation capacitor C2, the low potential of the VC triangular wave signal of the charging node is always stabilized to be 0, and the frequency stability of the signal is enhanced.

Drawings

FIG. 1 is a conventional on-chip clock generation circuit

FIG. 2 is a circuit diagram of an on-chip clock generating circuit according to the present invention

FIG. 3 is a diagram of the operation of the on-chip clock generation circuit of the present invention

FIG. 4 is a diagram showing simulation results of the on-chip clock generation circuit of the present invention

Detailed Description

The invention is explained in further detail below with reference to the drawings.

Example one

As shown in fig. 2, a stable on-chip generation circuit of the present invention comprises a charge/discharge circuit, a comparator and a sequential logic circuit, wherein,

the charging and discharging circuit receives a first clock SW and a second clock SW _ B from the sequential logic circuit, and controls a reference current source Iref to repeatedly charge a charging capacitor C1 according to a clock signal to generate a stable triangular wave signal VC;

the comparator compares a triangular wave signal VC generated by the charge and discharge circuit with a reference voltage VREF and outputs a comparison signal VO;

the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are all composed of an NMOS transistor and two PMOS transistors, taking the first switch S1 as an example, wherein:

the source electrodes and the drain electrodes of the PM1_ A and the PM1_ B are short-circuited, the drain electrode of the PM1_ A is also connected with the drain electrode of the NMOS tube NM1, the source electrode of the PM1_ B is also connected with the source electrode of the NMOS tube, the grid electrodes of the PM1_ A, the PM1_ B and the NM1 are connected, the size of the PM1_ A is the same as that of the PM1_ B, the width-to-length ratio of the PM1_ A to the PM1_ B is half of that of the NM1, and the influence of clock feed-through and charge injection can be effectively avoided;

the non-inverting port of the comparator is connected with one end of a reference voltage source VREF, the inverting end of the comparator is connected with one end of a compensation capacitor C2 and one ends of a first switch S1 and a second switch S2, the output VO of the comparator is connected with the input of a first inverter in the sequential logic circuit, and the other end of the reference voltage source VREF is grounded;

the sequential logic circuit comprises a D trigger, two AND gates and six inverters, wherein the input of the first inverter is connected with the output VO of the comparator, the output of the first inverter is connected with the clock clk port of the D trigger, and the D end of the D trigger is connected with the output of the D trigger

The Q end is connected with the input of a second inverter and the input of a first AND gate, the other input of the first AND gate is connected with the output of a fourth inverter, one input of the second AND gate is connected with the output of the second inverter, the other input of the second AND gate is connected with the output of a third inverter, the input of the third inverter is connected with the output of the first AND gate, the input of the fourth inverter is connected with the output of the second AND gate, the input of the fifth inverter is connected with the output of the third inverter, a first clock SW is output, the input of the sixth inverter is connected with the output of the fourth inverter, and a second clock SW _ B is output;

the working principle of the invention is as follows:

in the charge and discharge circuit, a first switch S1 and a fourth switch S4 are controlled by a first clock signal SW, a second switch S2 and a third switch S3 are controlled by a second clock SW _ B, and the first clock SW and the second clock SW _ B are two-phase non-overlapping clocks, namely, the first clock SW and the second clock SW _ B cannot be high at the same time.

The charging capacitor C1 and the compensation capacitor C2 are preset to have no charge, and the voltage of the node VC is 0. The comparator outputs a comparison signal VO at a high level, and after the comparison signal VO is processed by the sequential logic circuit, the first clock SW is at a high level and the second clock SW _ B is at a low level. The first switch S1 and the fourth switch S4 are in a conducting state, the second switch S2 and the third switch S3 are in a disconnecting state, the left plate end VL of the charging capacitor C1 and the compensation capacitor C2 are connected with the reference current source Iref together, and the right plate of the charging capacitor C1 is grounded. The reference current source Iref starts to linearly charge the charging capacitor C1 and the compensation capacitor C2 to generate a triangular wave signal VC, and the voltage of the charging process meets the relation:

V＝(Iref×t)/(C1+C2)

when the charging node voltage VC is greater than the reference voltage source VREF, the comparator outputs the comparison signal VO to a low level, and after the comparison signal VO is processed by the sequential logic circuit, the first clock SW becomes a low level, and the second clock SW _ B becomes a high level. At the moment, the first switch S1 and the fourth switch S4 are switched off, the second switch S2 and the third switch S3 are switched on, the upper polar plate VL of the charging capacitor C1 is instantaneously switched to be grounded, and the lower polar plate VR of the charging capacitor is instantaneously switched to be connected with the charging current source Iref.

The difference in capacitance cannot be abrupt, so the difference between VL and VR is still about VREF, while VL =0, so VR = -VREF. Due to the existence of the compensation capacitor C2, the charge amount on the compensation capacitor C2 is Qp = C2 × Vref, the negative charge Qn = -C1 × Vref on the charging capacitor C1 can be neutralized by reasonably setting the proportion of the capacitors C1 and C2, so that the total charge amount on the charging capacitor C1 and the compensation capacitor C2 is 0, the comparator output VO is restored to a high level, the charging current source Iref charges the capacitors again, and a triangular wave signal is generated.

When the charging node voltage VC is again greater than VREF, the comparator output VO changes to a low level, and after the sequential logic signal processing, the first clock SW changes to a high level and the second clock SW _ B changes to a low level. Finally, the circuit can realize repeated charging and discharging of the capacitor and generate a clock signal with stable frequency.

Example two

Referring to fig. 3, a schematic diagram of an operation process of the on-chip clock generation circuit shown in fig. 2 is shown, and the operation process of the on-chip clock generation circuit is specifically as follows:

after the clock generating circuit is powered on, at the time of t0, the initial voltage of a charging node VC is 0, the left plate voltage VL of a charging capacitor C1 is 0, the right plate voltage VR is 0, the output signal VO of the comparator is high level, the first clock SW is high level, the second clock SW _ B is low level, the first switch S1 and the fourth switch S4 are conducted, the second switch S2 and the third switch S3 are disconnected, the left plate of the charging capacitor C1 is connected with a reference current source Iref to start charging, the potential VL of the left plate is the same as the potential of the charging node VC, the rising is started by the slope of Iref/(C1 + C2), a triangular wave signal is generated, the right plate of a compensating capacitor C2 is grounded, and the VR voltage is always 0.

At time t1, when the charge node potential VC rises to the reference voltage VREF, the output signal VO goes low at time t2 after the comparator delay time td. The first clock SW is also changed to a low level, the second clock SW _ B is changed to a high level, the first switch S1 and the fourth switch S4 are turned off, and the second switch S2 and the third switch S3 are turned on. The charge on the left polar plate VL of the charging capacitor C1 is discharged instantly, the voltage VL becomes 0, the right polar plate VR of the charging capacitor C1 is connected with the VC node due to the existence of the compensation capacitor C2, and the potential is stabilized to 0. After the comparator passes the delay time td, the output becomes high again at time t 3. The charging current source Iref charges the capacitor again, and the right plate VR of the charging capacitor C1 is the same as the charging node VC, so as to continue to charge with the slope Iref/(C1 + C2). Until the time t4, the potential of VC is greater than VREF, the comparator outputs VO at the time t5 and becomes low level, the first clock SW subsequently becomes high level, the second clock SW _ B becomes low level, the charge on the right plate VR of the charging capacitor C1 is discharged instantly, the voltage of VR becomes 0, due to the existence of the compensation capacitor C2, the left plate VL of the charging capacitor C1 is connected with the node VC again, the potential is stabilized to 0, and the comparator outputs VO at the time t6 and becomes high again after the delay time of td. The reference current source Iref charges the capacitor again, and the voltage of the node VC starts to rise linearly, so that one cycle is completed.

One cycle of the clock signal SW includes a linear charging time T1 during which the charging node VC rises from the zero potential to the VREF voltage and a delay time Td of the comparator. The linear charging time T1 can be obtained according to the charge conservation principle by the following expression:

the output frequency of the clock signal is therefore:

FIG. 4 is a simulation diagram of an actual circuit of the clock generating circuit of the present invention, wherein the frequency of the first clock signal SW is 800KHz, the left and right plates VR and VL of the charging capacitor C1 are sequentially charged in one cycle to generate a triangular wave signal, and after VC is greater than VREF, the charge is instantly discharged to the ground, and no transient negative voltage jump occurs due to the existence of the compensation capacitor C2, and the simulation shows that the initial voltage on the capacitor is 19nV at each recharging, which is in accordance with the theoretical expectation.

In summary, the on-chip clock generation circuit has the following advantages:

firstly, the on-chip clock generation circuit only uses a single comparator, and compared with the traditional double-comparator structure, the on-chip clock generation circuit not only reduces the power consumption, but also eliminates the adverse effect of double-comparator mismatch on the frequency stability;

secondly, the on-chip clock generation circuit adopts a structure of an overturning capacitor to sequentially charge the left and right polar plates of the charging capacitor C1 to generate a triangular wave signal, and inhibits transient negative voltage caused by overturning of the capacitor polar plates by adding the compensating capacitor C2, so that in each charging period, the charging nodes are linearly increased from 0 potential, and the frequency stability of the clock signal is enhanced;

in addition, the on-chip clock generation circuit effectively inhibits the adverse effects of charge injection and clock feed-through effect on signal frequency by adding two PMOS tubes in the switch structure.

Finally, the first clock SW and the second clock SW _ B generated by the on-chip clock generating circuit are two-phase non-overlapping clocks, so that four switches are prevented from being simultaneously switched on when the capacitor discharges, and surge current is generated.

The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can make various insubstantial modifications within the technical scope of the present invention, or without any modification, and the above idea and technical solution of the present invention can be directly applied to other occasions, and shall be included in the scope of the present invention.

Claims

1. A stable on-chip clock generation circuit, comprising a charging/discharging circuit (100), a comparator (200) and a sequential logic circuit (300), wherein:

the charging and discharging circuit (100) receives a first clock SW and a second clock SW _ B fed back by the sequential logic circuit (300) and generates a charging triangular wave signal VC;

the reverse phase end of the comparator (200) is connected with a triangular wave signal VC output by the charging and discharging circuit (100), the in-phase end is connected with a reference voltage source VREF, and a comparison signal VO is output to the sequential logic circuit (300);

the sequential logic circuit (300) receives the output signal VO of the comparator (200), outputs a first clock SW and a second clock SW _ B, and feeds back the output signal VO to the charging and discharging circuit (100).

2. The stable on-chip clock generation circuit of claim 1, wherein the charging and discharging circuit (100) comprises a reference current source Iref, a charging capacitor C1, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4 and a compensation capacitor C2, wherein:

the left polar plate of the charging capacitor C1 is connected with the second port of the first switch S1 and the first port of the third switch S3, and the right polar plate is connected with the second port of the second switch S2 and the first port of the fourth switch S4;

the first switch S1 and the fourth switch S4 are controlled by a first clock SW, the second switch S2 and the fourth switch S3 are controlled by a second clock SW _ B, and the polar plate of the charging capacitor C1 is determined to be in a grounding state or a charging state according to a clock signal;

the reference current source Iref outputs a stable triangular wave signal VC by linearly charging the capacitor.

3. A stable on-chip clock generation circuit according to claim 1 or 2, wherein the sequential logic circuit comprises a D flip-flop (301), a first inverter (302), a second inverter (303), a first and gate (304), a second and gate (305), a third inverter (306), a fourth inverter (307), a fifth inverter (308), and a sixth inverter (309), wherein:

the first inverter (302) is connected with the output VO of the comparator (200), and the output is connected with the D flip-flop (301);

the D end of the D trigger (301) is connected with

The Q end is connected with the second inverter (303) and the first AND gate (304);

the output of the second inverter (303) is connected with the input of a second AND gate (305);

the first output of the first AND gate (304) is connected with the output Q of the D flip-flop (301), the second input is connected with the output of the fourth inverter (307), and the output of the first AND gate (304) is connected with the input of the third inverter (306);

the first input of the second AND gate (305) is connected with the output of the second inverter (303), the second input is connected with the output of the third inverter (306), and the output of the second AND gate (305) is connected with the input of the fourth inverter (307);

the input of the fifth inverter (308) is connected with the output of the third inverter (306), and the output first clock SW is connected with the control ends of the first switch S1 (101) and the fourth switch S4 (104);

the input of the sixth inverter (309) is connected with the output of the fourth inverter (307), and the output second clock SW _ B is connected with the control ends of the second switch S2 (102) and the third switch S3 (103).

4. A stable on-chip clock generating circuit according to claim 1 or 2, wherein the first switch S1 comprises NM1, PM1_ a and PM1_ B, where the width-to-length ratio of PM1_ a and PM1_ B is 1/2 of NM1, and the source and drain are shorted, so as to eliminate the adverse effects caused by charge injection and clock feed-through, and the second switch S2, the third switch S3 and the fourth switch S4 have the same structure as the first switch S1.

5. The stable on-chip clock generating circuit of claim 1 or 2, wherein the upper end of the compensation capacitor C2 is connected to the charging node of the reference current source Iref, and the lower end is grounded, so as to suppress the sudden change of negative voltage caused by the inversion of the charging capacitor C1, and stabilize the triangular wave signal VC.

6. The stable on-chip clock generating circuit of claim 1 or 2, wherein the generated first clock SW and second clock SW _ B are two-phase non-overlapped clocks, i.e. they cannot be high simultaneously, so as to avoid surge current generated by the simultaneous conduction of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4.