CN115955201A - Power amplifier and mobile terminal - Google Patents
Power amplifier and mobile terminal Download PDFInfo
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- CN115955201A CN115955201A CN202211718282.XA CN202211718282A CN115955201A CN 115955201 A CN115955201 A CN 115955201A CN 202211718282 A CN202211718282 A CN 202211718282A CN 115955201 A CN115955201 A CN 115955201A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The embodiment of the application provides a power amplifier and a mobile terminal, wherein the power amplifier comprises: a bias circuit and an amplification circuit; the amplifying circuit comprises a first transistor and a shunt circuit; the bias circuit is used for providing bias current for the amplifying circuit; the amplifying circuit is used for amplifying the input radio frequency signal and outputting the amplified radio frequency signal; the grid electrode of the first transistor is connected with the bias circuit, the source electrode of the first transistor is grounded, and the drain electrode of the first transistor is connected with the power supply; the input end of the shunt circuit is connected with the grid electrode of the first transistor; and the output end of the shunt circuit is used for exporting the first bias current output by the bias circuit so as to drive the first transistor by using the first bias current.
Description
Technical Field
The present application relates to the field of power amplifier technology, and in particular, to a power amplifier and a mobile terminal.
Background
In order to increase data transmission rate, a radio frequency Power Amplifier (PA) is widely used in a mobile communication device of Second Generation mobile communication (2G)/Third Generation mobile communication (3G)/Fourth Generation mobile communication (4G)/Fifth Generation mobile communication (5G), and 3G/4G/5G communication adopts a high-order Modulation method, such as Quadrature Phase Shift Keying (QPSK), quadrature Amplitude Modulation (QAM), and the like, and an output signal thereof is a non-constant envelope signal, so that a linear PA is required to reduce signal distortion.
The rf power amplifier usually uses a compound semiconductor process such as GaAs HBT, which has the advantages of high efficiency and high linearity, but is expensive. If a channel field effect transistor (NFET) in a low-cost CMOS (Complementary Metal-Oxide-Semiconductor) process is used, the linearity of the NFET is low under large signals and the NFET is difficult to be designed as a high-power and high-linearity power amplifier, so that the designed power amplifier shows low linearity under high power.
Disclosure of Invention
In view of the above, embodiments of the present application are directed to providing a power amplifier and a mobile terminal, which can improve the linearity of a CMOS power amplifier and reduce the cost of the mobile terminal.
In order to achieve the purpose, the technical scheme of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a power amplifier, including: a bias circuit and an amplification circuit; the amplifying circuit includes: a first transistor and a shunt circuit;
the bias circuit is used for providing bias current for the amplifying circuit;
the amplifying circuit is used for amplifying the input radio frequency signal and outputting the amplified radio frequency signal;
the grid electrode of the first transistor is connected with the bias circuit, the source electrode of the first transistor is grounded, and the drain electrode of the first transistor is connected with the power supply;
the input end of the shunt circuit is connected with the grid electrode of the first transistor, and the output end of the shunt circuit is used for leading out the first bias current output by the bias circuit so as to drive the first transistor by using the first bias current.
In the above power amplifier, the shunt circuit includes: a second transistor;
the grid electrode of the second transistor and the drain electrode of the second transistor are respectively connected with the grid electrode of the first transistor; and the source electrode of the second transistor is used for leading out the bias current output by the bias circuit.
In the above power amplifier, the shunt circuit includes: a diode;
the anode of the diode is connected with the grid of the first transistor; and the cathode of the diode is used for leading out the bias current output by the bias circuit.
In the above power amplifier, the shunt circuit includes: a first resistor;
one end of the first resistor is connected with the grid electrode of the first transistor; the other end of the first resistor is used for leading out the bias current output by the bias circuit.
In the above power amplifier, the output terminal of the shunt circuit is grounded.
In the above power amplifier, the bias circuit includes a third transistor and a first capacitor;
the grid electrode of the third transistor is connected with one end of the first capacitor, and the other end of the first capacitor is grounded; the source electrode of the third transistor is connected with the grid electrode of the first transistor; the drain electrode of the third transistor is connected with a power supply;
a third transistor for supplying a bias current to a gate of the first transistor;
and the first capacitor is used for guiding the radio-frequency signal transmitted in a path where the drain electrode of the third transistor and the grid electrode of the third transistor are located into the ground.
In the above power amplifier, the bias circuit further includes a fourth transistor and a fifth transistor;
the grid electrode of the fourth transistor is connected with the grid electrode of the third transistor; the drain electrode of the fourth transistor is respectively connected with the grid electrode of the third transistor and the direct current power supply; the source electrode of the fourth transistor is connected with the grid electrode of the fifth transistor and the drain electrode of the fifth transistor; the source of the fifth transistor is grounded.
In the above power amplifier, the bias circuit further includes a second resistor;
one end of the second resistor is connected with the grid electrode of the first transistor; the other end of the second resistor is connected with the source electrode of the third transistor;
when the current transmitted by the grid electrode of the first transistor changes along with the temperature of the first transistor, the current is adjusted by the second resistor so as to adjust the bias voltage of the first transistor.
In the above power amplifier, the bias circuit further includes a third resistor;
one end of the third resistor is connected with the drain electrode of the fourth transistor; the other end of the third resistor is connected with the grid electrode of the third transistor;
the leaked radio frequency signal is isolated from the power supply by a third resistor.
In the above power amplifier, the power amplifier is a CMOS power amplifier.
In a second aspect, an embodiment of the present application provides a mobile terminal, which includes the power amplifier according to any one of claims 1 to 10.
The embodiment of the application provides a power amplifier and a mobile terminal, wherein the power amplifier comprises: a bias circuit and an amplification circuit; the amplifying circuit includes: a first transistor and a shunt circuit; the bias circuit is used for providing bias current for the amplifying circuit; the amplifying circuit is used for amplifying the input radio frequency signal and outputting the amplified radio frequency signal; the grid electrode of the first transistor is connected with the output end of the bias circuit, the source electrode of the first transistor is grounded, and the drain electrode of the first transistor is connected with the power supply; the input end of the shunt circuit is connected with the grid electrode of the first transistor; and the output end of the shunt circuit is used for leading out the first bias current output by the bias circuit so as to drive the first transistor by using the first bias current. By adopting the implementation scheme, in the process of amplifying the power of the input radio-frequency signal, the existing CMOS power amplifier is improved, the bias current output in the bias circuit of the CMOS power amplifier is increased along with the increase of the power of the radio-frequency signal, so that the bias voltage influencing the input end of the amplifying circuit is also increased along with the increase of the bias current output in the bias circuit, and the linearity of a transistor for amplifying the radio-frequency signal in the amplifying circuit is improved by utilizing the changed bias voltage.
Drawings
FIG. 1 is a diagram illustrating a CMOS power amplifier according to the prior art;
fig. 2 is a first schematic circuit diagram of a power amplifier according to an embodiment of the present disclosure;
fig. 3 is a first schematic structural diagram of an amplifying circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic diagram of an amplifying circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a circuit structure of a power amplifier according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a circuit structure of a power amplifier according to an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a circuit structure of a power amplifier according to an embodiment of the present disclosure;
fig. 8 is a schematic diagram of a circuit structure of a power amplifier according to an embodiment of the present disclosure;
fig. 9 is a sixth schematic diagram of a circuit structure of a power amplifier according to an embodiment of the present disclosure;
fig. 10 is a seventh schematic diagram of a circuit structure of a power amplifier according to an embodiment of the present disclosure;
fig. 11 is a schematic diagram eight illustrating a circuit structure of a power amplifier according to an embodiment of the present application;
fig. 12 is a schematic diagram of the DC-IV characteristic of the improved current-controlled power amplifier circuit;
figure 13 is a graph illustrating a comparison of power gain curves for a CMOS prior art power amplifier, a HBT prior art power amplifier, and an improved power amplifier of the present application.
Detailed Description
So that the manner in which the features and elements of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the application.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict. It should also be noted that reference to the terms "first/second/third" in the embodiments of the present application is only used for distinguishing similar objects and does not denote any particular order or importance to the objects, and it should be understood that "first/second/third" may be interchanged with a particular order or sequence where permissible to enable the embodiments of the present application described herein to be practiced in an order other than that shown or described herein.
In the prior art, a structure of a conventional CMOS power amplifier is generally shown in fig. 1, in which a transistor M0 for signal amplification and a transistor M1 in a bias circuit structure form a current mirror circuit to implement a dc bias function, and the bias circuit structure in a dotted line provides a bias voltage for the amplifying transistor M0. The CMOS power amplifier in the prior art has the disadvantage that the bias circuit in the dashed line box provides a fixed bias voltage for the transistor M0, and the transistor M0 for amplifying the radio frequency signal is biased at a fixed gate voltage, which has a poor linearity at high power.
Therefore, the CMOS power amplifier is difficult to be designed as a high-power and high-linearity power amplifier due to low linearity of a large signal, and thus is less used as a linear power amplifier PA in a radio frequency signal power amplifier, and is mainly used as a saturation power amplifier PA, for example, a mobile terminal amplifier in 2G GSM communication has been widely implemented by using a CMOS process. Since the CMOS process has a significant advantage of low cost, if the CMOS power amplifier can be used in a linear PA by improving the design of the circuit structure, the cost of the termination PA can be greatly reduced.
To solve the technical problem in the prior art, an embodiment of the present application provides a power amplifier 1, as shown in fig. 2, where the power amplifier 1 includes: a bias circuit 10 and an amplification circuit 11; the amplifier circuit 11 includes: a first transistor M1 and a shunt circuit. The bias circuit 10 is used for providing bias current for the amplifying circuit 11; the amplifying circuit 11 is configured to amplify an input radio frequency signal and output the amplified radio frequency signal. Specifically, the gate of the first transistor M1 is connected to the bias circuit, the source of the first transistor M1 is grounded, and the drain of the first transistor M1 is connected to the power supply; the input end of the shunt circuit is connected to the gate of the first transistor M1, and the output end of the shunt circuit is used for leading out the bias current output by the bias circuit 10 to drive the first transistor M1 by using the bias current.
In the embodiment of the application, an improved CMOS power amplifier is provided, which is based on the advantages of the HBT power amplifier circuit, and can adjust the gain of the power amplifier by adjusting the bias current, so that the gain of the amplifier can be increased with the increase of power, thereby improving the linearity of the CMOS power amplifier.
Based on this, in the embodiment of the present application, ids generated in the bias circuit structure of the transistor is discharged through the shunt circuit, so that the transistor in the CMOS process can be driven by the bias current.
In the embodiment of the present application, the power amplifier is a CMOS power amplifier, and all transistors used in the circuit structure are CMOS transistors. In other embodiments, the transistors in the bias circuit may also be HBT transistors.
In the embodiment of the present application, when the transistor is a CMOS transistor, the input terminal of the CMOS transistor is a gate, the output terminal is a drain, and the ground terminal is a source.
In the embodiment of the present application, the structure of the power amplifier 1 is as shown in fig. 2, wherein the first transistor M1 is a CMOS transistor, and three terminals of the first transistor M1 are a gate g, a drain d, and a source s, respectively. The power amplifier 1 includes a bias circuit 10 in addition to a transistor M1 for amplifying an input radio frequency signal and outputting the amplified radio frequency signal, and a shunt circuit for introducing Ids supplied to a gate of the first transistor M1 by the bias circuit 10 to ground.
In the embodiment of the present application, the gate of the first transistor M1 is connected to the bias circuit 10, the source of the first transistor M1 is grounded, and the drain of the first transistor M1 is connected to the power supply.
In the embodiment of the present application, since the first transistor M1 needs to be driven by a voltage, in order to achieve the purpose of improving the linearity of the first transistor M1 by using a bias current provided by the bias circuit 10, a voltage-controlled CMOS transistor can be modified into an equivalent current-controlled device by connecting a shunt circuit in parallel to the transistor M1 in the CMOS power amplifier in the prior art, as shown in fig. 3, the transistor M1 and the shunt circuit form a modified current-controlled amplifying circuit, i.e., a modified amplifying circuit 11, and the circuit structure of the amplifying circuit 11 is shown in fig. 3.
In the embodiment of the present application, as shown in fig. 3, the amplifying circuit 11 includes a CMOS transistor M1 and a shunt circuit, M1 is connected in parallel with the shunt circuit, and the circuit connection mode is that the gate of M1 is connected to the input terminal of the shunt circuit, the source of M1 is grounded, the drain of M1 is connected to the power supply, the output terminal of the shunt circuit is used to lead out the bias current output by the bias circuit 10, and the CMOS transistor M1 is driven by the bias current.
It should be noted that, the shunt circuit in the amplifying circuit is used to derive the bias current Ids output by the bias circuit to the gate of M1 through the output terminal of the shunt circuit, so that the bias voltage provided by the bias circuit 10 is input to the gate of M1, the linearity of M1 is adjusted by using the bias voltage, and the input bias voltage changes with the power change of the input large signal, and the linearity of M1 is adjusted by using the variable bias voltage.
It should be noted that VB provides a voltage for the bias circuit 10, which needs to keep the bias circuit 10 in a saturation region, so that Ids of the bias circuit 10 changes linearly with the change of the voltage, and the amplifier is further made to be more linear.
Optionally, the shunt circuit comprises a second transistor; the grid electrode of the second transistor and the drain electrode of the second transistor are respectively connected with the grid electrode of the first transistor; and the source electrode of the second transistor is used for leading out the bias current output by the bias circuit.
In the embodiment of the present application, the shunting circuit in the amplifying circuit 11 may include a second transistor M2, as shown in fig. 4, a gate of the second transistor M2 and a drain of the second transistor M2 are respectively connected to a gate of the first transistor M1, and a source of the second transistor M2 is used for leading out the bias current provided by the bias circuit 10.
In the embodiment of the present application, the bias circuit 10 provides a bias voltage to the gate of the first transistor M1, and when the input power gradually increases, the bias current provided by the bias circuit gradually increases, which results in an increase in the bias voltage output to the gate of the first transistor M1, and the linearity of the first transistor is improved by using the changed bias voltage.
It should be noted that the implementation principle is described in the implementation process, and specifically, the implementation process may be referred to, and is not described herein again.
Optionally, the shunt circuit comprises a diode; the anode of the diode is connected with the grid of the first transistor; and the cathode of the diode is used for leading out the bias current output by the bias circuit.
In the embodiment of the present application, the shunt circuit may be a diode, an anode of the diode is connected to the gate of the first transistor M1, and a cathode of the diode is used to conduct the bias current provided by the bias circuit 10.
The cathode of the diode may be grounded or may be connected to another circuit element.
It should be noted that, for the specific implementation principle, reference may be made to the above embodiments, and details are not described herein.
Optionally, the shunt current comprises a first resistance; one end of the first resistor is connected with the grid electrode of the first transistor; the other end of the first resistor is used for leading out the bias current output by the bias circuit.
In the embodiment of the present application, the shunt circuit may be a resistor, one end of the resistor is connected to the gate of the first transistor M1, and the other end of the resistor is used to derive the bias current provided by the bias circuit 10.
The other end of the resistor may be grounded or may be connected to another circuit element.
It should be noted that, for the specific implementation principle, reference may be made to the above embodiments, and details are not described herein.
In the embodiment of the present application, in addition to the transistor, the resistor, and the diode included in the electronic component in the shunt circuit, other electronic components that can conduct a direct current all belong to the protection scope of the present application, and specifically, may be selected according to actual situations, and are not specifically limited in the present application.
Optionally, the output of the shunt circuit is grounded.
In the embodiment of the application, the output end of the shunt circuit is grounded, and the bias current output from the bias circuit is led out in a grounded connection mode.
It should be noted that the output end of the shunt circuit may also be connected to other electronic circuits, and only the bias current output from the bias circuit 10 needs to be led out, specifically, the output end may be selected according to actual situations, and the application is not limited specifically.
Optionally, the bias circuit comprises a third transistor and a first capacitance; the grid electrode of the third transistor is connected with one end of the first capacitor, and the other end of the first capacitor is grounded; the source electrode of the third transistor is connected with the grid electrode of the first transistor; the drain electrode of the third transistor is connected with a power supply; a third transistor for supplying a bias current to a gate of the first transistor; and the first capacitor is used for guiding the radio-frequency signal transmitted in a path where the drain electrode of the third transistor and the grid electrode of the third transistor are located into the ground.
In the embodiment of the application, the bias mode of the CMOS power amplifier is improved, and the large-signal gain characteristic similar to an HBT circuit is realized.
In the embodiment of the present application, the gate of the first transistor M1 is connected to the source of the third transistor M3, the gate of the second transistor M2, and the drain of the second transistor M2, respectively; the source electrode of the first transistor M1 and the source electrode of the second transistor M2 are respectively grounded; the drain electrode of the first transistor M1 is connected with a direct current power supply VDD; the grid electrode of the third transistor is connected with one end of the first capacitor C1; the drain electrode of the third transistor is connected with a power supply VB; the other end of the first capacitor C1 is grounded.
In the embodiment of the present application, since the first transistor M1 needs to be driven by a voltage, in order to achieve the purpose of improving the linearity of M1 by using a bias voltage provided by M3, a voltage-controlled CMOS transistor can be modified into an equivalent current-controlled device by connecting a diode-connected CMOS transistor in parallel to the transistor M1 in a CMOS power amplifier in the prior art, and exemplarily, as shown in fig. 4, the transistors M1 and M2 constitute a modified current-controlled amplifying circuit.
In the embodiment of the present application, as shown in fig. 4, the transistor amplifier circuit 11 includes a CMOS transistor M1 and a CMOS transistor M2, the transistor M1 is connected in parallel with a diode-connected transistor M2, the circuit connection is that the gate of the transistor M1 is connected to the gate and the drain of the transistor M2, the source of the transistor M1 is grounded, the drain of the transistor M1 is connected to the power supply, and the source of the transistor M2 is grounded.
M2 in the transistor amplifier circuit introduces the bias current Ids for outputting M3 to the gate of M1 to the ground through the gate of M2, so that the bias voltage provided by M3 is input to the gate of M1, M1 is driven by the bias voltage, the input bias voltage is variable with the change of the power of the input large signal, and the linearity of M1 is adjusted by the variable bias voltage.
In the embodiment of the present application, the structure of the power amplifier 1 is as shown in fig. 5, and includes a bias circuit 10 in addition to the transistor M1 and the transistor M2, where the bias circuit 10 includes a CMOS transistor M3 and a first capacitor C1. The CMOS transistor M3 is connected by using a source follower connection mode, the source electrode of the M3 is connected with the grid electrode of the M1, the drain electrode of the M3 is connected with a power supply VB, and the grid electrode of the M3 is grounded; one end of the first capacitor C1 is connected to the gate of M3, and the other end of C3 is grounded.
It should be noted that VB provides a voltage for the drain of M3, which needs to keep M3 in the saturation region, so that Ids of M3 varies linearly with the gate, and the amplifier is more linear.
It should be noted that the transistor M3 is a source follower connection type, and is used for providing a bias current to M1, as the power of the rf signal inputted by the signal becomes higher, ids of M3 increases accordingly, and correspondingly, the voltage of the gate of M1 also increases accordingly, thereby improving the linearity of the power amplifier.
In addition, ids represents the drain-to-source current of M3.
In the embodiment of the application, C3 is a linearization capacitor, which can reduce the impedance of the gate of M3, reduce the rf swing of the gate voltage VG2 of M3, make the amplitude of the rf signal mainly on the voltage VGs of the gate of M3 relative to the source, and increase the current flowing through M3 due to the nonlinear characteristics of the voltage and the current of M3, thereby improving the gain of the power amplifier under large signals.
Optionally, in this embodiment of the present application, the power amplifier 1 further includes an input impedance matching circuit and an output impedance matching circuit; the input impedance matching circuit is connected in series on a branch where the grid of the first transistor is positioned; the output impedance matching circuit is connected in series on a branch where the drain of the first transistor is; the input impedance of the first transistor is adjusted by the input impedance matching circuit, the output impedance of the first transistor is adjusted by the output impedance matching circuit, and the adjusted input impedance and the adjusted output impedance are matched with the load impedance.
In the embodiment of the present application, as shown in fig. 6, the power amplifier circuit further includes an input impedance matching circuit and an output impedance matching circuit, the input impedance matching circuit is connected in series to the branch where the gate of the transistor M1 is located, and the output matching circuit is connected in series to the branch where the drain of the transistor M1 is located.
In the embodiment of the present application, the input impedance matching circuit and the output impedance matching circuit respectively provide the power amplifier with suitable input impedance and output impedance, which are adjusted by the input impedance and output impedance of the transistor M1 so as to match the load impedance of the external circuit.
It should be noted that the load impedance of the external circuit is typically 50ohm.
In the embodiment of the present application, the input impedance matching circuit may be a capacitor and/or a resistor; the output impedance matching circuit may be a capacitor and/or a resistor.
In the embodiment of the present application, for example, as shown in fig. 7, the capacitor in the input impedance matching circuit is connected in series in the branch where the input terminal of the first transistor is located; one end of the capacitor is connected with the grid electrode of the first transistor M1, and the input radio frequency signal is output from the other end of the capacitor in the input impedance matching circuit through the capacitor and is transmitted to the grid electrode of the first transistor; a capacitor in the output impedance matching circuit is connected in series with a branch circuit where the output end of the first transistor is located; one end of a capacitor in the input impedance matching circuit is connected with the drain electrode of the first transistor M1, and after the input radio-frequency signal is amplified by the transistor M1, the amplified radio-frequency signal is output from the other end of the capacitor in the output impedance matching circuit.
In the embodiment of the present application, the input impedance matching circuit includes a capacitor C2, and the radio frequency signal input to the gate of the transistor M1 is input through one end of the capacitor C2 and output from the other end of the capacitor C2 to the gate of the transistor M1; the output impedance matching circuit comprises a capacitor C3, and the amplified radio-frequency signal is output through the drain electrode of the transistor M1 and is output through the capacitor C3.
Optionally, in this embodiment, the input impedance matching circuit and/or the output impedance matching circuit may also be a combination circuit among an inductor, a capacitor, and a resistor. It should be noted that the input impedance matching circuit and the output impedance matching circuit may be any components capable of matching the input impedance and the output impedance of the power amplifier, and are not limited to the above-mentioned capacitor and resistor, and may be selected according to the actual situation, and are not specifically limited in this application.
Optionally, the power amplifier further comprises a first inductor; one end of the first inductor is connected with the drain electrode of the first transistor; the other end of the first inductor is connected with a direct-current power supply; and isolating the radio-frequency signal transmitted in the path between the drain electrode of the first transistor and the direct-current power supply by using the first inductor.
In this embodiment, as shown in fig. 8, the power amplifier circuit further includes a first inductor L1, one end of the first inductor L1 is connected to the drain of the first transistor M1, and the other end of the first inductor L1 is connected to the dc power VDD, and the first inductor L1 can isolate the rf signal leaked from the drain of the first transistor on the path where the first inductor L1 is located, specifically, in the path where the input rf signal leaks to the first inductor L1 along the gate of the transistor M1 through the drain of the transistor M1, the rf signal leaked from the path is isolated by the first inductor L1.
In the embodiment of the present invention, when the first transistor is turned on, in order to prevent the rf signal leaked from the first transistor from affecting the dc power VDD, the rf signal leaked from the first transistor may be isolated from the dc power VDD by the first inductor.
Optionally, the bias circuit further comprises a fourth transistor and a fifth transistor; the grid electrode of the fourth transistor is connected with the grid electrode of the third transistor, the drain electrode of the fourth transistor is respectively connected with the grid electrode of the third transistor and the direct current power supply, and a current mirror is formed by the fourth transistor and the third transistor; the source electrode of the fourth transistor is connected with the grid electrode of the fifth transistor and the drain electrode of the fifth transistor; the source of the fifth transistor is grounded.
In the embodiment of the present application, as shown in fig. 9, the structure of the bias circuit 10 further includes a fourth transistor M4 and a fifth transistor M5, the fourth transistor M4 and the fifth transistor M5 are connected in a cascade manner, a gate and a drain of the fourth transistor M4 are connected to a gate of the third transistor M3, a source of the fourth transistor M4 is connected to a gate and a drain of the fifth transistor M5, a source of the fifth transistor M5 is grounded, and M4 and M5 are CMOS transistors connected by a diode connection manner.
Optionally, the bias circuit further comprises a second resistor; one end of the second resistor is connected with the grid electrode of the first transistor; the other end of the second resistor is connected with the source electrode of the third transistor; when the current transmitted by the grid electrode of the first transistor changes along with the temperature of the first transistor, the current is adjusted by the second resistor so as to adjust the bias voltage of the first transistor.
It should be noted that the current transmitted at the gate of the first transistor may increase with the temperature of the first transistor, and the current is adjusted by the second resistor to adjust the bias voltage of the first transistor.
In the embodiment of the present application, as shown in fig. 10, the bias circuit 10 further includes a second resistor R2, one end of the R2 is connected to the source of M3, the other end of the R2 is connected to the gate of M1, and the resistor R2 can perform negative feedback on M1 to ensure the stability of the operating state of M1.
Optionally, the bias circuit further comprises a third resistor; one end of the third resistor is connected with the drain electrode of the fourth transistor; the other end of the third resistor is connected with the grid electrode of the third transistor; the leaked radio frequency signal is isolated from the power supply by a third resistor.
In this embodiment, the rf signal is transmitted through a path between the gate of the third transistor and the drain of the fourth transistor, the transmitted rf signal leaks to the power supply along a path connected to the power supply, and the rf signal leaking to the power supply can be isolated by the third resistor.
In the embodiment of the present application, as shown in fig. 11, the bias circuit further includes a third resistor R3, one end of R3 is connected to the gate and the drain of M4, and the other end of R3 is connected to the gate of M3.
In the embodiment of the present application, the resistor R3 is used to isolate the rf signal leaked from M3, so as to prevent the rf signal from entering M4 and M5 to affect the DC bias voltage of the power supply.
In the embodiment of the present application, an input rf signal is transmitted to the gate of the transistor M4 through the gate of the transistor M3 along the source of the transistor M3, and in order to ensure that the leaked rf signal does not enter M4 and M5 and affect the second bias voltage, a resistor R4 is disposed between M3 and M4, and the rf signal transmitted to the gate of the fourth transistor is isolated by using the resistor R4.
It should be noted that, depending on the implementation of the CMOS amplifier, the structure of the present application may also be used for other types of CMOS amplifiers, such as a cascode type or a differential type.
It should be noted that the CMOS circuit process of the present invention may be a Bulk CMOS process or an SOI CMOS process.
It should be noted that the CMOS transistor in the present application may be NMOS or PMOS.
It should be noted that, the present application utilizes a low-cost CMOS process, and realizes power characteristics similar to HBT devices through an improved power amplifier circuit, and has a simple structure and good versatility, and can be used for designing a linear power amplifier.
In the embodiment of the present application, the ratio of the total widths of M1 and M2 may be equivalent to the current amplification factor β of the HBT, and a typical value thereof may be about 100 to 150. Its DC-IV characteristics are similar to the exponential relationship, similar to HBT transistors, as shown in fig. 12.
In the embodiment of the present application, as shown in fig. 13, the gain power curves of two power amplifiers in the prior art and the improved power amplifier of the present application are shown, and it can be seen from fig. 13 that the gain of the conventional CMOS power amplifier generally shows a decreasing trend when the output power is larger, and the whole shows a characteristic of gain compression; the HBT power amplifier generally has a region with gain increasing along with power due to the exponential characteristic and the effect of a bias circuit, and the whole HBT power amplifier has the characteristic of gain expansion; the CMOS power amplifier can realize a gain curve similar to an HBT through a working mode similar to a circuit designed in the HBT power amplifier, and has the characteristic of gain expansion. Because the HBT has better high-frequency performance, its single-stage gain is generally higher than that of the CMOS power amplifier. For radio frequency power amplifiers, the gain expansion characteristic is more advantageous for designing linear power amplifiers PA, which can be combined with the gain compression characteristic of the preamplifier to realize a flat gain curve in a multistage PA, thereby obtaining better linearity.
It can be understood that, in the power amplifier provided in the embodiments of the present application, by improving the existing CMOS power amplifier, the bias current output in the bias circuit of the power amplifier increases with the increase of the power of the radio frequency signal, so that the bias voltage affecting the input terminal of the amplifier circuit also increases with the increase of the bias current output in the bias circuit, and the linearity of the transistor for amplifying the radio frequency signal in the amplifier circuit is improved by using the varying bias voltage.
It should be noted that the modified current source device is connected in a manner similar to a bias circuit of an HBT, and the M2 connected as a source follower is used to provide bias for the amplifier tube, so that a gain expansion effect similar to the HBT circuit can be achieved, and finally the linearity of the power amplifier is improved.
Based on the foregoing embodiments, the mobile terminal provided in this application includes any one of the power amplifiers in the foregoing embodiments, and the composition and implementation principle of the power amplifier are discussed in the foregoing embodiments, and are not described herein again.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a component of' 8230; \8230;" does not exclude the presence of another like element in a process, method, article, or apparatus that comprises the element.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling an image display device (e.g., a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present application.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (11)
1. A power amplifier, characterized in that the power amplifier comprises: a bias circuit and an amplification circuit; the amplifying circuit comprises a first transistor and a shunt circuit;
the bias circuit is used for providing bias current for the amplifying circuit;
the amplifying circuit is used for amplifying the input radio frequency signal and outputting the amplified radio frequency signal;
the grid electrode of the first transistor is connected with the bias circuit, the source electrode of the first transistor is grounded, and the drain electrode of the first transistor is connected with a power supply;
the input end of the shunt circuit is connected with the grid electrode of the first transistor, and the output end of the shunt circuit is used for leading out the first bias current output by the bias circuit so as to drive the first transistor by utilizing the first bias current.
2. The power amplifier of claim 1, wherein the shunt circuit comprises a second transistor;
the grid electrode of the second transistor and the drain electrode of the second transistor are respectively connected with the grid electrode of the first transistor; and the source electrode of the second transistor is used for leading out the bias current output by the bias circuit.
3. The power amplifier of claim 1, wherein the shunt circuit comprises a diode;
the anode of the diode is connected with the grid of the first transistor; and the cathode of the diode is used for leading out the bias current output by the bias circuit.
4. The power amplifier of claim 1, wherein the shunt circuit comprises a first resistor;
one end of the first resistor is connected with the grid electrode of the first transistor; and the other end of the first resistor is used for leading out the bias current output by the bias circuit.
5. The power amplifier of claim 1, wherein the output of the shunt circuit is connected to ground.
6. The power amplifier of claim 1, wherein the bias circuit comprises a third transistor and a first capacitor;
the grid electrode of the third transistor is connected with one end of the first capacitor, and the other end of the first capacitor is grounded; a source of the third transistor is connected to a gate of the first transistor; the drain electrode of the third transistor is connected with a power supply;
the third transistor is used for providing bias current to a grid electrode of the first transistor;
the first capacitor is used for guiding the radio-frequency signal transmitted in a path where the drain electrode of the third transistor and the grid electrode of the third transistor are located to the ground.
7. The power amplifier of claim 1, wherein the bias circuit further comprises a fourth transistor and a fifth transistor;
the grid electrode of the fourth transistor is connected with the grid electrode of the third transistor; the drain electrode of the fourth transistor is respectively connected with the grid electrode of the third transistor and a direct current power supply; a source of the fourth transistor is connected with a gate of the fifth transistor and a drain of the fifth transistor; the source of the fifth transistor is grounded.
8. The power amplifier of claim 7, wherein the bias circuit further comprises a second resistor;
one end of the second resistor is connected with the grid electrode of the first transistor; the other end of the second resistor is connected with a source electrode of the third transistor;
when the current transmitted by the grid electrode of the first transistor changes along with the temperature of the first transistor, the current is adjusted by the second resistor so as to adjust the bias voltage of the first transistor.
9. The power amplifier of claim 7, wherein the bias circuit further comprises a third resistor;
one end of the third resistor is connected with the drain electrode of the fourth transistor; the other end of the third resistor is connected with the grid electrode of the third transistor;
and isolating the leaked radio frequency signal from the power supply by using the third resistor.
10. The power amplifier of claim 1, wherein the power amplifier is a CMOS power amplifier.
11. A mobile terminal, characterized in that the mobile terminal comprises a power amplifier according to any of claims 1-10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211718282.XA CN115955201A (en) | 2022-12-29 | 2022-12-29 | Power amplifier and mobile terminal |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211718282.XA CN115955201A (en) | 2022-12-29 | 2022-12-29 | Power amplifier and mobile terminal |
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| CN115955201A true CN115955201A (en) | 2023-04-11 |
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| CN202211718282.XA Pending CN115955201A (en) | 2022-12-29 | 2022-12-29 | Power amplifier and mobile terminal |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050083128A1 (en) * | 2003-10-16 | 2005-04-21 | Yi-Jen Chan | [power amplifier with active bias circuit] |
| CN107863939A (en) * | 2017-11-09 | 2018-03-30 | 西安电子科技大学 | Low-power consumption feedback-type power amplification circuit |
| CN110677132A (en) * | 2019-09-05 | 2020-01-10 | 广州穗源微电子科技有限公司 | Radio frequency linear power amplifier circuit |
-
2022
- 2022-12-29 CN CN202211718282.XA patent/CN115955201A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050083128A1 (en) * | 2003-10-16 | 2005-04-21 | Yi-Jen Chan | [power amplifier with active bias circuit] |
| CN107863939A (en) * | 2017-11-09 | 2018-03-30 | 西安电子科技大学 | Low-power consumption feedback-type power amplification circuit |
| CN110677132A (en) * | 2019-09-05 | 2020-01-10 | 广州穗源微电子科技有限公司 | Radio frequency linear power amplifier circuit |
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