CN115953213A

CN115953213A - Virtual integrated circuit platform and control method and system thereof

Info

Publication number: CN115953213A
Application number: CN202211361182.6A
Authority: CN
Inventors: 高大为; 陈鼎崴; 许凯; 张凯; 柴路芸
Original assignee: Zhejiang Chuangxin Integrated Circuit Co ltd
Current assignee: Zhejiang Chuangxin Integrated Circuit Co ltd
Priority date: 2022-10-31
Filing date: 2022-10-31
Publication date: 2023-04-11

Abstract

A virtual integrated circuit platform and a control method and a system thereof are provided. The method comprises the following steps: when chip demand information sent by a demand party is received, generating a chip design order based on the chip demand information; the chip requirement information includes: requirement type indication information and chip related information; the requirement type indication information is used for indicating the requirement type of a requirement party, and the requirement type comprises at least one of the following: chip design requirements and chip manufacturing requirements; identifying characteristic information in the chip design order to obtain layout information matched with the chip design order; and when the demand type indicated by the demand type indication information is only a chip design demand, completing delivery of the layout information matched with the chip design order. By adopting the scheme, the chip cost can be reduced.

Description

Virtual integrated circuit platform and control method and system thereof

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a virtual integrated circuit platform and a control method and a control system thereof.

Background

The integrated circuit needs to go through three links of design, manufacture and seal test to obtain a corresponding chip. Specifically, after the integrated circuit is successfully designed, real tape-out manufacturing is started, and after the integrated circuit is manufactured, sealing and testing are performed, and the chips which pass the sealing and testing can be delivered.

In practical applications, a large amount of cost including labor cost, time cost and the like is required in any link, and particularly, in an integrated circuit design link and an integrated circuit manufacturing link, the chip cost is high.

Disclosure of Invention

The invention aims to solve the problems that: how to reduce the chip cost.

In order to solve the above problem, an embodiment of the present invention provides a method for controlling a virtual integrated circuit platform, where the method includes: when chip demand information sent by a demand side is received, generating a chip design order based on the chip demand information; the chip requirement information includes: requirement type indication information and chip related information; the requirement type indication information is used for indicating the requirement type of a requirement party, and the requirement type comprises at least one of the following: chip design requirements and chip manufacturing requirements; identifying characteristic information in the chip design order to obtain layout information matched with the chip design order; and when the demand type indicated by the demand type indication information is only the chip design demand, completing the delivery of the layout information matched with the chip design order.

Optionally, the chip-related information includes: product information of the chip and chip specification information.

Optionally, the identifying the feature information in the chip design order and generating layout information matched with the chip design order include:

identifying characteristic information in the chip design order, and matching the characteristic information with layout information in a preset layout information base based on an identification result;

when the layout information matched with the chip design order exists in the preset layout information base, taking the layout information matched with the chip design order in the preset layout information base as the layout information matched with the chip design order;

and when the layout information which is completely matched with the chip order does not exist in the preset layout information base, searching the layout information of which the matching degree with the chip design order is greater than a preset matching degree threshold value in the preset layout information base, and obtaining the layout information matched with the chip design order based on the searching result.

Optionally, the searching for the layout information with the matching degree with the chip design order being greater than the preset matching degree threshold in the preset layout information base, and obtaining the layout information matched with the chip design order based on the search result includes:

when layout information with the matching degree with the chip design order being greater than a preset matching degree threshold exists in the preset layout information base, correcting the layout information with the matching degree with the chip design order being greater than the preset matching degree threshold in the preset layout information base, wherein the corrected layout information is used as the layout information matched with the chip design order;

when the preset layout information base does not have layout information of which the matching degree with the chip design order is greater than a preset matching degree threshold value, the chip design order is sent to a corresponding design end, and when chip design response information sent by the corresponding design end is received, the layout information carried in the chip design response information is used as the layout information matched with the chip design order.

Optionally, the design end is a design end that is registered in the virtual integrated circuit platform and meets the design capability requirement corresponding to the chip order.

Optionally, when the requirement type indicated by the requirement type indication information includes a chip manufacturing requirement, the method further includes: generating a chip manufacturing order based on the obtained layout information, and sending the chip manufacturing order to a corresponding manufacturing end; and when the manufacturing response information sent by the manufacturing end corresponding to the chip manufacturing order is received, the charging and distribution of the fee of the chip order are completed.

Optionally, the manufacturing end is a manufacturing end that is registered in the virtual integrated circuit platform and meets the manufacturing capability requirement corresponding to the chip order.

Optionally, the method further comprises: executing simulation tape-out operation based on the layout information matched with the chip design order and the chip requirement information; performing yield analysis based on the result of the simulated tape-out operation; and calculating to obtain the actual tape-out cost based on the yield analysis result so as to be used for collecting and distributing the fee of the chip order.

Optionally, the executing a simulated tape-out operation based on the layout information matched with the chip design order and the chip requirement information includes: determining a process type corresponding to the chip manufacturing order based on the layout information matched with the chip design order and the chip requirement information; creating corresponding process flow information based on the determined process type; configuring manufacturing information required by each process flow based on the created process flow information; based on the manufacturing information required for each process flow, a simulated tape-out operation is performed.

Optionally, the method further comprises: generating quotation information based on the actual tape-out cost obtained by calculation, and sending the generated quotation information to a demand side; and when receiving a quotation agreement response message of a demand party, sending the chip manufacturing order to a corresponding manufacturing end, wherein the chip manufacturing order comprises a process flow corresponding to the simulation tape-out operation.

The embodiment of the invention also provides a virtual integrated circuit platform, which comprises a demander management module and a platform operation module; wherein, demand side management module includes: a demand management unit;

the demand management unit is suitable for receiving chip demand information sent by a demand party;

the platform operation module is suitable for generating a chip design order based on chip demand information when the chip demand information sent by a demand party is received; identifying characteristic information in the chip design order to obtain layout information matched with the chip design order;

the chip requirement information includes: requirement type indication information and chip related information; the requirement type indication information is used for indicating the requirement type of a requirement party, and the requirement type comprises at least one of the following: chip design requirements and chip manufacturing requirements;

the demand management unit is further adapted to complete delivery of the layout information matched with the chip order when the demand type indicated by the demand type indication information is only a chip design demand.

Optionally, the platform operation module includes:

the third order management unit is suitable for identifying characteristic information in the chip order and matching the characteristic information with layout information in a preset layout information base based on an identification result, and when the layout information matched with the chip design order exists in the preset layout information base, the layout information matched with the chip design order in the preset layout information base is used as the layout information matched with the chip design order; and when the layout information which is completely matched with the chip order does not exist in the preset layout information base, searching the layout information of which the matching degree with the chip design order is greater than a preset matching degree threshold value in the preset layout information base, and obtaining the layout information matched with the chip design order based on the searching result.

Optionally, the third order management unit is adapted to, when layout information whose matching degree with the chip design order is greater than a preset matching degree threshold exists in the preset layout information base, modify the layout information whose matching degree with the chip design order is greater than the preset matching degree threshold in the preset layout information base, where the modified layout information is used as the layout information matched with the chip design order; when the preset layout information base does not have layout information of which the matching degree with the chip design order is greater than a preset matching degree threshold value, the chip design order is sent to a corresponding design end, and when chip design response information sent by the corresponding design end is received, the layout information carried in the chip design response information is used as the layout information matched with the chip design order.

Optionally, the virtual integrated circuit platform further includes: a manufacturing end management module;

the third order management unit is further adapted to generate a chip manufacturing order based on the obtained layout information and send the chip manufacturing order to the manufacturing end management module when the demand type indicated by the demand type indication information includes a chip manufacturing demand;

the manufacturing-side management module includes: the second order management unit is suitable for receiving the chip manufacturing order sent by the third order management unit and sending the chip manufacturing order to a corresponding manufacturing end; and the third fee management unit is suitable for receiving the manufacturing response information corresponding to the chip manufacturing order sent by the manufacturing end and finishing the fee collection and distribution with the manufacturing end.

Optionally, the platform operation module further includes:

the simulation tape-out unit is suitable for executing simulation tape-out operation based on layout information matched with the chip design order and the chip requirement information;

the yield analysis unit is suitable for carrying out yield analysis based on the result of the simulation tape-out operation;

and the cost calculation unit is suitable for calculating the actual tape-out cost based on the yield analysis result so as to be used for collecting and distributing the fee of the chip order.

Optionally, the analog tape-out unit is adapted to determine a process type corresponding to the chip manufacturing order based on layout information matched with the chip design order and the chip requirement information; based on the determined process type, creating corresponding process flow information; configuring manufacturing information required by each process flow based on the created process flow information; and executing the simulation tape-out operation based on the manufacturing information required by each process flow.

Optionally, the platform operation module further includes:

the fourth expense management unit is suitable for generating quotation information based on the actual tape-out cost obtained by calculation and sending the generated quotation information to the demand side management module;

the third order management unit is suitable for sending the chip manufacturing order to the manufacturing end management module when receiving quotation agreement response information of a demand side, wherein the chip manufacturing order comprises a process flow corresponding to the simulation tape-out operation;

the demand side management module further comprises: the first expense management unit is suitable for receiving the quotation information sent by the expense management unit, completing the expense collection and distribution with a demand party, receiving the quotation agreement response information of the demand party and sending the quotation agreement response information of the demand party to the fourth expense management unit.

An embodiment of the present invention further provides a virtual integrated circuit system, where the system includes: a virtual integrated circuit platform of any of the above.

Optionally, the system further comprises: and the design end is used for receiving the design order sent by the virtual integrated circuit platform and sending chip design response information to the virtual integrated circuit platform after the chip design is finished.

Optionally, the system further comprises: and the manufacturing end is used for receiving the manufacturing order sent by the virtual integrated circuit platform and sending manufacturing response information to the virtual integrated circuit platform after the chip is manufactured.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

by applying the scheme of the invention, the virtual integrated circuit platform can receive the chip related information sent by the demand side, generate the chip order based on the chip related information, identify the characteristic information in the chip order and obtain the layout information matched with the chip order. When the chip related information only includes chip design requirement information, the virtual integrated circuit platform can feed back layout information matched with the chip order to a demander. That is to say, the scheme of the invention can provide the matched layout information for the demander based on the chip design requirement of the demander, and further can save the labor cost and the time cost required by the demander in the process of searching for a chip design company, thereby reducing the chip cost.

Drawings

Fig. 1 is a flowchart of a control method for a virtual integrated circuit platform according to an embodiment of the present invention;

FIG. 2 is a flowchart of another control method for a virtual integrated circuit platform according to an embodiment of the present invention;

FIG. 3 is a flowchart of another control method for a virtual integrated circuit platform according to an embodiment of the present invention;

FIG. 4 is a block diagram of a virtual integrated circuit platform according to an embodiment of the present invention;

FIG. 5 is a functional diagram of modules of a virtual integrated circuit platform according to an embodiment of the present invention;

fig. 6 is a schematic diagram of information interaction among functional units of a virtual integrated circuit platform according to an embodiment of the present invention.

Detailed Description

With the continuous expansion of the global chip market, china, which is the first large market, is continuously increasing productivity, and the number of domestic chip design enterprises is increasing, and most domestic chip design enterprises are performing chip design for large-scale chip demand enterprises.

At present, most of the enterprises with the existing chip demands search suitable chip design enterprises for designing chips by a manual mode. However, for some small and medium-sized enterprises and laboratory designed chips, the demand is very small, the process is unstable, and few chip design enterprises help to design the chips. Therefore, a large amount of labor cost and time cost are required for small and medium-sized enterprises and laboratories to search for appropriate chip design enterprises for chip design, which results in higher final chip cost.

Aiming at the problem, the invention provides a control method of a virtual integrated circuit platform, and by adopting the method, the virtual integrated circuit platform can provide matched layout information for a demand side based on the chip design demand of the demand side, so that the labor cost and the time cost required by the demand side in the process of finding a chip design company can be saved, and the chip cost is finally reduced.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 1, an embodiment of the present invention provides a method for controlling a virtual integrated circuit platform, where the method may include the following steps:

and 11, when chip requirement information sent by a requiring party is received, generating a chip design order based on the chip requirement information.

Wherein the chip requirement information includes: requirement type indication information and chip related information; the requirement type indication information is used for indicating the requirement type of a requirement party, and the requirement type comprises at least one of the following: chip design requirements and chip manufacturing requirements.

The receiving manner of the chip requirement information may be various, and is not limited herein. For example, the virtual integrated circuit platform may provide a demander access interface on which a demander may enter chip related information. In some embodiments, the demander may also input the chip requirement information by way of remote wireless access.

In a specific implementation, the chip-related information is information required to satisfy the demand type of the demand side. When the requirement type of the demander is the chip design requirement, the chip related information is the information required by meeting the chip design requirement. When the requirement type of the demander is a chip manufacturing requirement, the chip related information is information required for meeting the chip manufacturing requirement. When the requirement type of the demander comprises a chip design requirement and a chip manufacturing requirement, the chip related information is information required for meeting the chip design requirement and the chip manufacturing requirement.

In a specific implementation, the chip related information may include: product information of the chip and chip specification information. The product of the chip can be a memory, a charger, a CPU, a camera, a sensor and the like. The chip specification may be the operating temperature, operating voltage, area, power consumption, etc. of the chip. Based on the chip-related information, a process function (function) type corresponding to the chip can be determined, and based on the chip-corresponding process function type and the chip-related information, a process technology type corresponding to the chip can be determined. Wherein, the process function type can include: logic chips, power chips, radio frequency chips, mixed signal (Mix-signal) chips, micro-Electro-Mechanical systems (MEMS) chips, digital-analog chips, and the like. The process technology types may include: 55nm, 90nm and 40 nm.

In a specific implementation, the chip design order template with multiple formats may be preset on the virtual integrated circuit platform. The chip order templates may be sorted according to the product or specification in which the chip is located. After the chip related information is received, corresponding information in the chip related information can be extracted and filled into a corresponding chip order template to form a chip order. When the content of the partial information item of the chip order template is absent from the chip related information, the default information content can be used as the content of the partial information item of the chip order template.

In a specific implementation, the chip design order template with multiple formats may be preset on the virtual integrated circuit platform. The chip design order template may be classified according to process function type. And extracting corresponding information in the chip demand information, and filling the corresponding chip demand information into a corresponding chip design order template to form a chip design order. When the content of a part of information items of a chip design order is absent in a chip order, the default information content can be used as the content of the part of information items of the chip design order template.

And step 12, identifying characteristic information in the chip design order to obtain layout information matched with the chip design order.

In specific implementation, the characteristic information in the chip design order is information for forming a chip layout. And obtaining layout information matched with the chip design order based on the chip order, namely a chip design process. The chip design is based on chip requirements and provides a chip layout, wherein the chip layout comprises specification formulation, logic design, layout planning, performance design, circuit simulation, layout wiring, layout verification and the like of a chip. The chip layout is a graphic file containing a layout structure. Tape-out may be subsequently fabricated according to the chip layout.

In a specific implementation, the virtual integrated circuit platform may be preset with a layout information base, where the preset layout information base is a preset layout information base. After the characteristic information in the chip design order is identified, the characteristic information can be matched with the layout information in the preset layout information base based on the identification result. And when the layout information matched with the chip order exists in the preset layout information base, taking the layout information matched with the chip order as the layout information matched with the chip order. And when the layout information which is completely matched with the chip order does not exist in the preset layout information base, searching the layout information of which the matching degree with the chip design order is greater than a preset matching degree threshold value in the preset layout information base, and obtaining the layout information matched with the chip design order based on the searching result. And the layout information matched with the chip design order, namely the layout information required to be used by the actual tape-out, namely the final layout information.

In specific implementation, the preset layout information base may store chip layout information of different chip specifications, different process function types of different products, and different process technology types, and the chip layout information may be stored in a manner of an association table. Based on the chip specification, the product information, the process function type and the process technology type, the corresponding chip layout information can be retrieved.

In specific implementation, when the identification result is matched with the layout information in the preset layout information base, the product information of the chip can be matched with the product information stored in the preset layout information base. And matching the chip specification information in the chip order with the chip specification information corresponding to the stored product information when the same product information exists in the preset layout information base. And if the preset layout information base has layout information of the same product and the same chip specification, determining the corresponding process function type based on the product information and the chip specification information of the chip in the chip order. If the layout information with the same process function type exists in the preset layout information base, whether the layout information with the same process manufacturing technology type exists can be further searched in the layout information with the same process function type.

If the layout information of the same process technology type exists in the layout information of the same process function type, the layout information of the same process technology type, namely the layout information matched with the chip design order, is used as the layout information matched with the chip design order, namely the final layout information.

If the layout information of the same process technology type does not exist in the layout information of the same process function type, the layout information of which the matching degree with the chip design order is greater than a preset matching degree threshold value can be searched in a preset layout information base, and the layout information matched with the chip design order is obtained based on the searching result.

And when the preset layout information base has layout information of which the matching degree with the chip design order is greater than a preset matching degree threshold value, correcting the layout information of which the matching degree with the chip design order is greater than the preset matching degree threshold value in the preset layout information base, wherein the corrected layout information is used as finally obtained layout information.

That is to say, the virtual integrated circuit platform may optimize, according to the chip design order, layout information in the preset layout information base, for which the matching degree with the chip design order is greater than the preset matching degree threshold, and obtain layout information matched with the chip design order again. For example, according to a chip design order, the positions and connection relations of some devices in the layout information with the matching degree of the chip design order being greater than a preset matching degree threshold value can be adjusted.

When layout information with the matching degree larger than a preset matching degree threshold value with the chip design order does not exist in the preset layout information base, the chip design order can be sent to a corresponding design end, the design end carries out chip design based on the chip design order, layout information matched with the chip order is obtained, and the layout information is sent to a virtual integrated circuit platform. And when receiving the chip design response information sent by the corresponding design end, the virtual integrated circuit platform takes the layout information carried in the chip design response information as finally obtained layout information.

In specific implementation, an enterprise or an individual with chip design capability may register on the virtual integrated circuit platform to obtain a corresponding design-side registration account. Each design end registration account corresponds to one design end. The design end which completes the registration should provide the basic information, qualification, design case and the like of the enterprise or team to the virtual integrated circuit platform, so that the virtual integrated circuit platform can evaluate the design capability of the design end. The virtual integrated circuit platform can have a plurality of associated design ends, and the design ends are classified according to the design capacity of the design ends.

The corresponding design end is a design end which is registered in the virtual integrated circuit platform and meets the design capability requirement corresponding to the chip order.

That is to say, when layout information with a matching degree greater than a preset matching degree threshold value with the chip design order does not exist in a preset layout information base, the virtual integrated circuit platform selects a design end which is registered and meets the design capability requirement corresponding to the chip design order based on the chip related information, and designs to obtain layout information matched with the chip design order.

In specific implementation, the chip design order may include process function type information corresponding to the chip in addition to chip-related information, so that the design end may quickly design the chip based on the chip design order after receiving the chip design order, thereby shortening the chip design cycle.

In specific implementation, the design end can independently design layout information matched with a chip order based on the chip design order. In some embodiments, the virtual integrated circuit platform may further provide a Design side with a Process Design Kit (PDK) so that the Design side can use the PDK for chip Design without time limitation.

And step 13, when the requirement type indicated by the requirement type indication information is only the chip design requirement, completing the delivery of the layout information matched with the chip order.

In specific implementation, an enterprise or an individual having chip design requirements can register on the virtual integrated circuit platform by using basic information (such as a mobile phone number, an identity card number and the like) and other information (such as mailbox information) to obtain a corresponding registered account of a demander. Each demand party registration account corresponds to one demand party. And the registered demander can submit the chip requirement information to the virtual integrated circuit platform. The virtual integrated circuit platform may manage registration information provided by a claimant.

In specific implementation, when the requirement type indicated by the requirement type indication information is only a chip design requirement, the virtual integrated circuit platform may feed back layout information matched with a chip order to a demand side, so as to complete delivery of chip design.

In practical application, the virtual integrated circuit platform can interact with a demand party before delivery, and the collection of chip design cost is completed. The virtual integrated circuit platform may prompt the payment information to the demander after obtaining the layout information matched with the chip design order, for example, display the payment two-dimensional code to the demander. And after receiving the payment paid by the demand side, delivering the layout information matched with the chip design order to the demand side.

As can be seen from the above, in the control method in the embodiment of the present invention, once the demand party inputs the chip demand information, the virtual integrated circuit platform can provide the corresponding chip layout information for the demand party to complete chip design, and the demand party does not need to search the design end by itself to design the chip, so that the cost of the demand party for searching the design end by itself to design the chip is effectively reduced, and the chip cost is finally reduced.

The embodiment of the invention provides another control method of a virtual integrated circuit platform. Referring to fig. 2, the method includes:

and step 21, when chip requirement information sent by a requiring party is received, generating a chip design order based on the chip requirement information.

And step 22, identifying the characteristic information in the chip design order to obtain layout information matched with the chip design order.

For step 21 and step 22, the above description about

steps

11 and 12 can be specifically referred to for implementation, and will not be described herein again.

And step 23, when the demand type indicated by the demand type indication information includes a chip manufacturing demand, generating a chip manufacturing order based on the obtained layout information, and sending the chip manufacturing order to a corresponding manufacturing end.

In an implementation, a fab with manufacturing capability may provide basic information of the fab (including the number of employees, etc.), qualification information of the fab, capability information of the fab, etc. to the virtual ic platform, and complete registration on the virtual ic platform. The virtual integrated circuit platform can distinguish the manufacturing capability of different wafer factories.

In the prior art, for chips designed by small and medium-sized enterprises and laboratories, the demand is very small, and a plurality of chip factories help to manufacture the tapestry. Therefore, these small and medium sized enterprises and laboratories need to spend a lot of labor cost and time cost to find a suitable foundry for tape-out manufacturing, resulting in a high final cost of the chip.

By adopting the scheme of the invention, the manufacturing end is managed through the virtual integrated circuit platform, once the demander puts forward the chip manufacturing requirement, a proper manufacturing end can be provided for the demander to carry out tape-out manufacturing, so that the time cost and the labor cost required for the demander to find the manufacturing end can be saved, and the chip cost is further reduced.

In a specific implementation, the virtual integrated circuit platform may preset chip manufacturing order templates in various formats. The chip manufacturing order template may be categorized according to process type (including process function type and process recipe technology type). After receiving the chip layout information, the chip layout information and the corresponding information in the chip demand information can be filled into the corresponding chip manufacturing order template to form a chip manufacturing order. When the chip manufacture order template lacks the content of the part information item, the default information content may be used as the content of the part information item of the chip manufacture order template.

In some embodiments, before sending a chip manufacturing order to a corresponding manufacturing end, a simulated tape-out operation may be executed based on layout information matched with the chip design order and the chip demand information, yield analysis may be performed based on a result of the simulated tape-out operation, and an actual tape-out cost may be calculated based on a result of the yield analysis, so as to be used for collecting and distributing a fee of the chip order.

The cost of the chip is calculated by simulating the tape-out, and compared with the actual tape-out, the economic loss of a virtual integrated circuit platform and a manufacturing end caused by too low yield in the actual tape-out process can be reduced. In some embodiments, the actual process flow may be adjusted based on the simulated tape-out results, improving the yield of actual tape-out.

In a specific implementation, when the virtual integrated circuit platform executes the analog tape-out operation, a process type corresponding to the chip manufacturing order may be determined based on layout information matched with the chip design order and the chip requirement information, then corresponding process flow information may be created based on the determined process type, manufacturing information required by each process flow may be configured based on the created process flow information, and finally, the analog tape-out operation may be executed based on the manufacturing information required by each process flow.

The process types include a process function type and a process recipe type. Based on the chip-related information, the corresponding process function type may be determined. Based on the chip-related information and the process function type, the process recipe technology type can be determined. Different process function types and process technology types have different process flows.

In determining the process type, corresponding process flow information may be created, such as performing a first process, then performing a second process, and so on. Manufacturing information required by each process flow is configured based on the created process flow information, wherein the manufacturing information comprises equipment information, formula information, carrier information, photomask information and the like. And finally, performing the simulated tape-out operation according to the determined process flows and the manufacturing information required by the process flows.

In a specific implementation, after the tape-out is simulated, a simulation test can be performed on the result of the simulated tape-out, and the yield and the like can be calculated. And analyzing the data of the process flow, equipment and the like by utilizing the big data, and finally calculating the cost of the tape-out.

In specific implementation, the analog tape-out process flow with the yield greater than the preset yield threshold value can be added to the chip manufacturing order and sent to the corresponding manufacturing end, so that the manufacturing end can refer to the analog tape-out process flow in the chip manufacturing order to manufacture the chip, and the yield of the actual tape-out is ensured.

In some embodiments, the chip manufacturing order may not include the simulated tape-out process flow, and the manufacturing end may set the manufacturing flow by itself.

In some embodiments, before sending the chip manufacturing order to the manufacturing side, price quote information may be generated based on the calculated actual cost of tape-out, and the generated price quote information is sent to the demand side, and when receiving a price quote agreement response message of the demand side, the chip manufacturing order is sent to the corresponding manufacturing side. The chip manufacturing order may include a process flow corresponding to the simulation tape-out operation.

That is to say, before the actual tape-out, the actual tape-out cost obtained by calculation may be provided to the demand side, and after the demand side agrees to the quotation, the actual tape-out is performed, so that the delivery is prevented from being affected by the over-high quotation of the actual flow, and the delivery success rate is improved.

In a specific implementation, after receiving the chip manufacturing order, the manufacturing end may directly manufacture the chip by using the manufacturing resources of the manufacturing plant, or may substitute the manufacturing resources of other manufacturing plants, which is not limited herein. For part of process types, the manufacturing end has the condition of no manufacturing license (license), and at this time, the virtual integrated circuit platform can authorize the relevant manufacturing license, and the manufacturing end only needs to pay the relevant authorization fee to the virtual integrated circuit platform.

In a specific implementation, after the tape-out is completed, the manufacturing terminal with the encapsulation testing capability can perform encapsulation testing on the manufactured chip.

In an embodiment of the invention, for some manufacturing terminals without package testing capability, after the virtual integrated circuit platform generates the chip manufacturing order, the virtual integrated circuit platform may further include: and sending sealing and testing indication information to the manufacturing end corresponding to the chip manufacturing order, wherein the sealing and testing indication information is suitable for indicating the identification information of the sealing and testing end, so that the manufactured chip is transported to the indicated sealing and testing end for sealing and testing after the manufacturing of the chip is completed by the manufacturing end corresponding to the chip manufacturing order.

That is, for some manufacturing terminals without encapsulation capability, the manufactured chips can be transported to the indicated encapsulation terminals for encapsulation under the indication of the virtual integrated circuit platform.

In specific implementation, a seal terminal with seal capability can be registered on a virtual integrated circuit platform to obtain a corresponding seal terminal registration account. Each seal terminal registration account corresponds to one seal terminal. The seal terminal completing registration should provide basic information, qualification, seal case and the like of an enterprise or a team to the virtual integrated circuit platform, so that the virtual integrated circuit platform can evaluate the design capability of the seal terminal. The virtual integrated circuit platform can have a plurality of associated sealed terminals, and the sealed terminals are classified according to the sealed test capability of the sealed terminals.

In an implementation, the manufacturing side directly sends the manufactured chip to the testing side, and the manufactured chip may also be sent to the testing side through the virtual integrated circuit platform, which is not limited herein.

And 24, when the manufacturing response information sent by the manufacturing end corresponding to the chip manufacturing order is received, completing the fee collection and distribution of the chip order.

In an implementation, the manufacturing end starts to manufacture the tape-out after receiving the chip manufacturing order, and sends manufacturing response information to the virtual integrated circuit platform after the manufacturing is finished. After receiving the manufacturing response message, the virtual integrated circuit platform may collect a fee from the requesting party according to the price quoted by the requesting party, and distribute the fee to the design end and the manufacturing end according to a predetermined fee distribution ratio among the design end, the virtual integrated circuit platform, and the manufacturing end.

In one embodiment, after the chip order is received and distributed, the manufacturing end may directly deliver the chip to the customer, i.e., deliver the chip.

Fig. 3 is a flowchart of a virtual integrated circuit platform control method according to an embodiment of the present invention. Referring to fig. 3, the method may include the steps of:

step 301, a demand direction virtual integrated circuit platform puts forward chip design demands and chip manufacturing demands.

In specific implementation, the chip design requirement and the chip manufacturing requirement are indicated through requirement type indication information. The requirement type indication information is located in the chip requirement information. Besides the requirement type indication information, the chip requirement information also comprises chip related information.

Step 302, the virtual integrated circuit platform classifies the process functions according to the chip requirements.

Specifically, the virtual integrated circuit platform may classify the process functions according to chip-related information (e.g., information about a product where the chip is located and information about specifications of the chip) to determine the function type of the chip.

Step 303, forming a chip design order and sending the chip design order to a design end.

In specific implementation, when the preset layout information database does not have layout information of the same process function type as the chip order, the virtual integrated circuit platform can form a chip design order and send the chip design order to the design end after the process functions are classified. At this time, the chip design order can protect the process function type information to which the chip to be manufactured belongs.

And step 304, the design end provides layout information matched with the chip design order.

In specific implementation, after receiving a chip design order, a design end may perform chip design to obtain layout information matched with the chip design order.

At step 305, process recipe technology classification is performed according to the process function type.

In the specific implementation, the chip related information and the determined process function type can be combined to perform process technology classification, and the process node to which the chip to be produced belongs is determined.

And step 306, simulating the flow sheet.

In an implementation, after determining the type of the process technology, the simulation tape-out operation may be performed according to the complexity of the process flow.

And 307, calculating the cost required by the whole tape-out, calculating the profit according to the cost and generating quotation information.

In specific implementation, yield analysis can be performed on the result of the simulation tape-out operation, and then the result of the yield analysis is calculated to obtain the actual tape-out cost. And calculating corresponding profit based on the actual slide cost, and generating quotation information according to the actual slide cost and the profit.

At step 308, offer is provided to the requesting party.

In the specific implementation, the quotation information can be sent to the demander, and the subsequent chip manufacturing is started only after the demander agrees to quotation, that is, a chip manufacturing order is generated to the manufacturing end after the demander agrees to quotation.

In some implementations, the chip requirement information provided by the demander may include expected quote information. The virtual integrated circuit platform may generate the offer information in combination with the desired offer information of the requesting party.

Step 309, after tape out, the process flow is sent to the manufacturing end.

In specific implementation, after the demander agrees to quote, the virtual integrated circuit platform may generate a chip manufacturing order and send the chip manufacturing order to the manufacturing end, where the chip manufacturing order includes a process flow, thereby shortening the chip manufacturing period.

At step 310, a fee is allocated to the manufacturing site.

In the specific implementation, after the chip is manufactured, the manufacturing end can directly deliver the chip to a demand side and then perform cost distribution with the virtual integrated circuit platform.

In this embodiment, the manufacturing end has an encapsulation capability, and can deliver the manufactured chip to a demander after encapsulation.

And 311, distributing the cost with the design end.

In a specific implementation, after the quotation information is generated, the cost can be distributed with a design end.

It should be noted that there is no order restriction between step 310 and step 311, and step 310 and step 311 may be performed first, or step 311 and step 310 may be performed first, or step 310 and step 311 may be performed at the same time.

By adopting the scheme, a demander only needs to put forward chip requirements, and can realize chip design and manufacture through the virtual integrated circuit platform to obtain a final chip, so that the virtual integrated circuit platform is convenient to use, can effectively save the labor cost and the time cost required by the demander to search a design end and a manufacture end, and reduces the cost of the chip as much as possible.

In order to make the present invention more comprehensible and practical for those skilled in the art, the virtual integrated circuit platform and the virtual integrated circuit system corresponding to the method are described in detail below.

Referring to fig. 4, an embodiment of the present invention provides a virtual integrated circuit platform 40, where the virtual integrated circuit platform 40 may include a demander management module 41 and a platform operation module 42. Wherein, the demander management module 41 includes: a demand management unit 411.

The requirement management unit 411 is adapted to receive chip requirement information sent by a requiring party;

the platform operation module 42 is adapted to generate a chip design order based on chip requirement information sent by a demander when the chip requirement information is received; and identifying the characteristic information in the chip design order to obtain layout information matched with the chip design order.

the demand management unit 411 is further adapted to complete delivery of the layout information matched with the chip order when the demand type indicated by the demand type indication information is only a chip design demand.

In an embodiment of the present invention, the platform operating module 42 includes: the third order management unit 421. The third order management unit 421 is adapted to identify feature information in the chip order, match the feature information with layout information in a preset layout information base based on an identification result, and when layout information matched with the chip design order exists in the preset layout information base, use the layout information matched with the chip design order in the preset layout information base as the layout information matched with the chip design order; and when the layout information which is completely matched with the chip order does not exist in the preset layout information base, searching the layout information of which the matching degree with the chip design order is greater than a preset matching degree threshold value in the preset layout information base, and obtaining the layout information matched with the chip design order based on a searching result.

Accordingly, the virtual integrated circuit platform further comprises: the end management module 43 is manufactured. The third order management unit 421 is further adapted to generate a chip manufacturing order based on the obtained layout information when the demand type indicated by the demand type indication information includes a chip manufacturing demand, and send the chip manufacturing order to the manufacturing end management module 43.

The manufacturing-side management module 43 includes: a second order management unit 431, adapted to receive the chip manufacturing order sent by the third order management unit 421, and send the chip manufacturing order to a corresponding manufacturing end; and a third fee management unit 432 adapted to receive the manufacturing response information corresponding to the chip manufacturing order sent by the manufacturing end, and complete the fee collection and distribution with the manufacturing end.

In an embodiment of the present invention, the platform operating module 42 may further include: an analog tape out unit 422, a yield analysis unit 423, and a cost calculation unit 424. Wherein:

the analog tape-out unit 422 is adapted to execute an analog tape-out operation based on layout information matched with the chip design order and the chip requirement information;

the yield analysis unit 423 is adapted to perform yield analysis based on the result of the simulated tape-out operation;

the cost calculating unit 424 is adapted to calculate an actual tape-out cost based on the yield analysis result, so as to be used for the fee collection and distribution of the chip order.

In an embodiment of the present invention, the analog tape-out unit 422 is adapted to determine a process type corresponding to the chip manufacturing order based on layout information matched with the chip design order and the chip requirement information; creating corresponding process flow information based on the determined process type; configuring manufacturing information required by each process flow based on the created process flow information; and executing the simulation tape-out operation based on the manufacturing information required by each process flow.

In an embodiment of the present invention, the platform operating module 42 may further include: a fourth fee management unit 425. The fourth cost management unit 425 is adapted to generate quotation information based on the calculated actual tape-out cost, and send the generated quotation information to the demand side management module 41.

The third order management unit 421 is further adapted to send the chip manufacturing order to the manufacturing end management module 43 when receiving a quotation agreement response message from the demand side, where the chip manufacturing order includes a process flow corresponding to the analog tape-out operation;

the demand side management module further comprises: the first fee management unit 413 is adapted to receive the quotation information sent by the fee management unit, complete fee collection and distribution with the demand party, receive the quotation agreement response information of the demand party, and send the quotation agreement response information of the demand party to the fourth fee management unit 425.

In an embodiment of the present invention, the virtual integrated circuit platform 40 may further include: the end management module 44 is designed. The design end management module 44 includes: a second information management unit 441 and a second fee management unit 442. The second information management unit 441 is adapted to process a registration operation of a design side, and store information of the design side that has been registered and satisfies different design capabilities. The second fee management unit 442 is adapted to receive the chip design response information sent by the design end, and complete fee collection and distribution with the design end.

Fig. 5 is a functional diagram of modules of the virtual integrated circuit platform according to an embodiment of the present invention. The functions of the modules of the virtual integrated circuit platform are described as follows:

referring to fig. 5, the demander side management module is mainly responsible for interaction with the demander, which may mainly include:

a. a first information management unit including management demander registration information;

b. a demand management unit;

specifically, the demand management function includes: receiving chip requirement information sent by a demander, wherein the chip requirement information comprises: requirement type indication information. The requirement type indicating information may be only the chip design requirement, may also be only the chip design requirement, and may also include the chip design requirement and the chip manufacturing requirement at the same time.

c. A first fee management unit;

specifically, the wallet function includes: a payment function and a collection function. The payment function can be providing a payment two-dimensional code for the demand party. After receiving the payment amount of the demand party, the payment function may transfer the received payment amount to the platform operation module.

The design end management module is mainly responsible for interaction with the design end, and mainly comprises:

a. the second information management unit comprises registration information for managing the design end, wherein the registration information of the design end can comprise basic information, design resource information, design case column information and the like of a design company; the design capability of each design end can be divided according to the registration information of the design end, and the like;

b. the first order management unit comprises a chip design order receiving unit;

c. a design management unit comprising: providing an open source PDK for a design end to use, and receiving layout information and the like which are uploaded by the design end and matched with a chip order;

d. a second fee management unit comprising: a payment function and a collection function; the payment function may be to receive a chip design amount allocated by the platform operation module, and the payment function may be to pay the chip design amount to the design end.

The manufacturing end management module is mainly responsible for interaction with the manufacturing end and mainly comprises:

a. a third information management unit, which comprises registration information for managing the manufacture end, wherein the registration information of the manufacture end can comprise basic information of a manufacture factory, manufacture resource and manufacture capacity information, etc.; the manufacturing capacity of the manufacturing end is divided according to the registration information of the manufacturing end, so that a proper manufacturing end flow sheet can be selected for manufacturing when a chip manufacturing order is received;

b. a second order management unit for receiving chip manufacture orders;

c. a third fee management unit comprising: a payment function and a collection function; the payment function may be to receive a chip design amount allocated by the platform operation module, and the payment function may be to pay the chip design amount to the design end.

The platform operation module is mainly responsible for the operation of the virtual integrated circuit platform, and mainly comprises:

a. and the third order management unit is used for acquiring layout information matched with the chip order from the design end, and sending the chip manufacturing order to the manufacturing end management module and the like.

In some embodiments, the third order management unit may further obtain layout information matched with the chip order from a preset information database, optimize the obtained layout information, and send the chip manufacturing order to the manufacturing end management module, and the like;

b. the analog stream slice unit is mainly used for:

b1, receiving layout information (namely a chip design scheme provided by a design end) which is sent by a third order management unit or a fourth order management unit and is matched with the chip order, and carrying out process function classification on the received layout information;

b2, establishing process flow information and manufacturing information required by each process flow;

b3, simulating a flow sheet;

c. a yield analysis unit, comprising: simulating a test after simulating the tape-out, and calculating the yield;

d. a cost calculation unit comprising: analyzing the process flow of the simulated tape-out, the used equipment and the like, and calculating the tape-out cost and the like;

e. the fourth expense management unit comprises a payment function and a collection function; the payment function can be to receive the payment amount of the demander forwarded by the demander management module, and the payment function is to pay the payment amount of the demander to the design end and the manufacturing end through the design end management module and the manufacturing end management module.

FIG. 6 is a diagram illustrating information interaction among functional units of the virtual integrated circuit platform according to an embodiment of the present invention. Referring to fig. 6, after the first information management unit 611 of the demand management module 61 completes registration, the demand management unit 612 of the demand management module 61 analyzes that the demand of the demand management module a is a chip design and manufacturing demand, and sends the chip demand information to the third order management unit 621 of the platform operation module 62.

The third order management unit 63 generates a chip design order and transmits the chip design order to the first order management unit 631 of the design side management module 63. The first order management unit 631 receives a chip design order. The second information managing unit 632 of the design side managing module 63 selects an appropriate design side. Assuming that the chip design company B is selected as a design end, the chip design company B uploads the design scheme to the design scheme management unit 633 after completing the chip design according to the chip design order. The design management unit 633 transmits the received design to the simulated tape-out unit 622 of the platform operation module 62, and the simulated tape-out unit 622 performs a simulated tape-out operation based on the design. After the tape-out is simulated, the yield analysis unit 623 performs testing and yield analysis on the tape-out result, and the cost calculation unit 624 calculates the tape-out cost by using data analysis.

After calculating the tape-out cost, the third order management unit 621 issues a chip manufacturing order to the manufacturing end management module 64, the second order management unit 641 of the manufacturing end management module 64 receives the chip manufacturing order, and the third information management unit 642 of the manufacturing end management module 64 selects an appropriate manufacturing end for chip manufacturing, for example, a manufacturing factory C can be selected for chip manufacturing. After the manufacturing factory C completes the chip manufacturing, the product is delivered to the customer a.

Then, the first fee management unit 613 of the demand side management module 61 collects the fee and transfers the fee to the fourth fee management unit 625 of the platform operation module 62. The fourth fee management unit 625 interacts with the third fee management unit 643 of the manufacturing-side management module 64 and the second fee management unit 634 of the design-side management module 63, respectively, to complete the fee allocation.

In some implementations, when the manufacturing side does not have a manufacturing license for a partial process, the platform operation module 62 may authorize the manufacturing side with the associated manufacturing license, and the manufacturing side pays a certain authorization fee to the platform operation module 62.

In some embodiments, the virtual integrated circuit platform may further include: and the sealing and measuring end management module is mainly responsible for interaction with the sealing and measuring end. Specifically, the seal terminal management module may send seal indication information to the manufacturing terminal management module after the chip manufacturing order is generated, where the seal indication information is suitable for indicating identification information of the seal terminal.

Correspondingly, the manufacturing end management module is further adapted to send the sealing and testing indication information to the manufacturing end corresponding to the chip manufacturing order, so that the manufactured chip is transported to the indicated sealing and testing end for sealing and testing after the manufacturing of the chip is completed by the manufacturing end corresponding to the chip combination manufacturing order.

An embodiment of the present invention further provides a virtual integrated circuit system, where the virtual integrated circuit system may include: the virtual integrated circuit platform of any of the above embodiments.

In an embodiment of the present invention, the virtual integrated circuit system may further include: and the design end is used for receiving the design order sent by the virtual integrated circuit platform and sending chip design response information to the virtual integrated circuit platform after the chip design is finished.

In an embodiment of the present invention, the virtual integrated circuit system may further include: and the manufacturing end is used for receiving the manufacturing order sent by the virtual integrated circuit platform and sending manufacturing response information to the virtual integrated circuit platform after the chip is manufactured.

In an embodiment of the present invention, the virtual integrated circuit system may further include: and the sealing and testing end is used for sealing and testing the chip manufactured by the manufacturing end.

The scheme of the invention can provide design and manufacture of various processes, such as 55nm, 90nm and the like, for a demand party through the virtual integrated circuit platform, so that tape-out manufacturing can be realized for various chip designs. In addition, the invention is wide in object-oriented range, integrates design resources and manufacturing resources, and meets the specific requirements of numerous small and medium-sized enterprises or laboratories. After the demand side puts forward the demand, the subsequent process, such as chip design or direct manufacturing, can be started according to the demand without waiting for a fixed unified tape-out time.

Each module/unit included in each apparatus and product described in the above embodiments may be a software module/unit, or may also be a hardware module/unit, or may also be a part of a software module/unit and a part of a hardware module/unit. For example, for each device or product applied to or integrated into a chip, each module/unit included in the device or product may be implemented by hardware such as a circuit, or at least a part of the module/unit may be implemented by a software program running on a processor integrated within the chip, and the rest (if any) part of the module/unit may be implemented by hardware such as a circuit; for each device or product applied to or integrated with the chip module, each module/unit included in the device or product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least some of the modules/units may be implemented by using a software program running on a processor integrated within the chip module, and the rest (if any) of the modules/units may be implemented by using hardware such as a circuit; for each device and product applied to or integrated in the terminal, each module/unit included in the device and product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least part of the modules/units may be implemented by using a software program running on a processor integrated in the terminal, and the rest (if any) part of the modules/units may be implemented by using hardware such as a circuit.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for controlling a virtual integrated circuit platform, comprising:

when chip demand information sent by a demand party is received, generating a chip design order based on the chip demand information; the chip requirement information includes: requirement type indication information and chip related information; the requirement type indication information is used for indicating the requirement type of a requirement party, and the requirement type comprises at least one of the following: chip design requirements and chip manufacturing requirements;

identifying characteristic information in the chip design order to obtain layout information matched with the chip design order;

and when the demand type indicated by the demand type indication information is only the chip design demand, completing the delivery of the layout information matched with the chip design order.

2. The control method of claim 1, wherein the chip-related information comprises: product information of the chip and chip specification information.

3. The control method according to claim 1, wherein the identifying the feature information in the chip design order and generating layout information matched with the chip design order comprises:

and when the layout information which is completely matched with the chip order does not exist in the preset layout information base, searching the layout information of which the matching degree with the chip design order is greater than a preset matching degree threshold value in the preset layout information base, and obtaining the layout information matched with the chip design order based on a searching result.

4. The control method according to claim 3, wherein the searching for the layout information having a matching degree with the chip design order that is greater than a preset matching degree threshold in a preset layout information base and obtaining the layout information matching with the chip design order based on the search result comprises:

when layout information with the matching degree with the chip design order being larger than a preset matching degree threshold exists in the preset layout information base, correcting the layout information with the matching degree with the chip design order being larger than the preset matching degree threshold in the preset layout information base, wherein the corrected layout information is used as the layout information matched with the chip design order;

5. The method of claim 4, wherein the design end is a design end that is registered in the virtual integrated circuit platform and meets design capability requirements corresponding to the chip order.

6. The control method according to claim 1, wherein when the demand type indicated by the demand type indication information includes a chip manufacturing demand, the method further includes:

generating a chip manufacturing order based on the obtained layout information, and sending the chip manufacturing order to a corresponding manufacturing end;

and when the manufacturing response information sent by the manufacturing end corresponding to the chip manufacturing order is received, the charging and distribution of the fee of the chip order are completed.

7. The method of claim 6, wherein the manufacturing site is a manufacturing site that is registered in the virtual integrated circuit platform and meets the manufacturing capability requirement corresponding to the chip order.

8. The control method according to claim 6, further comprising:

executing simulation tape-out operation based on the layout information matched with the chip design order and the chip requirement information;

performing yield analysis based on the result of the simulated tape-out operation;

and calculating to obtain the actual tape-out cost based on the yield analysis result so as to be used for collecting and distributing the fee of the chip order.

9. The control method according to claim 8, wherein the performing a simulated tape-out operation based on the layout information matched with the chip design order and the chip requirement information comprises:

determining a process type corresponding to the chip manufacturing order based on the layout information matched with the chip design order and the chip requirement information;

creating corresponding process flow information based on the determined process type;

configuring manufacturing information required by each process flow based on the created process flow information;

based on the manufacturing information required for each process flow, a simulated tape-out operation is performed.

10. The control method according to claim 8, further comprising:

generating quotation information based on the actual tape-out cost obtained by calculation, and sending the generated quotation information to a demand side;

and when receiving a quotation agreement response message of a demand party, sending the chip manufacturing order to a corresponding manufacturing end, wherein the chip manufacturing order comprises a process flow corresponding to the simulation tape-out operation.

11. A virtual integrated circuit platform is characterized by comprising a demander management module and a platform operation module; wherein, demand side management module includes: a demand management unit;

the platform operation module is suitable for generating a chip design order based on the chip demand information when the chip demand information sent by a demand party is received; identifying characteristic information in the chip design order to obtain layout information matched with the chip design order;

12. The virtual integrated circuit platform of claim 11, wherein the platform operations module comprises:

13. The virtual integrated circuit platform according to claim 12, wherein the third order management unit is adapted to, when there is layout information in the preset layout information base whose matching degree with the chip design order is greater than a preset matching degree threshold, modify the layout information in the preset layout information base whose matching degree with the chip design order is greater than the preset matching degree threshold, and the modified layout information is used as the layout information matched with the chip design order; when the preset layout information base does not have layout information of which the matching degree with the chip design order is greater than a preset matching degree threshold value, the chip design order is sent to a corresponding design end, and when chip design response information sent by the corresponding design end is received, the layout information carried in the chip design response information is used as the layout information matched with the chip design order.

14. The virtual integrated circuit platform of claim 12, wherein the virtual integrated circuit platform further comprises: a manufacturing end management module;

15. The virtual integrated circuit platform of claim 14, wherein the platform operations module further comprises:

16. The virtual integrated circuit platform of claim 15, wherein the analog tape-out unit is adapted to determine a process type corresponding to the chip manufacturing order based on layout information matched to the chip design order and the chip requirement information; based on the determined process type, creating corresponding process flow information; configuring manufacturing information required by each process flow based on the created process flow information; and executing the simulation tape-out operation based on the manufacturing information required by each process flow.

17. The virtual integrated circuit platform of claim 15, wherein the platform operations module further comprises:

the demand side management module further comprises: the first fee management unit is suitable for receiving the quotation information sent by the fee management unit, completing fee collection and distribution with a demand party, receiving the quotation agreement response information of the demand party and sending the quotation agreement response information of the demand party to the fourth fee management unit.

18. A virtual integrated circuit system, comprising: the virtual integrated circuit platform of any of claims 11 to 17.

19. The virtual integrated circuit system of claim 18, further comprising: and the design end is used for receiving the design order sent by the virtual integrated circuit platform and sending chip design response information to the virtual integrated circuit platform after the chip design is finished.

20. The virtual integrated circuit system of claim 19, further comprising: and the manufacturing end is used for receiving the manufacturing order sent by the virtual integrated circuit platform and sending manufacturing response information to the virtual integrated circuit platform after the chip is manufactured.