CN115939128A - Transient voltage suppressor - Google Patents
Transient voltage suppressor Download PDFInfo
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- CN115939128A CN115939128A CN202211476598.2A CN202211476598A CN115939128A CN 115939128 A CN115939128 A CN 115939128A CN 202211476598 A CN202211476598 A CN 202211476598A CN 115939128 A CN115939128 A CN 115939128A
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Abstract
The invention discloses a transient voltage suppressor, which comprises a unit component, wherein the unit component comprises a substrate, a first deep well region, a second deep well region, a Zener coupling region, a first injection region and a second injection region; the substrate is provided with a first deep well region and a second deep well region, the first deep well region and the second deep well region are alternately distributed along the surface direction of the substrate, the first deep well region and the second deep well region are of opposite conduction types, and the second deep well region is provided with a Zener coupling region; the first injection region and the second injection region are arranged in the Zener coupling region at intervals; all the first injection regions are electrically connected to form a first working end, and all the second injection regions are electrically connected to form a second working end. The invention adopts a multiple parallel structure to release large current, clamps the voltage at a safe level, can integrate more transistor structures in the same area, effectively increases the current capability, and is suitable for high-power surge protection.
Description
Technical Field
The invention relates to the technical field of integrated circuit protection devices, in particular to a transient voltage suppressor.
Background
A Transient Voltage Suppressor (TVS), which is a commonly used circuit protection device and can be driven by 10 when the TVS is impacted by reverse high energy －12 The s-level speed reduces the impedance between the two electrodes from high to low, absorbs the surge power of several kW, clamps the electric potential of the two electrodes to a preset value, and effectively protects components in the circuit from damage of surge pulse.
In high-power protection applications, the conventional transient voltage suppressor is usually designed by using structures such as vertical diodes and transistors, and realizes high voltage by means of multi-chip serial stacked packaging. For example, in 90V applications, 3 high power devices of 30V are often stacked in series, and in 60V applications, this is often achieved by stacking two devices in series. The advantage of this is that different voltages can be achieved by stacking under the same current capacity, but the transient voltage suppressor of the conventional structure has limited current capacity and low power density, and if a larger current device is required, the area of a single vertical device needs to be increased, thereby increasing the cost on one hand and affecting the circuit board layout on the other hand.
Disclosure of Invention
The invention aims to solve the technical problems and provide a transient voltage suppressor which is an improvement on the prior art and solves the problems that the transient voltage suppressor in the prior art adopts a multi-chip vertical device series stacked structure, the through-current capacity is limited and the power density is low.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a transient voltage suppressor comprising a cell structure comprising a substrate, a first deep well region, a second deep well region, a zener coupling region, a first implant region, and a second implant region;
the substrate is provided with a first deep well region and a second deep well region, the first deep well region and the second deep well region are alternately distributed along the surface direction of the substrate, the first deep well region and the second deep well region are of opposite conduction types, and a Zener coupling region is arranged in the second deep well region;
the first injection region and the second injection region are arranged in the Zener coupling region at intervals;
all the first injection regions are electrically connected to form a first working end, and all the second injection regions are electrically connected to form a second working end.
Furthermore, when ion implantation is carried out in the Zener coupling area, the ion implantation energy is 60-140 keV, and a sacrificial oxide layer with the thickness of 360-420 angstroms is arranged between the Zener coupling area and the sacrificial oxide layer.
Furthermore, the ion implantation inclination angle of the Zener coupling area is 8-12 degrees.
Further, the first deep well region and the second deep well region are grown on the substrate.
Further, the zener coupling region and the second deep well region are of opposite conductivity types.
Further, the first implantation region and the second implantation region are respectively one of a P + implantation region and an N + implantation region.
Further, the first implantation region and the second implantation region are the same type of implantation region.
Further, the first and second implanted regions are of opposite conductivity type to the zener coupling region.
Furthermore, all the first implantation regions and all the second implantation regions are respectively connected through different metal interconnection lines.
Further, the conductivity types include a P type and an N type, the first deep well region is a P type deep well region, and the second deep well region is an N type deep well region; or the first deep well region is an N-type deep well region, and the second deep well region is a P-type deep well region.
The transient voltage suppressor further comprises a plurality of unit components, wherein the unit components are sequentially connected in series, a first working end of the first unit component forms a first working electrode of the transient voltage suppressor, a second working end of the previous unit component is electrically connected with a first working end of the next unit component, and a second working end of the last unit component forms a second working electrode of the transient voltage suppressor.
Compared with the prior art, the invention has the advantages that:
the transient voltage suppressor disclosed by the invention adopts a multiple parallel structure and can release large current, a transistor structure formed by combining the first injection region, the Zener coupling region and the second injection region can start working when encountering external static electricity or surge, so that the voltage is clamped at a safe level, more transistor structures can be integrated in the same area, the current capability is effectively increased, and the unit components are stacked in series, so that the function of single-chip high voltage can be realized, and the transient voltage suppressor is suitable for high-power surge protection.
Drawings
FIG. 1 is a cross-sectional view of a unit cell of the transient voltage suppressor of the present invention;
fig. 2 is a schematic diagram of a plurality of cell members stacked in series of the transient voltage suppressor of the present invention.
In the figure:
the device comprises a substrate 1, a first deep well region 2, a second deep well region 3, a Zener coupling region 4, a first injection region 5, a second injection region 6, a first working end 7 and a second working end 8.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a transient voltage suppressor which is compact in structure, adopts a parallel packaging structure, can effectively increase the current capacity, can realize the function of single-chip high voltage, and is suitable for high-power surge protection.
Example one
As shown in fig. 1, a transient voltage suppressor includes a cell structure, which may include only one cell structure or a plurality of cell structures, the cell structure including a substrate 1, a first deep well region 2, a second deep well region 3, a zener coupling region 4, a first implantation region 5 and a second implantation region 6;
the substrate 1 is provided with a first deep well region 2 and a second deep well region 3, the substrate 1 is in a flat plate shape, the first deep well region 2 and the second deep well region 3 are arranged along the upper surface of the substrate 1, and the first deep well region 2 and the second deep well region 3 are alternately distributed on the upper surface of the substrate 1 along the surface direction of the substrate 1, the first deep well region 2 and the second deep well region 3 are grown on the substrate 1, and the first deep well region 2 and the second deep well region 3 are in direct contact with the substrate 1, that is, the first deep well region 2, the second deep well region 3, and the like are sequentially distributed on the upper surface of the substrate 1 along a certain direction, specifically, the first deep well region 2 and the second deep well region 3 are alternately distributed on the upper surface of the substrate 1 along a straight line, a curved line or a circumference, the first deep well region 2 and the second deep well region 3 are of opposite conductivity types, the conductivity types include P type and N type, in this embodiment, the first deep well region 2 is the second deep well region 3 is a P type, and the substrate 1 is a P type;
the second deep well region 3 is provided with a zener coupling region 4, the zener coupling region 4 and the second deep well region 3 are of opposite conductivity type, in this embodiment, the zener coupling region 4 is a P-type zener coupling region, the zener coupling region 4 is manufactured by a special process, the zener coupling region 4 is different from a conventional high-energy zener ion implantation manufacturing method, firstly, it avoids wafer surface defects caused by high-energy ion implantation by low-energy ion implantation (the conventional high-energy ion implantation energy is at least greater than 200keV, while the ion implantation energy for forming the zener coupling region 4 is only 60-140 keV, preferably 100keV, and is separated by a sacrificial oxide layer with a thickness of 360-420 angstroms, preferably a sacrificial oxide layer with a thickness of 400 angstroms), on the other hand, the ion implantation inclination angle during forming the zener coupling region 4 is controlled at an angle of 8-12 degrees, preferably 10 degrees, the ion implantation energy and the ion implantation inclination angle are precisely controlled so that the concentration distribution of implanted ions is compatible with the conventional P well or N well region, after subsequent annealing process of the P well or N well region 4, the zener coupling region 4 has the advantages of low leakage, uniform current equalizing coupling region 4 is embedded in the second deep well region 3, and the zener coupling region is flush with the surface of the second deep well region 3;
the first implantation region 5 and the second implantation region 6 are arranged in the zener coupling region 4 at intervals, specifically, the first implantation region 5 and the second implantation region 6 are embedded in the zener coupling region 4, the first implantation region 5 and the second implantation region 6 are flush with the top surface of the zener coupling region 4, in this embodiment, the first implantation region 5 and the second implantation region 6 are of opposite conductivity types to the zener coupling region 4, then the first implantation region 5 and the second implantation region 6 are both N + implantation regions, and the first implantation region 5, the zener coupling region 4 and the second implantation region 6 form an NPN transistor structure in combination;
all the first injection regions 5 in the unit component are electrically connected to form a first working end 7, that is, the first injection regions 5 are electrically connected to a same potential, all the second injection regions 6 in the unit component are electrically connected to form a second working end 8, that is, the second injection regions 6 are electrically connected to a same potential, specifically, all the first injection regions 5 are electrically connected through metal interconnection wires, all the second injection regions 6 are electrically connected through another set of metal interconnection wires, the upper surfaces of the first injection regions 5 and the second injection regions 6 are covered with a dielectric layer (not shown in the figure), the material of the dielectric layer can be silicon dioxide, doped or undoped silicon glass, etc., the forming method can be chemical vapor deposition, contact holes are formed on the dielectric layer through processes of photoetching, etching, etc., and each contact hole respectively exposes the first injection regions 5 and the second injection regions 6, and depositing a metal material on the dielectric layer, filling the metal material in the contact holes, and then performing photoetching and etching to obtain metal interconnection wires, wherein the metal material can comprise one or more of Ag, au, cu, pd, pt, cr, mo, ti, ta, W and Al, the metal interconnection wires are respectively and electrically connected with the first injection region 5 and the second injection region 6 through the contact holes, when the transient voltage suppressor only comprises one unit component, the first working end 7 is led out to form a working electrode of the transient voltage suppressor, the second working end 8 is led out to form the other working electrode of the transient voltage suppressor, and when the transient voltage suppressor is used, the first working end 7 can be an anode, the second working end 8 can be a cathode, the first working end 7 can also be a cathode, and the second working end 8 can be an anode, namely the anode and the cathode of the transient voltage suppressor can be interchanged.
In the present embodiment, since all the first injection regions 5 are electrically connected to form the first working end 7, and all the second injection regions 6 are electrically connected to form the second working end 8, that is, all the NPN transistor structures formed by the combination of the first injection regions 5, the zener coupling region 4, and the second injection regions 6 are connected in parallel, and the first working end 7 is an anode, and the second working end 8 is a cathode, for explanation, when an external electrostatic ESD or surge signal enters the anode of the transient voltage suppressor, the first injection regions 5 and the zener coupling region 4 will break down, and when the junction voltage of the zener coupling region 4 and the second injection regions 6 reaches 0.7V, the NPN transistor structure will start to operate, release a large current, clamp the voltage, and the smaller the process line width is, more NPN transistor structures can be integrated in the same area, and thus, a vertical product with the same number of chips can have a higher current capability than a conventional device, and thus, the overall power density is improved.
Example two
As shown in fig. 1, the difference from the first embodiment is that the substrate 1 in the unit component is an N-type substrate, the first deep well region 2 is an N-type deep well, the second deep well region 3 is a P-type deep well, the zener coupling region 4 is an N-type zener coupling region, the first implantation region 5 and the second implantation region 6 are both P + implantation regions, in this embodiment, the first working end 7 and the second working end 8 of the unit component respectively constitute an anode and a cathode of the transient voltage suppressor, and the anode and the cathode of the transient voltage suppressor can be interchanged when in use.
EXAMPLE III
As shown in fig. 1, the difference from the first embodiment is that the substrate 1 in the unit component is a P-type substrate, the first deep well region 2 is a P-type deep well, the second deep well region 3 is an N-type deep well, the zener coupling region 4 is a P-type zener coupling region, the first implantation region 5 is an N + implantation region, and the second implantation region 6 is a P + implantation region, in this embodiment, the first working end 7 of the unit component constitutes an anode of the transient voltage suppressor, the second working end 8 of the unit component constitutes a cathode of the transient voltage suppressor, and the anode and the cathode of the transient voltage suppressor are not interchangeable when the transient voltage suppressor is used, and the transient voltage suppressor is only a unidirectional device.
Example four
As shown in fig. 2, the tvs includes a plurality of unit members, the unit members are sequentially connected in series, the first working terminal 7 of the first unit member forms a first tvs working electrode, the second working terminal 8 of the previous unit member is electrically connected to the first working terminal 7 of the next unit member, and the second working terminal 8 of the last unit member forms a second tvs working electrode, the first working electrode and the second working electrode are an anode and a cathode, the anode and the cathode of the tvs are interchangeable when the unit members according to the first and second embodiments are used, and the anode and the cathode of the tvs are not interchangeable when the unit members according to the third embodiment are used and are only unidirectional devices.
The second working end 8 of the previous unit element is electrically connected to the first working end 7 of the next unit element, that is, all the second injection regions 6 in the previous unit element and all the first injection regions 5 in the next unit element are electrically connected together, the second working end 8 of the previous unit element and the first working end 7 of the next unit element are connected to the same potential, so that the transistor structures in each cell group are connected in parallel and then connected in series with the next cell group, the second working end 8 of the previous unit element and the first working end 7 of the next unit element are defined for convenience of description, and specifically, all the second injection regions 6 in the previous unit element and all the first injection regions 5 in the next unit element are connected through metal interconnection lines.
Different unit components share the same substrate and are integrated together, the first deep well region 2 and the second deep well region 3 in each unit component are alternately distributed on the upper surface of the substrate 1 along a straight line, and the different unit components are distributed at intervals in parallel.
The transient voltage suppressor is formed by series-parallel connection of a plurality of transistor structures through a high-voltage isolation structure, is suitable for high-power surge protection, has a plurality of transistor structures connected in parallel in unit components, can release large current, clamps voltage, and then the unit components are stacked in series, provide sufficient withstand voltage, and can realize the function of single high voltage.
The above is only a preferred embodiment of the present invention, and it should be noted that the above preferred embodiment should not be considered as limiting the present invention, and the protection scope of the present invention should be subject to the scope defined by the claims. It will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the spirit and scope of the invention, and should be considered to be within the scope of the invention.
Claims (10)
1. A transient voltage suppressor, comprising a cell structure comprising a substrate (1), a first deep well region (2), a second deep well region (3), a zener coupling region (4), a first implant region (5) and a second implant region (6);
the substrate (1) is provided with first deep well regions (2) and second deep well regions (3), the first deep well regions (2) and the second deep well regions (3) are alternately distributed along the surface direction of the substrate (1), the first deep well regions (2) and the second deep well regions (3) are of opposite conduction types, and Zener coupling regions (4) are arranged in the second deep well regions (3);
a first injection region (5) and a second injection region (6) are arranged in the Zener coupling region (4) at intervals;
all the first implantation regions (5) are electrically connected to form a first working end (7), and all the second implantation regions (6) are electrically connected to form a second working end (8).
2. The transient voltage suppressor according to claim 1, wherein said zener coupling region (4) is characterized by an ion implantation energy of 60-140 keV and a sacrificial oxide layer with a thickness of 360-420 angstroms.
3. The transient voltage suppressor according to claim 2, wherein the zener coupling region (4) has an ion implantation tilt angle of 8 to 12 degrees.
4. The transient voltage suppressor according to claim 1, characterized in that the first deep well region (2) and the second deep well region (3) are grown on the substrate (1).
5. The transient voltage suppressor according to claim 1, characterized in that the zener coupling region (4) and the second deep well region (3) are of opposite conductivity type.
6. The transient voltage suppressor according to claim 1, characterized in that said first (5) and second (6) implanted regions are one of a P + implanted region and an N + implanted region, respectively.
7. The transient voltage suppressor of claim 6, characterized in that the first implant region (5) and the second implant region (6) are the same type of implant region.
8. The transient voltage suppressor according to claim 6, characterized in that the first (5) and second (6) implanted regions are of opposite conductivity type to the zener coupling region (4).
9. The transient voltage suppressor according to claim 1, characterized in that all first implanted regions (5) are connected to all second implanted regions (6) by different metal interconnects, respectively.
10. The transient voltage suppressor of claim 1, wherein said conductivity types comprise P-type and N-type, said first deep well region (2) being a P-type deep well region, said second deep well region (3) being an N-type deep well region; or the first deep well region (2) is an N-type deep well region, and the second deep well region (3) is a P-type deep well region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211476598.2A CN115939128A (en) | 2022-11-23 | 2022-11-23 | Transient voltage suppressor |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211476598.2A CN115939128A (en) | 2022-11-23 | 2022-11-23 | Transient voltage suppressor |
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| Publication Number | Publication Date |
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| CN115939128A true CN115939128A (en) | 2023-04-07 |
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| CN202211476598.2A Pending CN115939128A (en) | 2022-11-23 | 2022-11-23 | Transient voltage suppressor |
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