CN115939094A - Semiconductor device, MIM capacitor device manufacturing method, and semiconductor device - Google Patents

Abstract

The invention discloses a semiconductor device, a manufacturing method of an MIM capacitor and the semiconductor device, wherein the manufacturing method of the semiconductor device comprises the following steps: providing a semiconductor substrate; forming a plurality of amorphous dielectric layers on a semiconductor substrate; removing at least one amorphous medium layer in the multiple amorphous medium layers in at least one preset area to form at least one removing space, wherein the corresponding amorphous medium layers are distributed on the upper surface and the lower surface of the removing space along the height direction of the semiconductor substrate, and the exposed surface of the corresponding amorphous medium layer through the removing space is an amorphous surface; and forming a metal layer in the removing space. The manufacturing method of the semiconductor device can reduce the surface roughness of the metal layer and the dielectric layer, can reduce the surface roughness of the metal pole plate and the dielectric layer for the MIM capacitor, effectively improves the TDDB characteristic of the capacitor device, and further improves the performance of the semiconductor device.

Description

Semiconductor device, MIM capacitor device manufacturing method, and semiconductor device

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor device, a manufacturing method of an MIM capacitor and the semiconductor device.

Background

In the application process of integrated circuits, the performance of various devices is affected by the roughness between the materials of each layer, and in order to reduce the roughness between the materials of each layer, the devices are generally prepared in a stacking manner.

In practical operation, the inventors of the present application found that, in the current semiconductor device manufacturing scheme, in the stacking process of the metal layer and the dielectric layer, since the metal layer is a crystalline substance in the manufacturing process, the roughness of the surface of the metal layer is high due to metal crystallization, which affects the performance of the semiconductor device.

Disclosure of Invention

The invention mainly solves the technical problems that: the semiconductor device and the manufacturing method of the MIM capacitor device are provided, which can reduce the surface roughness of a metal layer and a Dielectric layer, improve the TDDB (Time Dependent Dielectric Breakdown) characteristic of the capacitor device, and further improve the performance of the semiconductor device.

In order to solve the technical problem, the present application adopts a technical scheme that: provided is a method for manufacturing a semiconductor device, including: providing a semiconductor substrate; forming a plurality of amorphous dielectric layers on the semiconductor substrate; removing at least one amorphous dielectric layer in the multiple amorphous dielectric layers in at least one preset area to form at least one removing space, wherein the corresponding amorphous dielectric layers are distributed on the upper surface and/or the lower surface of the removing space along the height direction of the semiconductor substrate; and forming a metal layer in the removing space.

In order to solve the above technical problem, another technical solution adopted by the present application is: providing a manufacturing method of an MIM capacitor device; the method comprises the following steps: providing a semiconductor substrate; forming a first amorphous dielectric layer, a second amorphous dielectric layer, a third amorphous dielectric layer, a fourth amorphous dielectric layer and a fifth amorphous dielectric layer on the semiconductor substrate; removing the second amorphous medium layer and the fourth amorphous medium layer in at least one preset region to form a first removal space and a second removal space, wherein the first amorphous medium layer and the third amorphous medium layer are distributed on the upper surface and the lower surface of the first removal space correspondingly, and the third amorphous medium layer and the fifth amorphous medium layer are distributed on the upper surface and the lower surface of the second removal space correspondingly along the height direction of the semiconductor substrate; the upper surface of the first amorphous dielectric layer and the lower surface of the third amorphous dielectric layer are exposed through the first removing space and are respectively amorphous surfaces; the upper surface of the third amorphous dielectric layer and the lower surface of the fifth amorphous dielectric layer are exposed through the second removing space and are respectively amorphous surfaces; and forming a first metal layer in the first removing space and a second metal layer in the second removing space, wherein the first metal layer, the third amorphous dielectric layer and the second metal layer form a MIM capacitor device.

In an embodiment of the present application, the second amorphous dielectric layer and the fourth amorphous dielectric layer are made of different materials from the first amorphous dielectric layer, the third amorphous dielectric layer, and the fifth amorphous dielectric layer; and/or for at least one etching process, the etching selection ratio of the second amorphous dielectric layer to the fourth amorphous dielectric layer is larger than that of the first amorphous dielectric layer, the third amorphous dielectric layer and the fifth amorphous dielectric layer.

In an embodiment of the present application, the second amorphous dielectric layer and the fourth amorphous dielectric layer are made of the same material, and the first amorphous dielectric layer, the third amorphous dielectric layer and the fifth amorphous dielectric layer are made of the same material.

In an embodiment of the application, the removing the second and fourth amorphous dielectric layers in the predetermined region to form a first removed space and a second removed space includes: forming an opening in a preset area of the MIM capacitor device, wherein the opening at least exposes the side surfaces of the second amorphous dielectric layer, the third amorphous dielectric layer, the fourth amorphous dielectric layer and the fifth amorphous dielectric layer in the preset area of the MIM capacitor device; selecting at least one etching process to etch the second amorphous dielectric layer and the fourth amorphous dielectric layer, wherein the etching selection ratio of the at least one etching process to the second amorphous dielectric layer and the fourth amorphous dielectric layer is greater than that of the first amorphous dielectric layer, the third amorphous dielectric layer and the fifth amorphous dielectric layer, so that the first amorphous dielectric layer, the third amorphous dielectric layer and the fifth amorphous dielectric layer are reserved in the etching process, and the first removal space and the second removal space are formed.

In an embodiment of the application, the forming a first metal layer in the first removing space and a second metal layer in the second removing space includes: depositing a metal material on the first removal space, the second removal space, the opening and the fifth amorphous dielectric layer by an atomic layer deposition method or a physical vapor deposition method; removing the redundant metal material on the fifth amorphous dielectric layer; and forming an upper plate and a lower plate of the MIM capacitor device.

In an embodiment of the present application, a sixth dielectric layer is formed on the upper plate and the lower plate, and a contact plug of the upper plate and the lower plate is formed on the sixth dielectric layer.

In an embodiment of the present application, the first amorphous dielectric layer is used as a barrier layer, and the thickness thereof is between 40 nm and 100 nm; the third amorphous dielectric layer is used as a dielectric layer of the MIM capacitor device; the fifth amorphous medium layer is used as a hard mask layer, and the thickness of the fifth amorphous medium layer is 35-100 nm.

In an embodiment of the present application, the semiconductor base material includes a substrate and a device structure, an isolation structure, a dielectric layer, or a wiring structure disposed in or on the substrate.

In order to solve the above technical problem, the present application adopts another technical solution: provided is a semiconductor device including: a semiconductor substrate; a multilayer amorphous dielectric layer disposed on the semiconductor substrate; and the metal layer is formed between two adjacent corresponding amorphous medium layers, wherein the surfaces of the two adjacent corresponding amorphous medium layers facing the metal layer are amorphous surfaces.

In an embodiment of the present application, the multiple amorphous dielectric layers include a first amorphous dielectric layer, a third amorphous dielectric layer, and a fifth amorphous dielectric layer, which are sequentially disposed; the at least one metal layer comprises a first metal layer and a second metal layer, wherein the first metal layer is positioned between the first amorphous dielectric layer and the third amorphous dielectric layer, and the surfaces of the first amorphous dielectric layer and the third amorphous dielectric layer facing the first metal layer are amorphous surfaces; the second metal layer is positioned between the third amorphous medium layer and the fifth amorphous medium layer, and the surfaces of the third amorphous medium layer and the fifth amorphous medium layer facing the second metal layer are amorphous surfaces.

In contrast to the prior art, the present application provides a method for manufacturing a semiconductor device, including: providing a semiconductor substrate; depositing a plurality of amorphous dielectric layers on the semiconductor substrate; removing at least one amorphous medium layer in a plurality of amorphous medium layers in at least one preset area to form at least one removing space, wherein the corresponding amorphous medium layers are distributed on the upper surface or the lower surface of the removing space along the height direction of the semiconductor substrate, and the surface of the corresponding amorphous medium layer exposed through the removing space is an amorphous surface; and forming a metal layer in the removing space. According to the method, a plurality of amorphous medium layers are deposited firstly, and then some amorphous medium layers are etched to form a removing space, and the amorphous medium layers are distributed up and down in the removing space, so that the surface of a metal layer formed subsequently can be flat on the surface of the amorphous medium layer in the metal layer depositing process, and the surface roughness of the metal layer and the medium layers is further reduced. For the MIM capacitor, the surface roughness of the metal polar plate and the dielectric layer can be reduced, the TDDB characteristic of the capacitor device is improved, and the performance of the semiconductor device is further improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

FIG. 1 is a schematic flow chart diagram illustrating one embodiment of a method for fabricating a semiconductor device according to the present application;

FIG. 2 is a schematic view of an embodiment of a semiconductor substrate according to the present application;

FIG. 3 is a schematic diagram of a structure for forming a multi-layer amorphous dielectric layer on a semiconductor substrate according to the present application;

FIG. 4 is a schematic structural diagram illustrating the formation of an etched region in a multi-layer amorphous dielectric layer according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a structure for forming a removal space in a multi-layer amorphous dielectric layer according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram illustrating a structure of forming a metal layer in a removal space according to an embodiment of the present application;

fig. 7 is a schematic flow chart diagram illustrating one embodiment of a method for fabricating a MIM capacitor device according to the present application;

FIG. 8 is a schematic diagram of a semiconductor substrate with multiple amorphous dielectric layers deposited thereon according to one embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a structure for forming an opening in a predetermined area according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of forming a first removing space and a second removing space according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a structure for forming a first metal layer and a second metal layer according to an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of a stepped structure provided in one embodiment of the present application;

fig. 13 is a schematic diagram of a MIM capacitor device according to an embodiment of the present application;

fig. 14 is a schematic top view of a MIM capacitor device according to an embodiment of the present application.

Description of reference numerals:

a semiconductor substrate 100; a preset area 110; an opening 120; a first amorphous dielectric layer 200; a second amorphous dielectric layer 300; a third amorphous dielectric layer 400; a fourth amorphous dielectric layer 500; a fifth amorphous dielectric layer 600; a first removal space 310; a second removal space 510; a first metal layer 320; a second metal layer 520; a sixth dielectric layer 700; a first conductive plug 820; a second conductive plug 810; a first connection end 920; a second connection end 910; an MIM capacitor inner region 10; MIM capacitor outer region 11.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms "first", "second" and "third" in this application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or as implying a number of indicated technical features. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless explicitly specifically limited otherwise. In the embodiment of the present application, all the directional indicators (such as upper, lower, left, right, front, and rear … …) are used only to explain the relative positional relationship between the components, the movement, and the like in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.

The present application will be described in detail with reference to the accompanying drawings and examples.

In the current semiconductor device manufacturing process, a metal layer and a dielectric layer of a semiconductor device are usually manufactured in a sequential deposition mode, so that a stacked structure of the metal layer and the dielectric layer is formed, and in the manufacturing process of the stacked structure, the metal layer has higher interface roughness due to metal crystallization, and the roughness of other dielectric layers above the metal layer is correspondingly influenced; because the interface roughness of the metal layer is high, interface traps are easy to generate on the interface of the metal layer/the medium layer, so that electrons are trapped at the interface, and the local electric field intensity at the interface is greatly improved. The MIM (Metal-Insulator-Metal) capacitor device comprises a Metal lower electrode plate, a middle dielectric layer and a Metal upper electrode plate, and the MIM capacitor is formed by sequentially depositing, because the interface roughness of a Metal layer is high, the phenomenon can cause the degradation of molecules of the dielectric layer at the positions of the Metal layer and the dielectric layer, a destructive conductive channel is formed, and the breakdown of the capacitor occurs. The performance of the semiconductor device with high requirements on the surface roughness of the metal layer and the dielectric layer is also affected.

Therefore, a method for manufacturing a semiconductor device is provided, wherein a removing space is formed by forming a stack of amorphous dielectric layers and then removing some of the amorphous dielectric layers, and since the amorphous dielectric layers distributed above and/or below the removing space, the surface of a metal layer formed subsequently can be flattened by the surface of the amorphous dielectric layer in the process of depositing the metal layer, thereby reducing the surface roughness of the metal layer and the dielectric layers. For the MIM capacitor, the surface roughness of the metal polar plate and the dielectric layer can be reduced, the TDDB characteristic of the capacitor is improved, and the performance of the semiconductor device is improved.

Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. The manufacturing method of the semiconductor device is generally used in the manufacturing process of the semiconductor device with high requirements on the roughness of the interface of each layer of material, the roughness of the interface of the metal layer and the interface of the dielectric layer can be reduced, and for the MIM capacitor, the TDDB characteristic of the capacitor device can be improved, so that the performance of the semiconductor device is improved.

As shown in fig. 1, a method for manufacturing a semiconductor device of the present application includes:

s11, providing a semiconductor substrate.

Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment of the semiconductor base material of the present application, and it can be understood that, as shown in fig. 2, the semiconductor base material 100 includes a substrate. The substrate may be a silicon substrate, a germanium substrate, an SOI (Semiconductor On Insulator) substrate, or any other substrate. It will be understood by those skilled in the art that the substrate is not subject to any limitations, but may be selected according to the actual application.

In other embodiments, the semiconductor substrate 100 may further include a device structure (e.g., a transistor), an isolation structure, a dielectric layer, or a wiring structure (not shown) disposed in or on the substrate, and those skilled in the art will understand that the device structure, the isolation structure, the dielectric layer, or the wiring structure are not limited to any particular structure, but may be selected according to practical applications.

And S12, forming a plurality of amorphous dielectric layers on the semiconductor substrate.

Referring to fig. 3, fig. 3 is a schematic structural diagram illustrating a multi-layer amorphous dielectric layer formed on a semiconductor substrate according to an embodiment of the present disclosure. As shown in fig. 3, the semiconductor device includes a semiconductor substrate 100 and at least two amorphous dielectric layers deposited on the semiconductor substrate 100. The at least two amorphous dielectric layers may be three, five, ten, etc., and may be set according to an actual semiconductor device.

Specifically, in this embodiment, three amorphous dielectric layers are taken as an example for description, and the first amorphous dielectric layer 200, the second amorphous dielectric layer 300, and the third amorphous dielectric layer 400 are sequentially deposited on the semiconductor substrate 100, because each dielectric layer is an amorphous dielectric layer, and there is no metal crystal in the metal growth process between the amorphous dielectric layers, the surface of the amorphous dielectric layer is relatively flat.

And S13, removing at least one amorphous dielectric layer in the plurality of amorphous dielectric layers in at least one preset area to form at least one removing space.

And the upper surface and/or the lower surface of the removing space are/is distributed with corresponding amorphous medium layers along the height direction of the semiconductor substrate, and the surfaces of the corresponding amorphous medium layers exposed by the removing space are amorphous surfaces.

Referring to fig. 4 and 5, fig. 4 is a schematic structural diagram illustrating a formation of an etched region in a multi-layer amorphous dielectric layer according to an embodiment of the present disclosure, and fig. 5 is a schematic structural diagram illustrating a formation of a removal space in the multi-layer amorphous dielectric layer according to an embodiment of the present disclosure. In this embodiment, three amorphous dielectric layers are taken as an example for description, and the at least one removed amorphous dielectric layer is, for example, a sacrificial dielectric layer, as shown in fig. 4, an opening 120 is formed in the semiconductor device, and at least a sidewall of the sacrificial dielectric layer is exposed by the opening 120. A preset area 110 is selected in the height direction of the semiconductor device, the preset area 110 is exposed and developed, and then the preset area 110 is etched to form an opening 120. Then, as shown in fig. 5, the second amorphous dielectric layer is used as a sacrificial dielectric layer, and the sacrificial dielectric layer is removed from the sidewall exposed by the opening 120, that is, the second amorphous dielectric layer 300 is etched away in the predetermined region 110, so as to form a first removal space 310 between the first amorphous dielectric layer 200 and the third amorphous dielectric layer 400; the etching selection ratio of the second amorphous dielectric layer is larger than that of the first amorphous dielectric layer and that of the third amorphous dielectric layer.

And S14, forming a metal layer in the removing space.

Referring to fig. 6, fig. 6 is a schematic structural diagram illustrating a metal layer formed in a removal space according to an embodiment of the present disclosure. As shown in fig. 6, after the first removal space 310 is formed, a metal material is deposited on the removal space 310 by an atomic layer deposition method or a physical vapor deposition method, so that a first metal layer 320 is formed in the removal space, thereby forming a semiconductor device.

In the above technical solution, a semiconductor device manufacturing method is provided, which includes: providing a semiconductor substrate 100; depositing a plurality of amorphous dielectric layers on the semiconductor substrate 100; removing at least one amorphous dielectric layer in the plurality of amorphous dielectric layers in a preset area to form at least one removing space, wherein the corresponding amorphous dielectric layers are distributed on the upper surface and/or the lower surface of the removing space along the height direction of the semiconductor substrate 100; and forming a metal layer in the removing space. According to the method, the plurality of amorphous dielectric layers are deposited firstly, and then some amorphous dielectric layers are etched to form the removing space, and the amorphous dielectric layers are distributed on the upper surface and/or the lower surface of the removing space, so that the surface of the metal layer can be smooth due to the amorphous surface in the metal layer depositing process, the surface roughness of the metal layer and the amorphous dielectric layers is reduced, and the performance of the semiconductor device is improved.

Referring to fig. 7, fig. 7 is a schematic flow chart illustrating a method for fabricating a MIM capacitor device according to an embodiment of the present invention. In this embodiment, the semiconductor device is an MIM capacitor, and the manufacturing method of the MIM capacitor according to the present application can reduce the interface roughness of the metal plate and the dielectric layer, improve the TDDB characteristic of the capacitor, and further improve the performance of the semiconductor device.

S21, providing a semiconductor substrate.

Referring to fig. 2, the description thereof is omitted.

S22, forming a first amorphous medium layer, a second amorphous medium layer, a third amorphous medium layer, a fourth amorphous medium layer and a fifth amorphous medium layer on the semiconductor substrate;

the material of the second amorphous dielectric layer 300 is different from the material of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600; the material of the fourth amorphous dielectric layer 500 is different from the material of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600, the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 may be made of the same material, and the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600 may be made of the same material. For at least one etching process, the etching selection ratio of the second amorphous dielectric layer 300 to the fourth amorphous dielectric layer 500 is greater than the etching selection ratio of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600, so that the first amorphous dielectric layer 200, the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600 can be reserved when the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 are etched.

Referring to fig. 8, fig. 8 is a schematic structural diagram illustrating a semiconductor substrate with a plurality of amorphous dielectric layers deposited thereon according to an embodiment of the present disclosure. As shown in fig. 8, the semiconductor device includes a semiconductor substrate 100, and a first amorphous dielectric layer 200, a second amorphous dielectric layer 300, a third amorphous dielectric layer 400, a fourth amorphous dielectric layer 500, and a fifth amorphous dielectric layer 600 deposited on the semiconductor substrate 100, because each of the dielectric layers is an amorphous dielectric layer, no metal crystallization occurs during deposition, and therefore, the interface of the amorphous dielectric layers is relatively flat, so that the metal layer formed subsequently is relatively flat, that is, the surface roughness of the metal layer is reduced.

Specifically, in the present embodiment, the semiconductor substrate 100 includes a substrate, wherein five layers of amorphous dielectric layers are taken as an example for illustration; in the prior art, a first amorphous dielectric layer 200, a second amorphous dielectric layer 300, a third amorphous dielectric layer 400, a fourth amorphous dielectric layer 500, and a fifth amorphous dielectric layer 600 are sequentially formed on a semiconductor substrate 100. For example, the amorphous dielectric layers are sequentially deposited by a CVD process, which is called Chemical Vapor Deposition for short.

In other embodiments, the semiconductor substrate 100 may further include a device structure (e.g., a transistor), an isolation structure, a dielectric layer, a wiring structure, etc. disposed in or on the substrate, and those skilled in the art will understand that the device structure, the isolation structure, the dielectric layer, the wiring structure, etc. are not limited in any way, and may be selected according to practical applications.

The first amorphous dielectric layer 200 serves as a barrier layer for blocking upward diffusion of some materials in the semiconductor substrate 100, such as Cu, and has a thickness of 40-100 nm; the thickness of the third amorphous dielectric layer 400, which is used as a dielectric layer of the MIM capacitor device, is determined according to the capacitance value of the MIM capacitor device, for example, 32nm of the third amorphous dielectric layer 400 corresponds to a 2fF capacitance value, and 130nm of the third amorphous dielectric layer 400 corresponds to a 0.5fF capacitance value; the fifth amorphous dielectric layer 600 is used as a hard mask layer, and the thickness of the fifth amorphous dielectric layer 600 is 35-100nm in order to ensure the subsequent windowing on the fifth amorphous dielectric layer. Since the first metal layer 320 and the second metal layer 520 are required to be manufactured as the upper and lower metal plates of the MIM capacitor at the positions of the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500, and the thickness of the metal plates determines the resistance of the metal plates, the thicknesses of the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 are between 30nm and 100 nm.

In the present embodiment, the material of the second amorphous dielectric layer 300 is different from the material of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600; the material of the fourth amorphous dielectric layer 500 is different from the material of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400, and the fifth amorphous dielectric layer 600. In one embodiment, the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 may be made of the same material, and the first amorphous dielectric layer 200, the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600 may be made of the other same material. In another embodiment, the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 may be made of different materials. For at least one etching process, the etching selection ratio of the second amorphous dielectric layer 300 is greater than the etching selection ratios of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600, and the etching selection ratio of the fourth amorphous dielectric layer 500 is greater than the etching selection ratios of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600, so that the etching selection ratios of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600 can be kept when the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 are etched.

In order to ensure the stability of the process, the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 are usually made of the same material, and the first amorphous dielectric layer 200, the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600 are usually made of the same material.

The material of the amorphous dielectric layer can be silicon dioxide and/or silicon nitride, and can be selected correspondingly according to the manufacturing requirements of the semiconductor device.

And S23, removing the second amorphous medium layer and the fourth amorphous medium layer in at least one preset area to form a first removing space and a second removing space.

Along the height direction of the semiconductor substrate 100, a first amorphous dielectric layer 200 and a third amorphous dielectric layer 400 are distributed above and below the first removing space 310, and a third amorphous dielectric layer 400 and a fifth amorphous dielectric layer 600 are distributed above and below the second removing space 300; the upper surface of the first amorphous dielectric layer 200 and the lower surface of the third amorphous dielectric layer 400 are exposed through the first removal space 310 and are amorphous surfaces, respectively; the upper surface of the third amorphous dielectric layer 400 and the lower surface of the fifth amorphous dielectric layer 600 are exposed through the second removal space 510 and are amorphous surfaces, respectively.

Referring to fig. 9, fig. 9 is a schematic structural diagram of forming an opening in a predetermined area according to an embodiment of the present invention. As shown in fig. 9, an opening 120 is formed in the MIM capacitor device predetermined area 110, and at least sides 600 of the second amorphous dielectric layer 300, the third amorphous dielectric layer 400, the fourth amorphous dielectric layer 500, and the fifth amorphous dielectric layer are exposed through the opening 120.

Referring to fig. 10, fig. 10 is a schematic structural diagram illustrating formation of a first removal space and a second removal space according to an embodiment of the present disclosure. As shown in fig. 10, a first removed space 310 and a second removed space 510 are formed by etching the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 in the MIM capacitor device predetermined area 130 based on fig. 9. For at least one etching process, the etching selection ratio of the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 is greater than the etching selection ratio of the first amorphous dielectric layer 200, the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600, so that when the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 are etched in the etching process, the first amorphous dielectric layer 200, the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600 are remained, and the first removal space 310 and the second removal space 510 are formed.

And S24, forming a first metal layer in the first removing space, and forming a second metal layer in the second removing space, wherein the first metal layer, the third amorphous dielectric layer and the second metal layer form the MIM capacitor device.

Referring to fig. 11, fig. 11 is a schematic structural diagram of forming a first metal layer and a second metal layer according to an embodiment of the present disclosure. As shown in fig. 11, on the basis of fig. 10, a metal material is deposited on the first removal space 310, the second removal space 510, the opening 140 and the fifth amorphous dielectric layer 600 by an atomic layer deposition method or a physical vapor deposition method, the metal material remaining between the first amorphous dielectric layer 200 and the third amorphous dielectric layer 400 is used as the first metal layer 320, and the metal material remaining between the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600 is used as the second metal layer 520; and removing the redundant metal material on the fifth amorphous dielectric layer 600 through an etching process or a planarization process.

Referring to fig. 12, fig. 12 is a schematic structural diagram of a step structure according to an embodiment of the present application.

In an actual operation process, on the basis of fig. 11, an upper plate and a lower plate of the MIM capacitor need to be formed through photolithography and etching processes, where the second metal layer 520 is the upper plate of the MIM capacitor, and the first metal layer 320 is the lower plate of the MIM capacitor; that is, a portion of the fifth amorphous dielectric layer 600, a portion of the metal material in the second removal space 510, a portion of the third amorphous dielectric layer 400, a portion of the metal material in the first removal space 310, and the metal material in the opening 120 are etched to form a stepped structure as shown in fig. 12. The metal material between the first amorphous dielectric layer 200 and the third amorphous dielectric layer 400 is used as the first metal layer 320, and the metal material between the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600 is used as the second metal layer 520; at least a portion of the third amorphous dielectric layer 400 and the first metal layer 320 form a first step, and the fifth amorphous dielectric layer 600, the second metal layer 520, and/or the third amorphous dielectric layer 400 form a second step, which exposes at least a portion of the first step.

Referring to fig. 13, fig. 13 is a schematic diagram of a MIM capacitor device according to an embodiment of the present disclosure. As shown in fig. 13, on the basis of fig. 12, a sixth dielectric layer 700 is formed on the stepped structure, that is, the sixth dielectric layer 700 is formed on the upper plate and the lower plate, wherein a surface of the sixth dielectric layer 700 away from the stepped structure is a planarized surface.

After the MIM capacitor device is manufactured, the surface of the wafer is rugged, so the surface is polished by a CMP process after the sixth dielectric layer 700 is deposited, i.e., planarization is performed, so that the surface of the sixth dielectric layer 700 away from the stepped structure is a planarized surface, and therefore, in order to meet the requirements of the CMP process, the thickness of the sixth dielectric layer 700 is between 3000nm and 5000 nm.

After the sixth dielectric layer 700 is formed, contact plugs of the metal upper plate and the metal lower plate are formed. Specifically, a first through hole and a second through hole (not shown in the figure) are formed on the metal upper plate and the metal lower plate through photoetching and etching processes; conductive substances are filled in the first through hole and the second through hole to form a first conductive plug 820 and a second conductive plug 810, and a first connection end 920 and a second connection end 910 are formed on the surface of the sixth dielectric layer 700 away from the stepped structure, wherein the first connection end 920 is connected to the first metal layer 320 through the first conductive plug 820, and the second connection end 910 is connected to the second metal layer 520 through the second conductive plug 810. The MIM capacitor device is formed with a first metal layer 320, a third amorphous dielectric layer 400, and a second metal layer 520.

In one embodiment, the diameter of the first via and the second via may be 45-150nm, and the height thereof may be set to be 2000-3000nm, depending on the thickness of each amorphous dielectric layer.

Referring to fig. 14, fig. 14 is a schematic top view of an MIM capacitor device according to an embodiment of the present disclosure. As shown in fig. 14, the MIM capacitor device includes an inner MIM capacitor region 10 and an outer MIM capacitor region 11, the inner MIM capacitor region 10 includes a second metal layer 520, a first metal layer 320, and a third amorphous dielectric layer 400 (not shown) between the second metal layer 520 and the first metal layer 320, the second metal layer 520 is an upper plate of the MIM capacitor, the first metal layer 320 is a lower plate of the MIM capacitor to form a capacitor device structure, a second conductive plug 810 in a second via hole on the second metal layer 520 is connected to a second connection terminal 910, and a first conductive plug 820 in a first via hole on the first metal layer 320 is connected to a first connection terminal 920, so that the MIM capacitor device can be connected to an external circuit.

In addition, with continued reference to fig. 14, there may be a plurality of first through holes formed on the first step, that is, there may be a plurality of first through holes formed on the first metal layer 320, and there may be a plurality of corresponding first conductive plugs 820; there may be a plurality of second vias formed on the second step, that is, there may be a plurality of second vias formed on the second metal layer 520, and there may be a plurality of second conductive plugs 810.

In the above technical solution, in the manufacturing method of the MIM capacitor device, a semiconductor substrate 100 is provided, and a first amorphous dielectric layer 200, a second amorphous dielectric layer 300, a third amorphous dielectric layer 400, a fourth amorphous dielectric layer 500, and a fifth amorphous dielectric layer 600 are deposited on the semiconductor substrate 100; removing the second amorphous dielectric layer 300 and the fourth amorphous dielectric layer 500 in a preset area of the MIM capacitor device to form a first removal space 310 and a second removal space 510, wherein the first amorphous dielectric layer 200 and the third amorphous dielectric layer 400 are distributed on the upper surface and the lower surface of the first removal space 310 correspondingly, and the third amorphous dielectric layer 400 and the fifth amorphous dielectric layer 600 are distributed on the upper surface and the lower surface of the second removal space 510 correspondingly; the upper surface of the first amorphous dielectric layer 200 and the lower surface of the third amorphous dielectric layer 400 are exposed through the first removal space 310 and are amorphous surfaces, respectively; the upper surface of the third amorphous dielectric layer 400 and the lower surface of the fifth amorphous dielectric layer 600 are exposed through the second removal space 510 and are amorphous surfaces, respectively; a first metal layer 320 is formed in the first removed space 310 and a second metal layer 520 is formed in the second removed space 510, wherein the first metal layer 320, the third amorphous dielectric layer 400 and the second metal layer 520 form a MIM capacitor device. According to the manufacturing method of the MIM capacitor, the surface roughness of the metal polar plate and the surface roughness of the amorphous dielectric layer can be reduced, so that the TDDB characteristic of the capacitor is improved, and the performance of the semiconductor device is improved.

In the present application, there is provided a semiconductor device including: the semiconductor substrate, form the multi-layer amorphous dielectric layer on the semiconductor substrate, and form at least a metal layer between two adjacent correspondent amorphous dielectric layers; the surfaces of the two adjacent corresponding amorphous dielectric layers facing the metal layer are amorphous surfaces. As shown in fig. 6, the semiconductor device includes a semiconductor substrate 100, and a first amorphous dielectric layer 200, a first metal layer 320, and a third amorphous dielectric layer 400 sequentially formed on the semiconductor substrate 100. Because the surface of the amorphous dielectric layer facing the metal layer is an amorphous surface, the surface of the metal layer can be flattened by the amorphous surface, the surface roughness of the metal layer and the amorphous dielectric layer is reduced, and the performance of the semiconductor device is improved.

In one embodiment, the plurality of amorphous dielectric layers include a first amorphous dielectric layer, a third amorphous dielectric layer and a fifth amorphous dielectric layer formed in sequence; the at least one metal layer includes a first metal layer and a second metal layer. The first metal layer is positioned between the first amorphous medium layer and the third amorphous medium layer, and the surfaces of the first amorphous medium layer and the third amorphous medium layer facing the first metal layer are amorphous surfaces; the second metal layer is positioned between the third amorphous medium layer and the fifth amorphous medium layer, and the surfaces of the third amorphous medium layer and the fifth amorphous medium layer facing the second metal layer are amorphous surfaces.

As shown in fig. 13, the semiconductor device is an MIM capacitor device, which includes a semiconductor substrate 100, and a first amorphous dielectric layer 200, a first metal layer 320, a third amorphous dielectric layer 400, a second metal layer 520, a fifth amorphous dielectric layer 600, and a sixth amorphous dielectric layer 700 sequentially formed on the semiconductor substrate 100; at least part of the third amorphous dielectric layer 400 and the first metal layer 320 form a first step, the fifth amorphous dielectric layer 600, the second metal layer 520 and/or the third amorphous dielectric layer 400 form a second step, at least part of the first step is exposed out of the second step to form a stepped structure, and a sixth dielectric layer 700 is formed on the stepped structure, namely the sixth dielectric layer 700 is formed on the upper plate and the lower plate; the first metal layer 320 is used as a lower electrode plate of the MIM capacitor, and the second metal layer 520 is used as an upper electrode plate of the MIM capacitor; forming a first through hole and a second through hole (not marked in the figure) on the metal upper polar plate and the metal lower polar plate; conductive substances are filled in the first through hole and the second through hole to form a first conductive plug 820 and a second conductive plug 810, and a first connection end 920 and a second connection end 910 are formed on the surface of the sixth dielectric layer 700 away from the stepped structure, wherein the first connection end 920 is connected to the first metal layer 320 through the first conductive plug 820, and the second connection end 910 is connected to the second metal layer 520 through the second conductive plug 810. The first metal layer 320, the third amorphous dielectric layer 400 and the second metal layer 520 form a MIM capacitor device. In the application, the surface of the amorphous dielectric layer is relatively flat, so that the surface of the metal layer formed in the amorphous dielectric layer is also relatively flat, and when the semiconductor device is an MIM capacitor device, the surface roughness of the metal plate and the amorphous dielectric layer is reduced, so that the TDDB characteristic of the capacitor device is improved, and the performance of the MIM capacitor device is further improved.

The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims (11)

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor substrate;

forming a plurality of amorphous dielectric layers on the semiconductor substrate;

removing at least one amorphous medium layer in a plurality of amorphous medium layers in at least one preset area to form at least one removing space, wherein the corresponding amorphous medium layers are distributed on the upper surface and/or the lower surface of the removing space along the height direction of the semiconductor substrate;

and forming a metal layer in the removing space.

2. A method of fabricating a MIM capacitor device, comprising:

providing a semiconductor substrate;

forming a first amorphous medium layer, a second amorphous medium layer, a third amorphous medium layer, a fourth amorphous medium layer and a fifth amorphous medium layer on the semiconductor substrate;

removing the second amorphous medium layer and the fourth amorphous medium layer in at least one preset area to form a first removal space and a second removal space, wherein the first amorphous medium layer and the third amorphous medium layer are distributed on the upper surface and the lower surface of the first removal space correspondingly, and the third amorphous medium layer and the fifth amorphous medium layer are distributed on the upper surface and the lower surface of the second removal space correspondingly along the height direction of the semiconductor substrate; the upper surface of the first amorphous dielectric layer and the lower surface of the third amorphous dielectric layer are exposed through the first removing space and are respectively amorphous surfaces; the upper surface of the third amorphous dielectric layer and the lower surface of the fifth amorphous dielectric layer are exposed through the second removing space and are respectively amorphous surfaces;

and forming a first metal layer in the first removing space and a second metal layer in the second removing space, wherein the first metal layer, the third amorphous dielectric layer and the second metal layer form a MIM capacitor device.

3. The manufacturing method according to claim 2,

the second amorphous medium layer and the fourth amorphous medium layer are made of different materials from the first amorphous medium layer, the third amorphous medium layer and the fifth amorphous medium layer; and/or

For at least one etching process, the etching selection ratio of the second amorphous dielectric layer to the fourth amorphous dielectric layer is greater than the etching selection ratio of the first amorphous dielectric layer, the third amorphous dielectric layer and the fifth amorphous dielectric layer.

4. The manufacturing method according to claim 2,

the second amorphous dielectric layer and the fourth amorphous dielectric layer are made of the same material, and the first amorphous dielectric layer, the third amorphous dielectric layer and the fifth amorphous dielectric layer are made of the same material.

5. The manufacturing method according to claim 2, characterized by comprising:

the removing the second amorphous medium layer and the fourth amorphous medium layer in the preset area to form a first removing space and a second removing space comprises the following steps:

forming an opening in a preset area of the MIM capacitor device, wherein the opening at least exposes the side surfaces of the second amorphous dielectric layer, the third amorphous dielectric layer, the fourth amorphous dielectric layer and the fifth amorphous dielectric layer in the preset area of the MIM capacitor device;

selecting at least one etching process to etch the second amorphous dielectric layer and the fourth amorphous dielectric layer, wherein the etching selection ratio of the at least one etching process to the second amorphous dielectric layer and the fourth amorphous dielectric layer is greater than that of the first amorphous dielectric layer, the third amorphous dielectric layer and the fifth amorphous dielectric layer, so that the first amorphous dielectric layer, the third amorphous dielectric layer and the fifth amorphous dielectric layer are reserved in the etching process, and the first removal space and the second removal space are formed.

6. The manufacturing method according to claim 5,

the forming a first metal layer in the first removal space and a second metal layer in the second removal space includes:

depositing a metal material on the first removal space, the second removal space, the opening and the fifth amorphous dielectric layer by an atomic layer deposition method or a physical vapor deposition method;

removing the redundant metal material on the fifth amorphous dielectric layer;

and forming an upper plate and a lower plate of the MIM capacitor device.

7. The manufacturing method according to claim 6, further comprising:

and forming a sixth medium layer on the upper polar plate and the lower polar plate, and forming contact plugs of the upper polar plate and the lower polar plate in the sixth medium layer.

8. The manufacturing method according to claim 2,

the first amorphous dielectric layer is used as a barrier layer, and the thickness of the first amorphous dielectric layer is 40-100 nm;

the third amorphous dielectric layer is used as a dielectric layer of the MIM capacitor device;

the fifth amorphous medium layer is used as a hard mask layer, and the thickness of the fifth amorphous medium layer is 35-100 nm.

9. The manufacturing method according to claim 2,

the semiconductor base material comprises a substrate and a device structure, an isolation structure, a dielectric layer or a connecting line structure arranged in or on the substrate.

10. A semiconductor device, comprising:

a semiconductor substrate;

a multilayer amorphous dielectric layer disposed on the semiconductor substrate;

and the metal layer is formed between two adjacent corresponding amorphous dielectric layers, wherein the surfaces of the two adjacent corresponding amorphous dielectric layers facing the metal layer are amorphous surfaces.

11. The semiconductor device according to claim 10,

the multilayer amorphous dielectric layer comprises a first amorphous dielectric layer, a third amorphous dielectric layer and a fifth amorphous dielectric layer which are sequentially arranged;

the at least one metal layer comprises a first metal layer and a second metal layer, wherein the first metal layer is positioned between the first amorphous dielectric layer and the third amorphous dielectric layer, and the surfaces of the first amorphous dielectric layer and the third amorphous dielectric layer facing the first metal layer are amorphous surfaces; the second metal layer is positioned between the third amorphous medium layer and the fifth amorphous medium layer, and the surfaces of the third amorphous medium layer and the fifth amorphous medium layer facing the second metal layer are amorphous surfaces.

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