CN115939033A - Manufacturing method of metal bump and flip chip interconnection method - Google Patents
Manufacturing method of metal bump and flip chip interconnection method Download PDFInfo
- Publication number
- CN115939033A CN115939033A CN202310019294.1A CN202310019294A CN115939033A CN 115939033 A CN115939033 A CN 115939033A CN 202310019294 A CN202310019294 A CN 202310019294A CN 115939033 A CN115939033 A CN 115939033A
- Authority
- CN
- China
- Prior art keywords
- seed layer
- layer
- photoresist pattern
- metal bump
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 100
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 87
- 239000002184 metal Substances 0.000 title claims abstract description 87
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 80
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000004070 electrodeposition Methods 0.000 claims abstract description 23
- 238000009713 electroplating Methods 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 9
- 229920001486 SU-8 photoresist Polymers 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims abstract description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 5
- 238000001465 metallisation Methods 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- 238000005566 electron beam evaporation Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 108
- 229910000679 solder Inorganic materials 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 238000002360 preparation method Methods 0.000 description 7
- 230000001105 regulatory effect Effects 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000001276 controlling effect Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Landscapes
- Wire Bonding (AREA)
Abstract
The application relates to a method for manufacturing a metal bump and a flip chip interconnection method. The manufacturing method of the metal bump comprises the following steps: forming a seed layer on a substrate; forming a first photoresist pattern on the seed layer, the first photoresist pattern exposing a portion of the seed layer; etching to remove the seed layer exposed outside the first photoresist pattern, and then removing the residual first photoresist pattern; forming a second photoresist pattern exposing the seed layer; electroplating on the seed layer by using an electrochemical deposition process to form under-bump metal and metal bumps; and removing the second photoresist pattern. In one embodiment, the material of the second photoresist pattern is SU8 photoresist. The manufacturing method of the metal bump and the manufactured metal bump can be well applied to the interconnection process of the flip chip with the ultra-fine spacing and the adjustable height.
Description
Technical Field
The application belongs to the field of semiconductor processing, and particularly relates to a manufacturing method of a metal bump and a flip chip interconnection method.
Background
With the rapid development of the semiconductor industry, chip packaging is developing towards the trend of increasing pin count and decreasing packaging volume, and the key technology therein is the bump flip-chip bonding process. Therefore, flip chip technology is inevitably under pressure with ever smaller bumps and ever greater bump density. The flip chip technology process comprises the main processes of under bump metallization layer preparation, bump preparation, reflow soldering and the like, wherein the bump preparation is a key technology for realizing the whole packaging mode and plays a decisive role in other process steps. Generally, the bump preparation method mainly comprises the following steps: electrochemical deposition, stud bump, metal mask evaporation, screen printing, ball placement, and solder jetting.
The size, shape control, bump spacing, production efficiency and cost advantages of the bumps are comprehensively considered, the advanced photoetching technology is used, the electrochemical deposition technology is a bump preparation technology which can flexibly control the size and spacing of the bumps in all technologies and is extremely low in cost, the bump preparation requirement of the existing ultrahigh density (the diameter of the ball is less than 100 mu m) can be met, and the method has great application value.
However, the trend of high integration and high density leads to low yield, complex process and low efficiency of the bump preparation process.
Disclosure of Invention
According to a first aspect of the present application, a method for fabricating a metal bump is provided, which includes:
forming a seed layer on a substrate;
forming a first photoresist pattern on the seed layer, the first photoresist pattern exposing a portion of the seed layer;
etching to remove the seed layer exposed outside the first photoresist pattern, and then removing the residual first photoresist pattern;
forming a second photoresist pattern exposing the seed layer;
electroplating on the seed layer by using an electrochemical deposition process to form under-bump metal and metal bumps;
and removing the second photoresist pattern.
The manufacturing method of the metal bump can utilize the thicker (75-85 micrometers) second photoresist pattern as the dielectric layer/sacrificial layer to limit the direction and the appearance of the metal bump formed by subsequent electroplating, so that the solder of the metal bump with the height within 150 micrometers can be regulated and controlled to grow, and the problem of adjustable solder height is solved. In addition, the metal under the bump and the metal bump formed by the electrochemical deposition process have strong directionality, high quality and good uniformity, thereby solving the problem of difficult laser ball planting.
In the manufacturing method of the metal bump, the seed layer in a partial area is etched and removed, and then the metal under the bump and the metal bump are formed by electroplating by using an electrochemical deposition process, so that the process steps are reduced, and the excellent rate of the obtained structure is improved.
Further, before forming the seed layer, an oxide insulating layer is grown on the surface of the substrate by a thermal oxidation method. The oxide insulating layer formed by thermal oxidation can prevent unnecessary electrical interconnection of the underlying pad or electrical structure.
Further, before thermal oxidation, an electrode strip, a plurality of pads and a plurality of connecting wires are arranged on the surface of the substrate, one electrode strip is connected with the plurality of pads, and each pad is electrically connected with the electrode strip through the connecting wire. In a subsequent electrochemical deposition process, voltages may be applied to the plurality of pads simultaneously by applying the voltages to the electrode strips.
Further, the electrode is disposed on a peripheral side of the substrate. The electrodes arranged on the periphery of the substrate do not influence the arrangement of the chip in the middle area, and the electrodes are conveniently cut off in the subsequent process.
Further, the seed layer is formed to include a first seed layer and a second seed layer.
Further, the material of the first seed layer comprises titanium, and the material of the second seed layer comprises gold or copper.
Further, the first seed layer and the second seed layer are formed by utilizing a magnetron sputtering or electron beam evaporation process.
Further, the step of forming the second photoresist pattern includes:
spin coating a second photoresist layer;
and removing the second photoresist layer above the seed layer through a photoetching process, and reserving the second photoresist layer on the peripheral side of the seed layer to form a second photoresist pattern.
Further, the material of the second photoresist layer and the second photoresist pattern is SU8 photoresist.
Further, the second photoresist pattern has a thickness of 75 to 85 micrometers.
Further, the height of the second photoresist pattern is greater than that of the seed layer, so that an accommodating space is formed above the seed layer.
Furthermore, the under bump metal formed by electroplating by using an electrochemical deposition process is completely positioned in the accommodating space above the seed layer; a part of the metal salient points formed by electroplating by utilizing an electrochemical deposition process are positioned in the accommodating space above the seed layer, and the other part of the metal salient points are exposed from the accommodating space.
Further, the under bump metal comprises a nickel layer.
Further, the thickness of the nickel layer is 2.5-3.5 microns.
Further, the metal bump comprises a gold layer or a copper layer on the lower layer and a tin layer on the upper layer.
Further, the thickness of the gold layer or the copper layer is 300-500 nanometers, and the thickness of the tin layer is 90-110 micrometers.
Further, before the step of removing the second photoresist pattern, a reflow process is performed;
through the reflow process, the metal salient point part exposed out of the accommodating space can form an arc salient point part.
Further, the arc-shaped salient point part is spherical or hemispherical.
Further, the temperature of the reflow process is controlled to be 130-140 ℃, and the duration of the reflow process is 50-70 minutes.
According to a second aspect of the present application, there is provided a flip chip interconnection method comprising:
manufacturing the metal bump by using the method;
cutting the substrate to form a plurality of independent chips;
and welding the flip chip to complete packaging.
The flip chip interconnection method can utilize the thicker (75-85 micrometers) second photoresist pattern as a dielectric layer/sacrificial layer to limit the direction and the appearance of the metal bump formed by subsequent electroplating, so that the metal bump solder with the height within 150 micrometers (micrometers) can be regulated and controlled to grow, and the problem of adjustable solder height is solved. In addition, the metal under the bump and the metal bump formed by the electrochemical deposition process have strong directionality, high quality and good uniformity, thereby solving the problem of difficult laser ball planting.
In the flip chip interconnection method, the seed layer in a partial area is etched and removed, and then the under-bump metal and the metal bump are formed by electroplating by using an electrochemical deposition process, so that the process steps are reduced, and the excellent rate of the obtained structure is improved.
Further, in the welding process, the pressure is 400-600N; the temperature is controlled between 105 and 115 ℃.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.
Fig. 1 is a flowchart illustrating a method for manufacturing a metal bump according to an embodiment of the present disclosure.
Fig. 2 to 10 are schematic views illustrating respective intermediate structures obtained in a process of manufacturing a metal bump according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. The use of the terms "a" or "an" and "the" and similar referents in the description and the claims of this application do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" means two or more. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper" and/or "lower," and the like, are used for convenience of description and are not limited to a single position or orientation in space. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The present application provides a method for manufacturing a metal bump, as shown in fig. 1, including:
step S10: forming a seed layer on a substrate;
step S20: forming a first photoresist pattern on the seed layer, the first photoresist pattern exposing a portion of the seed layer;
step S30: etching to remove the seed layer exposed outside the first photoresist pattern, and then removing the residual first photoresist pattern;
step S40: forming a second photoresist pattern exposing the seed layer;
step S50: electroplating on the seed layer by using an electrochemical deposition process to form under-bump metal and metal bumps;
step S60: and removing the second photoresist pattern.
According to the manufacturing method of the metal bump, the thicker (75-85 micrometers) second photoresist pattern (SU-8 photoresist) can be used as the dielectric layer/sacrificial layer to limit the direction and the shape of the metal bump formed by subsequent electroplating, so that the solder of the metal bump with the height within 150 micrometers can be regulated and controlled to grow, and the problem of adjustable solder height is solved. In addition, the metal under the bump and the metal bump formed by the electrochemical deposition process have strong directionality, high quality and good uniformity, thereby solving the problem of difficult laser ball planting.
In the manufacturing method of the metal bump, the seed layer in a partial area is etched and removed, and then the metal under the bump and the metal bump are formed by electroplating through the electrochemical deposition process, so that the process steps are reduced, and the excellent rate of the obtained structure is improved.
The manufacturing method of the metal bump and the manufactured metal bump can be well applied to the interconnection process of the flip chip with the ultra-fine spacing and the adjustable height.
The following describes the method for forming the metal bump in detail with reference to the specific embodiments and the accompanying drawings.
Referring to fig. 2, before step S10, step S05 may be executed: an oxide insulating layer 30 is grown on the surface of the substrate 20 by a thermal oxidation method.
The substrate 20 may be a silicon-based wafer. The oxide insulating layer 30 grown may be silicon dioxide. The thickness of the oxide insulating layer 30 grown may be 2 micrometers (μm).
The surface of the substrate 20 may be provided with a plurality of pads 82 before being subjected to thermal oxidation, as shown in fig. 3. In the thermal oxidation process, the region where the bonding pad is located is not oxidized, so that the bonding pad is still exposed and can be electrically connected with the bump formed subsequently. That is, the oxide insulating layer 30 as grown does not necessarily cover the entire surface of the substrate 20.
The surface of the substrate 20 may also be provided with elongated electrode strips 84, and the number of the electrode strips 84 may be one or more. One electrode bar 84 is connected to a plurality of pads 82 at the same time. In the electrochemical deposition process, voltages may be applied to the plurality of pads 82 simultaneously by applying the voltages to the electrode strips 84. Each pad 82 is connected to an electrode strip 84 by a connecting wire 86. The electrodes 4 may be disposed on the periphery of the substrate 20, so that the disposition of the middle area pads 82 and the chip may not be affected. In the subsequent dicing, the electrodes 4 and the connection wires 86 are cut off and are not part of the chip.
The oxide insulating layer 30 formed by thermal oxidation prevents unnecessary electrical interconnection of underlying pads or electrical structures.
In step S10, the seed layer may be formed as a single layer or a plurality of layers.
With continued reference to FIG. 2, the seed layer formed includes a first seed layer 40 and a second seed layer 50. The first seed layer 40 may be titanium (Ti), and the second seed layer 50 may be gold (Au) or copper (Cu). The first seed layer 40 may have a thickness of 20 nanometers (nm) and the second seed layer 50 may have a thickness of 50 nanometers (nm).
The first and second seed layers 40 and 50 may be formed using a magnetron sputtering or electron beam (thermal) evaporation process.
Referring to fig. 4, in step S20, the first photoresist pattern P1 is formed to expose a portion of the second seed layer 50 thereunder. The position of the first photoresist pattern P1 corresponds to the position of a metal bump to be formed and also corresponds to the position of a pad below.
In specific implementation, a first photoresist layer may be spin-coated on the second seed layer 50, and the first photoresist layer covers the entire surface. The material of the first photoresist layer may be AZ6130 photoresist. And then, exposing by using a mask, and carrying out photoetching development to obtain a first photoresist pattern P1.
In step S30, the second seed layer 50 and the first seed layer 40, which are not covered by the first photoresist pattern P1, may be removed using an Ion Beam Etching (IBE) technique. The second seed layer 50 and the first seed layer 40 under the first photoresist pattern P1 remain due to the shielding protection of the first photoresist pattern P1.
Then, the remaining first photoresist pattern P1 may be removed. The resulting structure is shown in fig. 5.
In the step S40, the forming of the second photoresist pattern may include:
spin coating a whole layer of the second photoresist layer P22, wherein the thickness of the second photoresist layer P22 is greater than that of the seed layer, and the resulting structure is shown in fig. 6;
the second photoresist layer P22 over the seed layer is removed through a photolithography process, and the second photoresist layer P22 at the peripheral side of the seed layer is remained to form a second photoresist pattern P2, resulting in the structure shown in fig. 7. The region of the opening in the second photoresist pattern P2 is the region where the metal bump is to be formed.
In one embodiment, the material of the second photoresist layer P22 and the second photoresist pattern P2 may be SU8-2038 photoresist. In one embodiment, the thickness of the second photoresist pattern P2 is 75 micrometers (μm) to 85 micrometers (μm).
In one embodiment, as shown in fig. 7, the height of the second photoresist pattern P2 is greater than that of the seed layer to form an accommodating space R above the seed layer for accommodating a metal bump to be formed.
The second photoresist layer P22 may be processed using an ultraviolet photolithography process to make a second photoresist pattern P2. In one embodiment, the processing the second photoresist layer P22 using the uv photolithography process includes:
step S41-pretreatment: pretreating the surface of the substrate 20 and the surface of the seed layer by using an oven (such as an HDMS oven) to increase the surface hydrophobicity so as to increase the adhesion between the substrate, the seed layer and the photoresist;
step S42-spin coating: the rotation of the substrate 20 after the photoresist is applied may be controlled in three stages. Wherein the set rotation speed of the first stage is 450-550rad/min, such as 500rad/min. The duration of the first phase is 8-12s, such as 10s; the duration includes the time from zero acceleration to the set rotational speed, which acceleration may be 500rad/s2. The set rotation speed in the second stage is 950-1050rad/min, such as 1000rad/min. The duration of the second phase is 35-45s, such as 40s; the duration comprises the time to accelerate from the set speed of the first phase to the set rotational speed of the second phase, which acceleration may be 500rad/s2. The third stage is a stage of gradual deceleration to zero. The duration of the third phase may be 4-8s, such as 6s;
step S43-Soft baking: controlling the temperature within 0-60 deg.C for 5min;
step S44 — exposure: the method comprises three stages, wherein the energy in unit area is respectively controlled as follows: (1) 280mj/cm 2 ；（2）250mj/cm 2 ；（3）240mj/cm 2 ；
Step S45-baking: comprises four stages, wherein the temperature of the first stage is set to be 65-95 ℃ and the duration time is 3-5min; the temperature of the second stage is set at 95 ℃, and the duration time is 40min; the temperature of the third stage is set to be 95-65 ℃ and the duration is 15min; the fourth stage is natural cooling;
step S46 — development: developing with 1500 Thinner diluent for 5min;
step S47-plasma cleaning: the power was set at 400W and the wash time 5min.
In step S42, the control of the thickness of the second photoresist layer P22 (SU-8 photoresist) is easily achieved by switching the different rotation speeds among the plurality of stages.
Referring to fig. 8, in step S50, the under bump metallurgy 60 formed by the electroplating through the electrochemical deposition process is completely located in the receiving space R above the seed layer, a portion of the metal bump 70 formed by the electroplating through the electrochemical deposition process is located in the receiving space R above the seed layer, and another portion (upper portion) of the metal bump 70 is exposed from the receiving space R.
In one embodiment, the under bump metallization 60 comprises a nickel layer (Ni). The thickness of the nickel layer may be 2.5-3.5 micrometers (μm), such as 3 μm. In one embodiment, the metal bump 70 includes a gold (Au) or copper (Cu) layer on a lower layer and a tin (Sn) layer on an upper layer. The thickness of the gold or copper layer may be 300-500 nanometers (nm), such as 400 nm; the tin layer may have a thickness of 90-110 micrometers (μm), such as 100 μm. The thickness of the gold layer or the copper layer and the thickness of the tin layer in the metal bump 70 can be well controlled by the second photoresist pattern P2, and further the height difference of the flip-chip bonding between the chip and the substrate can be adjusted at will according to different use scenes.
In one embodiment, the under bump metallization and metal bumps are electroplated with a low current, low rate during the electrochemical deposition process described above to further improve the quality, uniformity, and adhesion of the plating. Therefore, the defects of micro-holes, cracks and the like in the metal salient points can be avoided, and the problems of salient point fracture, insufficient adhesion and the like in the follow-up process are solved.
After step S50 and before step S60, step S55, a reflow process, may also be performed. Through the reflow process, an arc bump portion 75 is formed on the portion of the metal bump 70 exposed from the accommodating space R, as shown in fig. 9. The arc-shaped convex point portion 75 may have a spherical shape or a hemispherical shape.
In one embodiment, the temperature of the reflow process is controlled to be between 130-140 ℃, such as 135 ℃, and the duration of the reflow process is 50-70 minutes, such as 1 hour.
In step S60, the second photoresist pattern P2 may be removed by sequentially cleaning with acetone, ethanol, and deionized water. The resulting structure is shown in fig. 10.
After step S60, step S70 may also be performed: the substrate 20 is diced to form individual chips. After cutting, the relative integrity and adaptability of each chip circuit are ensured. In the cutting process, each metal bump structure is also cut to form a whole with the corresponding chip.
In one embodiment, the cutting may be accomplished with a hard knife.
After step S70, step S80 may also be performed: and reversing the chip for welding to complete the packaging. In one embodiment, the pressure between the chip and the substrate is maintained at 400-600N, such as 500N, during the soldering process; controlling the temperature to be 105-115 ℃, such as 110 ℃; the duration is 18-22 minutes, such as 20 minutes.
In the embodiment of the application, the thicker (75-85 micrometers) second photoresist pattern (SU-8 photoresist) is used as a dielectric layer/sacrificial layer to limit the direction and the shape of the metal bump formed by subsequent electroplating, so that the metal bump solder with the height within 150 micrometers (mum) can be regulated and controlled to grow, and the problem of adjustable solder height is solved. In addition, the metal under the bump and the metal bump formed by the electrochemical deposition process have strong directionality, high quality and good uniformity, thereby solving the problem of difficult laser ball planting.
In the embodiment of the application, the seed layer in a partial area is etched and removed, and then the under-bump metal and the metal bump are formed by electroplating by using an electrochemical deposition process, so that the process steps are reduced, and the excellent rate of the obtained structure is improved.
In the present application, the embodiments may be complementary to each other without conflict.
In this application, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. The terms "plurality," "plurality," and "a number" mean two or more unless expressly specified otherwise.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (21)
1. A method for manufacturing a metal bump is characterized by comprising the following steps:
forming a seed layer on a substrate;
forming a first photoresist pattern on the seed layer, the first photoresist pattern exposing a portion of the seed layer;
etching to remove the seed layer exposed outside the first photoresist pattern, and then removing the residual first photoresist pattern;
forming a second photoresist pattern exposing the seed layer;
electroplating on the seed layer by using an electrochemical deposition process to form under-bump metal and metal bumps;
and removing the second photoresist pattern.
2. The method for fabricating a metal bump according to claim 1 wherein an oxide insulating layer is grown on the surface of the substrate by a thermal oxidation method before forming the seed layer.
3. The method for fabricating a metal bump according to claim 2 wherein, before the thermal oxidation, an electrode bar, a plurality of pads and a plurality of connecting wires are disposed on the surface of the substrate, one of the electrode bars is connected to a plurality of pads, and each of the pads is electrically connected to the electrode bar through the connecting wire.
4. The method for fabricating a metal bump according to claim 3, wherein the electrode is disposed on a peripheral side of the substrate.
5. The method of claim 1, wherein the seed layer comprises a first seed layer and a second seed layer.
6. The method for fabricating a metal bump according to claim 5 wherein the material of the first seed layer comprises titanium and the material of the second seed layer comprises gold or copper.
7. The method for forming a metal bump according to claim 6 wherein the first seed layer and the second seed layer are formed by magnetron sputtering or electron beam evaporation.
8. The method for fabricating a metal bump according to claim 1, wherein the step of forming a second photoresist pattern comprises:
spin coating a second photoresist layer;
and removing the second photoresist layer above the seed layer through a photoetching process, and reserving the second photoresist layer on the peripheral side of the seed layer to form a second photoresist pattern.
9. The method for fabricating a metal bump according to claim 8 wherein the material of the second photoresist layer and the second photoresist pattern is SU8 photoresist.
10. The method of claim 8, wherein the second photoresist pattern has a thickness of 75 to 85 microns.
11. The method of claim 8, wherein a height of the second photoresist pattern is greater than a height of the seed layer to form a receiving space above the seed layer.
12. The method of claim 11, wherein the under bump metallization formed by electroplating using an electrochemical deposition process is completely disposed in the receiving space above the seed layer; a part of the metal salient points formed by electroplating by utilizing an electrochemical deposition process are positioned in the accommodating space above the seed layer, and the other part of the metal salient points are exposed from the accommodating space.
13. The method of claim 12, wherein the under bump metallization comprises a nickel layer.
14. The method for forming a metal bump according to claim 13 wherein said nickel layer has a thickness of 2.5 to 3.5 microns.
15. The method for forming a metal bump according to claim 12 wherein the metal bump comprises a gold or copper layer on a lower layer and a tin layer on an upper layer.
16. The method for fabricating a metal bump according to claim 15 wherein the thickness of the gold or copper layer is 300-500 nm and the thickness of the tin layer is 90-110 μm.
17. The method for fabricating a metal bump according to claim 12, wherein a reflow process is performed before the step of removing the second photoresist pattern;
through the reflow process, the metal salient point part exposed out of the accommodating space can form an arc salient point part.
18. The method of claim 17, wherein the arc bump portion is spherical or semi-spherical.
19. The method for fabricating a metal bump according to claim 17 wherein the temperature of the reflow process is controlled to be between 130 ℃ and 140 ℃ and the duration of the reflow process is 50 minutes to 70 minutes.
20. A flip chip interconnection method, comprising:
fabricating a metal bump by a method as claimed in any one of claims 1 to 19;
cutting the substrate to form a plurality of independent chips;
and welding the flip chip to complete the packaging.
21. The flip chip interconnection method of claim 20, wherein during the bonding, the pressure is 400-600 n and the temperature is controlled at 105-115 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310019294.1A CN115939033A (en) | 2023-01-06 | 2023-01-06 | Manufacturing method of metal bump and flip chip interconnection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310019294.1A CN115939033A (en) | 2023-01-06 | 2023-01-06 | Manufacturing method of metal bump and flip chip interconnection method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN115939033A true CN115939033A (en) | 2023-04-07 |
Family
ID=86654399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310019294.1A Pending CN115939033A (en) | 2023-01-06 | 2023-01-06 | Manufacturing method of metal bump and flip chip interconnection method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115939033A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593220B1 (en) * | 2002-01-03 | 2003-07-15 | Taiwan Semiconductor Manufacturing Company | Elastomer plating mask sealed wafer level package method |
| KR20050005303A (en) * | 2003-07-01 | 2005-01-13 | 삼성전자주식회사 | Fabrication method of Solder for flip-chip |
| CN102005396A (en) * | 2009-08-28 | 2011-04-06 | 中芯国际集成电路制造(上海)有限公司 | Bump making method and bump structure |
| US20120305631A1 (en) * | 2011-06-06 | 2012-12-06 | International Business Machines Corporation | Injection molded solder process for forming solder bumps on substrates |
| KR20140031155A (en) * | 2013-10-29 | 2014-03-12 | 에스티에스반도체통신 주식회사 | Semiconductor packages and methods for fabricating the same |
| US20200211990A1 (en) * | 2018-12-31 | 2020-07-02 | Texas Instruments Incorporated | Packaged semiconductor device with electroplated pillars |
| CN113314492A (en) * | 2020-02-27 | 2021-08-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN115036390A (en) * | 2022-04-24 | 2022-09-09 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Method for preparing height-width ratio increased type welding point column, electronic device and infrared detector |
-
2023
- 2023-01-06 CN CN202310019294.1A patent/CN115939033A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6593220B1 (en) * | 2002-01-03 | 2003-07-15 | Taiwan Semiconductor Manufacturing Company | Elastomer plating mask sealed wafer level package method |
| KR20050005303A (en) * | 2003-07-01 | 2005-01-13 | 삼성전자주식회사 | Fabrication method of Solder for flip-chip |
| CN102005396A (en) * | 2009-08-28 | 2011-04-06 | 中芯国际集成电路制造(上海)有限公司 | Bump making method and bump structure |
| US20120305631A1 (en) * | 2011-06-06 | 2012-12-06 | International Business Machines Corporation | Injection molded solder process for forming solder bumps on substrates |
| KR20140031155A (en) * | 2013-10-29 | 2014-03-12 | 에스티에스반도체통신 주식회사 | Semiconductor packages and methods for fabricating the same |
| US20200211990A1 (en) * | 2018-12-31 | 2020-07-02 | Texas Instruments Incorporated | Packaged semiconductor device with electroplated pillars |
| CN113314492A (en) * | 2020-02-27 | 2021-08-27 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN115036390A (en) * | 2022-04-24 | 2022-09-09 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Method for preparing height-width ratio increased type welding point column, electronic device and infrared detector |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5418186A (en) | Method for manufacturing a bump on a semiconductor chip | |
| KR100319813B1 (en) | method of forming solder bumps with reduced UBM undercut | |
| US6972480B2 (en) | Methods and apparatus for packaging integrated circuit devices | |
| KR100264479B1 (en) | Structure of bump electrode and method of forming the same | |
| US10700027B2 (en) | Semiconductor copper metallization structure and related methods | |
| US20120129333A1 (en) | Method for manufacturing semiconductor package and semiconductor package manufactured using the same | |
| JPH05335313A (en) | Manufacture of indium bump | |
| US20080230877A1 (en) | Semiconductor package having wire redistribution layer and method of fabricating the same | |
| JP2000100843A (en) | Semiconductor package and manufacture thereof | |
| KR20200068958A (en) | Connection structure and method of forming the same | |
| US8294266B2 (en) | Conductor bump method and apparatus | |
| JP2018116974A (en) | Semiconductor device and manufacturing method of the same | |
| JP2012114256A (en) | Method of producing solder bump, and semiconductor device | |
| CN112106191A (en) | Semiconductor structure and method for wafer level chip packaging | |
| CN115939033A (en) | Manufacturing method of metal bump and flip chip interconnection method | |
| JP5296567B2 (en) | Manufacturing method of semiconductor device | |
| JP2007258629A (en) | Manufacturing method of chip size package | |
| US20030157438A1 (en) | Bump forming process | |
| CN106252315B (en) | Encapsulating structure and its manufacturing method | |
| US20100330744A1 (en) | Ultrathin semiconductor circuit having contact bumps and corresponding production method | |
| JP2006120803A (en) | Semiconductor device and manufacturing method therefor | |
| CN111293099B (en) | Semiconductor circuit structure and manufacturing method thereof | |
| KR20090048879A (en) | Method of forming wire rerouting pattern for semiconductor packages | |
| JPH08213402A (en) | Manufacture of semiconductor device | |
| CN116072548A (en) | Method for manufacturing semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |