CN115938286A - Display device and pixel unit circuit thereof - Google Patents

Abstract

The invention discloses a display device and a pixel unit circuit thereof. The PAM control region is used for generating a PAM control signal according to a first voltage and a first data voltage. The PWM control area is used for generating a PWM control signal according to the first voltage, a second data voltage and a scanning signal. A control terminal of the second transistor is coupled to the PWM control region. A first terminal of the second transistor is coupled to the PAM control region. A control terminal of the fourteenth transistor receives a lighting control signal. A first terminal of the fourteenth transistor is coupled to a second terminal of the second transistor. The light emitting element is coupled to a second end of the fourteenth transistor.

Description

Display device and pixel unit circuit thereof

Technical Field

The invention relates to a display device and a pixel unit circuit thereof.

Background

Micro light emitting diodes (Micro LEDs) have recently been widely used in display devices. Micro light emitting diodes have higher peak luminance compared to Organic Light Emitting Diodes (OLEDs). However, the luminous efficiency of the micro-leds varies as the current density varies. Therefore, in order to operate the micro light emitting diode with a better light emitting efficiency, it is necessary to improve the pixel unit circuit.

Disclosure of Invention

The embodiment of the invention discloses a pixel unit circuit, which comprises a PAM control area, a PWM control area, a second transistor, a fourth transistor and a light-emitting element. The PAM control region is used for generating a PAM control signal according to a first voltage and a first data voltage. The PWM control area is used for generating a PWM control signal according to the first voltage, a second data voltage and a scanning signal. A control terminal of the second transistor is coupled to the PWM control region. A first terminal of the second transistor is coupled to the PAM control region. A control terminal of the fourteenth transistor receives a lighting control signal. A first terminal of the fourteenth transistor is coupled to a second terminal of the second transistor. The light emitting element is coupled to a second end of the fourteenth transistor.

The embodiment of the invention discloses a display device which comprises a plurality of pixel unit circuits. Each pixel unit circuit comprises a PAM control area, a PWM control area, a second transistor, a fourth transistor and a light-emitting element. The PAM control region is used for generating a PAM control signal according to a first voltage and a first data voltage. The PWM control area is used for generating a PWM control signal according to the first voltage, a second data voltage and a scanning signal. A control terminal of the second transistor is coupled to the PWM control region. A first terminal of the second transistor is coupled to the PAM control region. A control terminal of the fourteenth transistor receives a lighting control signal. A first terminal of the fourteenth transistor is coupled to a second terminal of the second transistor. The light emitting element is coupled to a second end of the fourteenth transistor.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments is made with reference to the accompanying drawings:

drawings

FIG. 1 shows a block diagram of a pixel cell circuit according to an embodiment of the invention;

FIG. 2 shows a circuit schematic of a pixel cell circuit according to an embodiment of the invention;

FIG. 3 is a schematic diagram illustrating signal timing according to an embodiment of the present invention;

FIG. 4 shows a schematic diagram of signal timing according to another embodiment of the present invention.

Description of reference numerals:

10. 20: pixel unit circuit

101: PAM control zone

102: PWM control region

103. 104, T1 to T14: transistor with a high breakdown voltage

105. LED: light emitting element

C1, C2: capacitor with a capacitor element

S1: first signal

S2: second signal

S3: third signal

S4: the fourth signal

Sweet: sweeping signal

EM: light emission control signal

VDD: first voltage

VSS: second voltage

Vref1: a first reference voltage

Vref2: second reference voltage

And (3) DataI: first data voltage

And (3) data G: second data voltage

V3: third voltage

V4: a fourth voltage

F. F': frame time

t1, t1': reset phase

t2, t2': compensation phase

t3, t3', t5', t7': stage of luminescence

t4', t6': non-light emitting stage

Detailed Description

Referring to fig. 1, fig. 1 is a block diagram of a pixel unit circuit according to an embodiment of the invention. The pixel circuit 10 includes a Pulse Amplitude Modulation (PAM) control region 101, a Pulse Width Modulation (PWM) control region 102, transistors 103 and 104, and a light emitting element 105.

The PAM control region 101 is configured to generate a PAM control signal according to a first voltage VDD and a first data signal DataI.

The PWM control section 102 is used for generating a PWM control signal according to the first voltage VDD, a second data signal DataG and a scan signal Sweep.

A control terminal of the transistor 103 is coupled to the PWM control region 102 and receives the PWM control signal. A first terminal of the transistor 103 is coupled to the PAM control region 101 and receives the PAM control signal.

A control terminal of the transistor 104 receives the transmission and reception control signal EM. A first terminal of the transistor 104 is coupled to a second terminal of the transistor T103.

A first terminal of the light emitting device 105 is coupled to a second terminal of the transistor 104. A second terminal of the light emitting device 105 receives a second voltage VSS.

Referring to fig. 2, fig. 2 is a circuit diagram of a pixel unit circuit according to an embodiment of the invention. The pixel cell circuit 20 is a detailed circuit of a specific embodiment of the pixel cell circuit 10.

The PAM control region 101 includes transistors T1, T4, T8, T10, and T11 and a capacitor C1.

The PWM control region 102 includes transistors T3, T5, T6, T7, T9, T12, T13 and a capacitor C2.

The transistor T2 corresponds to the transistor 103 of the pixel unit circuit 10. The transistor T14 corresponds to the transistor 104 of the pixel unit circuit 10. The light emitting element LED corresponds to the light emitting element 105 of the pixel unit circuit 10.

A first terminal of the transistor T1 receives the first voltage VDD. A second terminal of the transistor T1 is coupled to a first terminal of the transistor T2. A control terminal of the transistor T4 receives a third signal S3. A first terminal of the transistor T4 is coupled to the second terminal of the transistor T1. A second terminal of the transistor T4 is coupled to a control terminal of the transistor T1. A control terminal of the transistor T8 receives a first signal S1. A first terminal of the transistor T8 is coupled to the control terminal of the transistor T1. A second terminal of the transistor T8 is coupled to a control terminal of the transistor T2. A control terminal of the transistor T10 receives a second signal S2. A first terminal of the transistor T10 receives the first data signal DataI. A control terminal of the transistor T11 receives the transmission and reception control signal EM. A first terminal of the transistor T11 is coupled to a second terminal of the transistor T10. A second terminal of the transistor T11 receives a first reference voltage Vref1. A first terminal of the capacitor C1 is coupled to the control terminal of the transistor T1. A second terminal of the capacitor C1 is coupled to the second terminal of the transistor T10.

A control terminal of the transistor T6 receives the fourth signal S4. A first terminal of the transistor T6 is coupled to the control terminal of the transistor T2. A second terminal of the transistor T6 receives a second reference voltage Vref2. A control terminal of the transistor T7 receives the first signal S1. A first terminal of the transistor T7 receives the second reference voltage Vref2. A control terminal of the transistor T9 receives the transmission and reception control signal EM. A first terminal of the transistor T9 is coupled to the first terminal of the transistor T6. A control terminal of the transistor T3 is coupled to a second terminal of the transistor T7. A first terminal of the transistor T3 is coupled to a second terminal of the transistor T9. A control terminal of the transistor T5 receives the third signal S3. A second terminal of the transistor T5 is coupled to the second terminal of the transistor T7. A control terminal of the transistor T12 receives the transmission and reception control signal EM. A first terminal of the transistor T12 is coupled to a second terminal of the transistor T3. A second terminal of the transistor T12 receives the first voltage VDD. A control terminal of the transistor T13 receives the third signal S3. A first terminal of the transistor T13 is coupled to the second terminal of the transistor T3. A second terminal of the transistor T13 receives the second data signal DataG. A first terminal of the capacitor C2 is coupled to the second terminal of the transistor T7. A second terminal of the capacitor C2 receives the Sweep signal Sweep.

A control terminal of the transistor T14 receives the transmission and reception control signal EM. A first terminal of the transistor T14 is coupled to a second terminal of the transistor T2.

A first terminal of the light emitting device LED is coupled to a second terminal of the transistor T14. A second terminal of the light emitting element LED receives the second voltage VSS.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating signal timing according to an embodiment of the invention.

In a reset period t1 during a frame time F, the first signal S1 is at a low voltage level, the second signal S2 is at a low voltage level, the third signal S3 is at a high voltage level, the fourth signal S4 is at a low voltage level, the emission control signal EM is at a high voltage level, and the Sweep signal Sweep is at a third voltage V3. The transistors T4, T5, T9, T11, T12, T14 are non-conductive. The transistors T1, T2, T3, T6, T7, T8, T10, T13 are turned on. The second reference voltage Vref2 is written into the control terminals of the transistors T1, T2, T3.

In a compensation stage t2 during the frame time F, the first signal S1 is at a high voltage level, the second signal S2 is at a low voltage level, the third signal S3 is at a low voltage level, the fourth signal S4 is at a low voltage level, the emission control signal EM is at a high voltage level, and the Sweep signal Sweep is at a third voltage V3. The transistors T6, T7, T8, T9, T11, T12, T14 are non-conductive. The transistors T2, T4, T5, T10, T13 are turned on. The transistors T1, T3 gradually change from conductive to non-conductive. The second data voltage DataG is written to the control terminal of the transistor T3 through the transistors T13, T3, and T5, and the transistor T3 is gradually turned from on to off, thereby compensating for process variations of the transistor T3. The first voltage VDD is written to the control terminal of the transistor T1 through the transistors T1 and T4, and the transistor T1 is gradually turned from on to off, thereby compensating for process variations of the transistor T1.

In a lighting period t3 during the frame time F, the first signal S1 is at a high voltage level, the second signal S2 is at a high voltage level, the third signal S3 is at a high voltage level, the fourth signal S4 is at a high voltage level, the emission control signal EM is at a low voltage level, and the Sweep signal Sweep is gradually decreased from the third voltage V3 to a fourth voltage V4. The transistors T4, T5, T6, T7, T8, T10, T13 are non-conductive. The transistors T1, T9, T11, T12, T14 are turned on. The transistors T2, T3 gradually change from non-conducting to conducting. For the PAM control region, the control terminal of the transistor T1 is in a floating state, and the voltage of the control terminal of the transistor T1 is affected by the coupling effect of the capacitor C1 and becomes the voltage at the end of the compensation period T2 plus the first reference voltage Vref1 minus the first data voltage DataI. In this way, the current value of the PAM control signal output from the second terminal of the transistor T1 can be accurately determined. For the PWM control region, the Sweep signal Sweep is coupled to the control terminal of the transistor T3 through the capacitor C2 such that the transistor T3 gradually changes from conductive to non-conductive, and when the transistor T3 is conductive, the first voltage VDD is transferred to the control terminal of the transistor T2 such that the transistor T2 changes from conductive to non-conductive. In this way, the time that the PAM control signal is allowed to pass through the transistor T2 can be determined by the PWM control signal.

Referring to fig. 4, fig. 4 is a schematic diagram illustrating a signal timing sequence according to another embodiment of the invention. In this embodiment, one frame time F 'may include a plurality of light emitting periods t3', t5', t7', and two light emitting periods are connected by a non-light emitting period. For example, the light-emitting phases t3', t5' are connected in the light-emitting phase t4', and the light-emitting phases t5', t7 'are connected in the non-light-emitting phase t 6'. The operation of the reproducing stage t1', the compensating stage t2' and the lighting stages t3', t5' and t7' is similar to the reproducing stage t1, the compensating stage t2 and the lighting stage t3, respectively, as described above. In the non-light emitting periods t4 'and t6', the first signal S1 is at a high voltage level, the second signal S2 is at a low voltage level, the third signal S3 is at a low voltage level, the fourth signal S4 is at a high voltage level, the light emitting control signal EM is changed from the low voltage level to the high voltage level, and the Sweep signal Sweep is returned from the fourth voltage V4 to the third voltage V3. That is, during one frame time F', the third signal S3, the emission control signal EM, and the Sweep signal Sweep may be multi-pulses (multi-pulses).

It should be noted that the number of the light-emitting phases and the non-light-emitting phases included in one frame time is not limited to the examples shown in the above embodiments, and may be designed differently according to the requirements in different embodiments. In a general embodiment, one frame time includes two or more lighting periods and one or more non-lighting periods.

In the above embodiments, the transistors are all described by taking PMOS as an example. However, in alternative embodiments, the transistors may be NMOS, or a combination of PMOS and NMOS, and the technical effects of the present invention can be achieved by only performing adaptive adjustment on each signal. In one embodiment, the light emitting device is a Micro light emitting diode (Micro LED), but the invention is not limited thereto.

In the above embodiments, the high voltage level and the low voltage level of each signal may be the same or different. The high voltage level is a voltage applied to the control terminal of the PMOS transistor sufficient to render the transistor non-conductive, while the low voltage level PMOS is a voltage applied to the control terminal of the transistor sufficient to render the transistor conductive. In an embodiment, the high voltage levels of the first signal S1, the second signal S2, the third signal S3, the fourth signal S4 and the emission control signal EM are greater than the first voltage VDD, the third voltage V3, the fourth voltage V4, the first data voltage DataI and the second data voltage DataG, the first voltage VDD, the third voltage V3, the fourth voltage V4, the first data voltage DataI and the second data voltage DataG are greater than or equal to the first reference voltage Vref1, the first reference voltage Vref1 is greater than the second reference voltage Vref2, the second reference voltage Vref2 is greater than or equal to the second voltage VSS, and the second voltage VSS is greater than the low voltage levels of the first signal S1, the second signal S2, the third signal S3, the fourth signal S4 and the emission control signal EM.

The invention also discloses a display device. The display device comprises a plurality of pixel unit circuits, wherein the pixel unit circuits are arranged in an array and coupled to a control circuit, and the control circuit is at least used for generating the first signal S1, the second signal S2, the third signal S3, the fourth signal S4, the light-emitting control signal EM, the Sweep signal Sweep, the first data voltage DataI, the second data voltage DataG, the first reference voltage Vref1, the second reference voltage Vref2, the first voltage VDD and the second voltage VSS.

While the invention has been described with reference to the above embodiments, it is not intended to be limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the claims.

Claims (10)

1. A pixel cell circuit, comprising:

a PAM control region for generating a PAM control signal according to a first voltage and a first data voltage;

a PWM control region for generating a PWM control signal according to the first voltage, a second data voltage and a scan signal;

a second transistor, wherein a control terminal of the second transistor is coupled to the PWM control region, and a first terminal of the second transistor is coupled to the PAM control region;

a fourteenth transistor, a control terminal of which receives a lighting control signal, a first terminal of which is coupled to a second terminal of the second transistor; and

a light emitting device coupled to a second terminal of the fourteenth transistor.

2. The pixel cell circuit of claim 1, wherein the PAM control region comprises a first transistor, a fourth transistor, an eighth transistor, a tenth transistor, an eleventh transistor, and a first capacitor, a first terminal of the first transistor receives the first voltage, a second terminal of the first transistor is coupled to the first terminal of the second transistor, a control terminal of the fourth transistor receives a third signal, a first terminal of the fourth transistor is coupled to the second terminal of the first transistor, a second terminal of the fourth transistor is coupled to a control terminal of the first transistor, a control terminal of the eighth transistor receives a first signal, a first terminal of the eighth transistor is coupled to the control terminal of the first transistor, a second terminal of the eighth transistor is coupled to the control terminal of the second transistor, a control terminal of the tenth transistor receives a second signal, a first terminal of the tenth transistor receives the first data signal, a control terminal of the eleventh transistor receives the emission control signal, a first terminal of the eleventh transistor is coupled to a second terminal of the tenth transistor, a second terminal of the eleventh transistor receives a first reference voltage, a first terminal of the first capacitor is coupled to the control terminal of the first transistor, and a second terminal of the first capacitor is coupled to the second terminal of the tenth transistor.

3. The pixel cell circuit of claim 2, wherein the PWM control region comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, a ninth transistor, a twelfth transistor, a thirteenth transistor and a second capacitor, a control terminal of the sixth transistor receives the fourth signal, a first terminal of the sixth transistor is coupled to the control terminal of the second transistor, a second terminal of the sixth transistor receives a second reference voltage, a control terminal of the seventh transistor receives the first signal, a first terminal of the seventh transistor receives the second reference voltage, a control terminal of the ninth transistor receives the emission control signal, a first terminal of the ninth transistor is coupled to the first terminal of the sixth transistor, a control terminal of the third transistor is coupled to a second terminal of the seventh transistor, a first terminal of the third transistor is coupled to a second terminal of the ninth transistor, a control terminal of the fifth transistor receives the third signal, a second terminal of the fifth transistor is coupled to the second terminal of the seventh transistor, a control terminal of the twelfth transistor receives the light emitting control signal, a first terminal of the twelfth transistor is coupled to a second terminal of the third transistor, a second terminal of the twelfth transistor receives the first voltage, a control terminal of the thirteenth transistor receives the third signal, a first terminal of the thirteenth transistor is coupled to the second terminal of the third transistor, a second terminal of the thirteenth transistor receives the second data signal, a first terminal of the second capacitor is coupled to the second terminal of the seventh transistor, and a second terminal of the second capacitor receives the sweep signal.

4. The pixel cell circuit of claim 3, wherein a frame time comprises a reset phase, a compensation phase and a light emitting phase, wherein in the reset phase, the first signal is at a low voltage level, the second signal is at a low voltage level, the third signal is at a high voltage level, the fourth signal is at a low voltage level, the light emitting control signal is at a high voltage level, the sweeping signal is at a third voltage, in the compensation phase, the first signal is at a high voltage level, the second signal is at a low voltage level, the third signal is at a low voltage level, the fourth signal is at a low voltage level, the light emitting control signal is at a high voltage level, the sweeping signal is at a third voltage, in the light emitting phase, the first signal is at a high voltage level, the second signal is at a high voltage level, the third signal is at a high voltage level, the fourth signal is at a high voltage level, the light emitting control signal is at a low voltage level, and the sweeping signal gradually decreases from the third voltage to a fourth voltage.

5. The pixel cell circuit of claim 3, wherein a frame time comprises a reset phase, a compensation phase, a plurality of emission phases and at least one non-emission phase, wherein in the reset phase, the first signal is at a low voltage level, the second signal is at a low voltage level, the third signal is at a high voltage level, the fourth signal is at a low voltage level, the emission control signal is at a high voltage level, the sweep signal is at a third voltage, in the compensation phase, the first signal is at a high voltage level, the second signal is at a low voltage level, the third signal is at a low voltage level, the fourth signal is at a low voltage level, the emission control signal is at a high voltage level, the first signal is a high voltage level, the second signal is a high voltage level, the third signal is a high voltage level, the fourth signal is a high voltage level, the emission control signal is a low voltage level, the sweeping signal gradually decreases from the third voltage level to a fourth voltage level, the first signal is a high voltage level, the second signal is a high voltage level, the third signal is a high voltage level, the fourth signal is a low voltage level, the emission control signal is converted from a low voltage level to a high voltage level, and the sweeping signal is the third voltage.

6. A display device, comprising:

a plurality of pixel unit circuits, each of the pixel unit circuits comprising:

a PAM control region for generating a PAM control signal according to a first voltage and a first data voltage;

a PWM control region for generating a PWM control signal according to the first voltage, a second data voltage and a scan signal;

a second transistor, wherein a control terminal of the second transistor is coupled to the PWM control region, and a first terminal of the second transistor is coupled to the PAM control region;

a fourteenth transistor, a control terminal of the fourteenth transistor receiving an emission control signal, a first terminal of the fourteenth transistor being coupled to a second terminal of the second transistor; and

a light emitting device coupled to a second terminal of the fourteenth transistor.

7. The display apparatus according to claim 6, wherein each of the PAM control regions comprises a first transistor, a fourth transistor, an eighth transistor, a tenth transistor, an eleventh transistor, and a first capacitor, a first terminal of the first transistor receives the first voltage, a second terminal of the first transistor is coupled to the first terminal of the second transistor, a control terminal of the fourth transistor receives a third signal, a first terminal of the fourth transistor is coupled to the second terminal of the first transistor, a second terminal of the fourth transistor is coupled to a control terminal of the first transistor, a control terminal of the eighth transistor receives a first signal, a first terminal of the eighth transistor is coupled to the control terminal of the first transistor, a second terminal of the eighth transistor is coupled to the control terminal of the second transistor, a control terminal of the tenth transistor receives a second signal, a first terminal of the tenth transistor receives the first data signal, a control terminal of the eleventh transistor receives a control signal, a control terminal of the eleventh transistor is coupled to the control terminal of the first transistor, a first terminal of the tenth transistor is coupled to the second terminal of the first transistor, and a first capacitor is coupled to the second terminal of the first transistor, a first terminal of the tenth transistor receives a first voltage, a first terminal of the eleventh transistor, a first terminal of the first transistor is coupled to the first capacitor.

8. The display device according to claim 7, wherein each PWM control region comprises a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, a ninth transistor, a twelfth transistor, a thirteenth transistor and a second capacitor, a control terminal of the sixth transistor receives the fourth signal, a first terminal of the sixth transistor is coupled to the control terminal of the second transistor, a second terminal of the sixth transistor receives a second reference voltage, a control terminal of the seventh transistor receives the first signal, a first terminal of the seventh transistor receives the second reference voltage, a control terminal of the ninth transistor receives the emission control signal, a first terminal of the ninth transistor is coupled to the first terminal of the sixth transistor, a control terminal of the third transistor is coupled to a second terminal of the seventh transistor, a first terminal of the third transistor is coupled to a second terminal of the ninth transistor, a control terminal of the fifth transistor receives the third signal, a second terminal of the fifth transistor is coupled to the second terminal of the seventh transistor, a control terminal of the twelfth transistor receives the light emitting control signal, a first terminal of the twelfth transistor is coupled to a second terminal of the third transistor, a second terminal of the twelfth transistor receives the first voltage, a control terminal of the thirteenth transistor receives the third signal, a first terminal of the thirteenth transistor is coupled to the second terminal of the third transistor, a second terminal of the thirteenth transistor receives the second data signal, a first terminal of the second capacitor is coupled to the second terminal of the seventh transistor, and a second terminal of the second capacitor receives the sweep signal.

9. The display device according to claim 8, wherein a frame time includes a reset period, a compensation period and a light emitting period, wherein the first signal is at a low voltage level, the second signal is at a low voltage level, the third signal is at a high voltage level, the fourth signal is at a low voltage level, the light emitting control signal is at a high voltage level, the sweeping signal is at a third voltage level, the first signal is at a high voltage level, the second signal is at a low voltage level, the third signal is at a low voltage level, the fourth signal is at a low voltage level, the light emitting control signal is at a high voltage level, the sweeping signal is at the third voltage level, the first signal is at a high voltage level, the second signal is at a high voltage level, the third signal is at a high voltage level, the fourth signal is at a high voltage level, the light emitting control signal is at a low voltage level, and the sweeping signal gradually decreases from the third voltage to a fourth voltage.

10. The display device according to claim 8, wherein a frame time includes a reset stage in which the first signal is at a low voltage level, the second signal is at a low voltage level, the third signal is at a high voltage level, the fourth signal is at a low voltage level, the emission control signal is at a high voltage level, and the sweep signal is at a third voltage, a compensation stage in which the first signal is at a high voltage level, the second signal is at a low voltage level, the third signal is at a low voltage level, the fourth signal is at a low voltage level, the emission control signal is at a high voltage level, the sweep signal is at a third voltage level, the first signal is at a high voltage level, the second signal is at a high voltage level, the third signal is at a high voltage level, the fourth signal is at a high voltage level, the emission control signal is at a low voltage level, the sweep signal is gradually reduced from the third voltage level to the fourth voltage level, the sweep signal is at least one of the high voltage level, and the sweep signal is at least one of the high voltage level, the sweep signal level is at least one of the high voltage level, and the sweep signal level is at least one of the high voltage level.

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