CN115935865A - Verification method and platform for reconfigurable chip - Google Patents
Verification method and platform for reconfigurable chip Download PDFInfo
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Abstract
The invention discloses a verification method and a verification platform of a reconfigurable chip, which comprise the following steps: and (4) according to the set format and the key field specification in the format setting, the text of the RTL top-level file is specified. And generating a verification environment framework according to the specified RTL top-level file text. And verifying the reconfigurable chip through the generated verification environment framework. The invention also provides a verification method and a verification platform of the reconfigurable chip, which are used for reconstructing a top-level file of RTL design by adding keywords in a specific format. By using the verification platform, module-level verification environments of different modules are created according to different specific design characteristics. The verification method of the invention enables the module-level verification environments of different modules to use a set of similar verification methodologies to refine the specific verification codes of the module. And run the same simulation script to start eda simulation to check the simulation results. The same debugging and tracing means are used for realizing the quality assurance of different modules of the reconfigurable chip.
Description
Technical Field
The invention relates to the technical field of verification of reconfigurable chips. The invention particularly relates to a verification method and a verification platform of a reconfigurable chip.
Background
Chip verification is needed in the stage of chip design requirement, and different verification methods are needed in the whole life cycle of chip design to search for the design defects of the chip and fully and quickly release the chip-casting risk. The chip verification comprises logic function verification, pressure test verification, service life test verification, software and hardware collaborative verification and the like. In a logic function verification link, especially in module-level function verification, 70% of the whole chip development cycle is occupied, wherein a large amount of verification time is also required for constructing a large number of test cases.
In the verification method of the reconfigurable chip, verification processes such as a reference model of a relevant operator, a simulator of a processor, a memory model, verification IP and the like are required, and a large number of computing modules and instruction modules in the reconfigurable chip bring great challenges to verification period and quality assurance. In order to reserve enough time for a large number of test cases, a module level verification environment adaptive to a reconfigurable chip needs to be quickly and effectively built, and the prior art cannot realize quick construction of the verification environment, so that verification of the reconfigurable chip is not facilitated.
Disclosure of Invention
The invention aims to provide a verification method and a verification platform for a reconfigurable chip, which solve the problem of long verification period of the reconfigurable chip and perform procedural control on the verification quality of the reconfigurable chip.
In one aspect of the present invention, a verification method for a reconfigurable chip is provided, which includes: and (4) according to the set format and the key field specification in the format setting, the text of the RTL top-level file is specified. And generating a verification environment framework according to the normalized RTL top-level file text. And verifying the reconfigurable chip through the generated verification environment framework.
In an embodiment of the verification method for the reconfigurable chip of the present invention, the method further includes: reading the initial RTL top file text. And dividing the initial RTL top file text into a plurality of sections of RTL top file texts.
In another embodiment of the verification method for the reconfigurable chip, the setting of the keywords in the format includes: a program start field, a program end field, an input field at the time of verification, and an output field at the time of verification. And verifying the matched clock information and reset information in the reconfigurable chip. And the output field during verification comprises pin information corresponding to the reconfigurable chip pin.
In another embodiment of the verification method of the reconfigurable chip of the present invention, the method includes: and inputting the normalized RTL top-level file text, the reference model library file, the simulator library file, the simulation script file and the general agent file into a verification platform generating unit to generate a verification environment framework.
In another embodiment of the verification method for the reconfigurable chip according to the present invention, the verification platform generation unit includes a plurality of setting generation directories of the verification files required for verifying the environment configuration. The set generation directory corresponds to set parameters of each functional module in the verification environment.
The verification method of the reconfigurable chip further comprises the following steps: and extracting corresponding key field contents from the text of the specified RTL top-level file according to the key fields. And generating verification files in a plurality of setting generation catalogues according to the content of the key fields.
In another embodiment of the verification method for a reconfigurable chip according to the present invention, the setting of the generation directory includes: the environment variable starts the script file, test case file and verifies the environment file.
In another aspect of the present invention, a verification platform for a reconfigurable chip is provided, including:
and the formatting unit is configured to normalize the text of the RTL top-level file according to the set format and the key fields in the format setting.
And the verification environment generating unit is configured to generate a verification environment frame according to the normalized RTL top-level file text.
A verification unit configured to verify the reconfigurable chip through the generated verification environment framework.
In another embodiment of the verification platform of the reconfigurable chip according to the present invention, the formatting unit is further configured to read an initial RTL top-level file text. And dividing the initial RTL top file text into a plurality of sections of RTL top file texts.
In another embodiment of the verification platform for reconfigurable chips according to the present invention, the setting of the keywords in the format includes: a program start field, a program end field, an input field at the time of verification, and an output field at the time of verification. And verifying the matched clock information and reset information in the reconfigurable chip. And the output field during verification comprises pin information corresponding to the reconfigurable chip pin.
The verification environment generation unit further includes: a verification platform generation unit and a verification environment framework.
And the verification environment generating unit is also configured to input the normalized RTL top-level file text, the reference model library file, the simulator library file, the simulation script file and the general agent file into the verification platform generating unit to generate a verification environment framework.
The verification platform generation unit comprises a plurality of setting generation catalogues of verification files required in verification environment configuration. The set generation catalog corresponds to the set parameters of each functional module in the verification environment.
The verification environment generation unit is also configured to extract corresponding key field contents from the normalized RTL top-level document text according to the key fields. And generating verification files in a plurality of setting generation directories according to the content of the key field.
The setting of the generation list includes: the environment variable starts a script file, a test case file and a verification environment file.
In another embodiment of the verification platform for the reconfigurable chip according to the present invention, the verification environment framework includes:
the device comprises a test case input unit, a virtual controller, a functional register model, a reference model, a comparison model, a plurality of reconfigurable processing units capable of processing various operation types and a plurality of input/output excitation driving modules.
The test case input unit is configured to receive a test case file.
The input of the virtual controller is connected with the test case input unit and receives the test case file from the test case input unit. The output of the virtual controller is connected with the reconfigurable processing unit and the functional register model.
The reconfigurable processing unit drives the verification unit through the input/output excitation driving module according to the processing information in the test case file, and verifies the reconfigurable chip. The output of the input/output excitation driving module is connected with the reference model and the comparison model. And sending input/output verification data to the reference model and the comparison model.
And the reconfigurable processing unit drives the verification unit to verify the reconfigurable chip to acquire processor verification data according to the processing information in the test case file.
And the output of the functional register model is connected with a reference model, and the reference model acquires reference operation information from the test case file.
And the reference model acquires reference data according to the reference operation information and the input/output verification data and outputs the reference data to the comparison model.
And the comparison model acquires the current verification data according to the input/output verification data and the processor verification data.
And the comparison model compares the reference data with the current verification data to obtain a verification result.
The characteristics, technical features, advantages and implementation manners of the verification method and the verification platform for the reconfigurable chip are further described in a clear and understandable manner by combining the drawings.
Drawings
Fig. 1 is a flow chart for explaining a verification method of a reconfigurable chip in one embodiment of the present invention.
Fig. 2 is a schematic diagram illustrating the components of the verification platform of the reconfigurable chip according to an embodiment of the present invention.
Fig. 3 is a schematic diagram illustrating a verification platform of a reconfigurable chip according to another embodiment of the present invention.
FIG. 4 is a flowchart illustrating the tool apparatus for verifying the platform of the reconfigurable chip according to another embodiment of the present invention.
FIG. 5 is an architectural block diagram illustrating a unified module-level verification environment in one embodiment of the invention.
Detailed Description
In order to more clearly understand the technical features, objects and effects of the present invention, embodiments of the present invention will now be described with reference to the accompanying drawings, in which the same reference numerals indicate the same or structurally similar but functionally identical elements.
"exemplary" means "serving as an example, instance, or illustration" herein, and any illustration, embodiment, or steps described as "exemplary" herein should not be construed as a preferred or advantageous alternative. For the sake of simplicity, the drawings only schematically show the parts relevant to the present exemplary embodiment, and they do not represent the actual structure and the true scale of the product.
In one aspect of the present invention, as shown in fig. 1, a verification method for a reconfigurable chip is provided, which includes:
and S101, normalizing the text of the RTL top file according to the set format and the key field in the format setting.
And S102, generating a verification environment frame according to the normalized RTL top-level file text.
And step S103, verifying the reconfigurable chip through the generated verification environment framework.
The verification method provided by the invention is used for modifying the top-level file of the RTL design by adding keywords with a specific format. By using the verification platform, module-level verification environments of different modules are created according to different specific design characteristics. The verification method of the invention enables the module-level verification environments of different modules to use a set of similar verification methodologies to refine the specific verification codes of the module. And the same simulation script is run to initiate eda simulation to check the simulation results. And the quality assurance of different modules of the reconfigurable chip is realized by using the same debugging and tracing means.
In an embodiment of the verification method for the reconfigurable chip of the present invention, the method further includes: and reading the text of the initial RTL top file. And dividing the initial RTL top file text into a plurality of sections of RTL top file texts.
In another embodiment of the verification method for the reconfigurable chip, the setting of the keywords in the format includes: a program start field, a program end field, an input field at the time of verification, and an output field at the time of verification. And verifying the matched clock information and reset information in the reconfigurable chip. And the output field comprises pin information corresponding to the reconfigurable chip pins during verification.
In another embodiment of the verification method of the reconfigurable chip of the present invention, the method includes: and inputting the normalized RTL top file text, the normalized reference model library file, the normalized simulator library file, the normalized simulation script file and the normalized general agent file into a verification platform generating unit to generate a verification environment framework.
In another embodiment of the verification method for the reconfigurable chip according to the present invention, the verification platform generation unit includes a plurality of setting generation directories of the verification files required for verifying the environment configuration. The set generation catalog corresponds to the set parameters of each functional module in the verification environment.
The verification method of the reconfigurable chip further comprises the following steps: and extracting corresponding key field contents from the normalized RTL top-level file text according to the key fields. And generating verification files in a plurality of setting generation catalogues according to the content of the key fields.
In another embodiment of the verification method for a reconfigurable chip according to the present invention, the setting of the generation directory includes: the environment variable starts a script file, a test case file and a verification environment file.
In another aspect of the present invention, as shown in fig. 2, there is provided a verification system of a reconfigurable chip, including:
a formatting unit 101 configured to specify RTL top level document text according to a set format and key fields in the format setting.
And the verification environment generating unit 201 is configured to generate a verification environment framework according to the specified RTL top-level file text.
A verification unit 301 configured to verify the reconfigurable chip by the generated verification environment framework.
In another embodiment of the verification system of the reconfigurable chip according to the present invention, the formatting unit 101 is further configured to read an initial RTL top-level file text. And dividing the initial RTL top file text into a plurality of sections of RTL top file texts.
In another embodiment of the verification system for a reconfigurable chip according to the present invention, the setting of the keywords in the format comprises: a program start field, a program end field, an input field at the time of verification, and an output field at the time of verification. And verifying the matched clock information and reset information in the reconfigurable chip. And the output field during verification comprises pin information corresponding to the reconfigurable chip pin.
The verification environment generation unit 201 further includes: a verification platform generation unit and a verification environment framework.
The verification environment generating unit 201 is further configured to input the normalized RTL top-level document text, the reference model library file, the simulator library file, the simulation script file, and the general agent file into the verification platform generating unit to generate the verification environment framework.
The verification platform generation unit comprises a plurality of setting generation catalogues of verification files required in verification environment configuration. The set generation directory corresponds to set parameters of each functional module in the verification environment.
The verification environment generating unit 201 is further configured to extract corresponding key field contents from the normalized RTL top-level document text according to the key field. And generating verification files in a plurality of setting generation catalogues according to the content of the key fields.
The setting of the generation list includes: the environment variable starts a script file, a test case file and a verification environment file.
In still another embodiment of the verification system of the reconfigurable chip according to the present invention, the verification environment framework includes:
the device comprises a test case input unit, a virtual controller, a functional register model, a reference model, a comparison model, a plurality of reconfigurable processing units capable of processing various operation types and a plurality of input/output excitation driving modules.
The test case input unit is configured to receive a test case file.
The input of the virtual controller is connected with the test case input unit and receives the test case file from the test case input unit. The output of the virtual controller is connected with the reconfigurable processing unit and the functional register model.
The reconfigurable processing unit drives the verification unit 301 through the input/output excitation driving module according to the processing information in the test case file, and verifies the reconfigurable chip. The output of the input/output excitation driving module is connected with the reference model and the comparison model. And sending input/output verification data to the reference model and the comparison model.
The reconfigurable processing unit drives the verification unit 301 to verify that the reconfigurable chip obtains the processor verification data according to the processing information in the test case file.
And the output of the functional register model is connected with a reference model, and the reference model acquires reference operation information from the test case file.
And the reference model acquires reference data according to the reference operation information and the input/output verification data and outputs the reference data to the comparison model.
And the comparison model acquires the current verification data according to the input/output verification data and the processor verification data.
And the comparison model compares the reference data with the current verification data to obtain a verification result.
In one embodiment of the verification method of the reconfigurable chip, the platform for realizing the verification method of the reconfigurable chip comprises a set of tool devices realized by using a script language, keywords in a specific format are added as input files according to top-level files designed by RTL, and module-level verification environments are quickly created for different modules of the reconfigurable chip.
Before the tool device is operated, a platform needs to prepare a large number of verification code library files required by the verification of the reconfigurable chip.
The verification code base file needs a simulator file of a reconfigurable chip. A reference model is required. There is a need for a sophisticated proxy component that can reconfigure the common interfaces of the relevant modules of the chip. Before the tool device is operated, the platform needs to start a simulation script.
In another embodiment of the verification method of the reconfigurable chip, the top-level file of the RTL design is modified, and keywords with specific formats are added. Each row of the RTL design top level file contains the top level signals of the design with direction information and bit width information.
These top-level signals are divided into a number of different groups depending on whether or not they are associated with each other. And adding a row at the top and the bottom of each group respectively, wherein the row contains the keywords verify start, verify end, clk and reset information.
If a general proxy component can be used, the related information of the proxy component is added in the interface signal of the group.
In still another embodiment of the verification method of the reconfigurable chip of the present invention, the input file of claim 2 is input, and a module-level verification environment framework of the reconfigurable chip is quickly created.
When it is desired to create a module-level verification environment for different modules, only the specific input file of claim 2 needs to be modified.
In another embodiment of the verification method of the reconfigurable chip, the directory structure and the unified file of the verification environment are named uniformly.
In another embodiment of the verification method for the reconfigurable chip, the verification environment only needs to add the test case file and the test case file list, and does not need to add other files.
According to different design inputs, complete construction of the verification environment can be completed only by modifying the file contents in the env directory and the uvc directory.
In the verification environment, the completeness of the test case of the module-level verification can be realized only by adding and modifying files in the testcase directory.
The simulation script is directly started, and the collection of single test case, regression test case and coverage rate test can be realized.
The intermediate file in the simulation process is independently stored with another directory, so that the original verification environment is not modified, and the uploading of the database is facilitated.
In one embodiment of the verification method of the reconfigurable chip, the invention provides a verification platform tool device, and the verification platform can rapidly create a unified templated verification environment framework and verification thinking of each module for the reconfigurable chip. The verification method of the reconfigurable chip can be realized. The verification platform adds keywords with a specific format to the RTL register conversion level circuit design according to the top level file of the RTL register conversion level circuit design, and the keywords are used as input files, so that a module level verification environment can be quickly established. According to different front end designs, the contents of the input files in specific formats are changed, and different module-level verification environments can be created.
The special verification library file of the reconfigurable chip of the verification platform is designed in a modularized platform manner, and convenience can be brought to the verification platform
The library file is easy to use and continuously expand and modify.
And (4) preparing a reference model of an rcvc large-quantity operator, a reference model of an rccn convolutional neural network, a reference model of a pe operator and the like of the reconfigurable chip by verifying the library file.
The verification library file prepares the proxy component of the external interface axi, ahb, apb of the reconfigurable chip.
The validation library file is prepared with the proxy components and models of fspm, dspm, etc.
The verification library file prepares the simulator of the reconfigurable chip.
The invention also provides a method for improving the top-level file of RTL design, which is convenient for the verified platform tool device to be used as an input file.
The top level documentation for the RTL design is modified as follows:
1. each row of the RTL design file contains the top-level signal of the design with direction information and bit width information, which is the valid row, valid information.
2. The module row of the RTL design is the valid row and is the valid information.
3. These signals in (1) above are divided into different groups depending on whether or not they have associated protocol relationships. And adds the keywords verify start, clk, reset information to the top row of each group. In the bottom row of each group, the keyword verify end is added.
4. The verify start key part in (iii) will add the relevant information of the proxy component if it is supported by the mature proxy component already in 1.
The last step of this embodiment of the invention:
starting the verification platform tool device of the invention, inputting the modified RTL design top-level file of the invention, and a quickly created module-level verification environment is ready.
In the invention, the RTL design top-level input file of the reconfigurable verification platform reconstructed by the specific method plays an important role. The file is key information acquired by a verification platform tool device of the reconfigurable chip and controls the flow jump executed by the platform device. The related key word information of the agent component added in the file is also key information acquired by the platform device, and the related code of the agent component can be directly preset in the created module-level verification environment.
The benefits of the invention are as follows:
the module-level verification environment of the reconfigurable chip can be quickly created, and the building time of the module-level verification environment of each module can be shortened by 10%. For the utilization of top-level files of RTL design, the upgrading and reconstruction of keywords are added, and the whole project time can be saved. And (3) creating module-level verification platforms of different reconfigurable chips, and realizing the verification only by changing the top-level file of the RTL design.
The created module-level verification environment has a unified standard directory structure, standard file naming rules, a standard verification environment process and a standard eda process script, so that communication among project group members is easy. The created module-level verification environment has unified testplan to manage the test cases, so that the project management personnel can easily manage and control the verification process. By applying the platform, even a low-level primary verifier can create a standardized verification environment, so that the verification quality of the module is basically guaranteed.
In one embodiment of the verification method for the reconfigurable chip, the specific implementation process is as follows:
step S201, modifying a top-level file of the RTL design, an example of which is shown in fig. 3.
Wherein the first row of module information can be extracted for the instantiated name at the top level of the module level verification environment, and the module is separated from the following information by a space. The signal with the Input and output information can be extracted by the tool for use in generating a verification component for the module-level verification environment.
The keywords verify start and verify end are separated by a space, the immediately following ahb is the directory name of the verification component, the keywords clk and reset are separated by a colon, and the colon is followed by the clock and reset signals used in the actual verification environment.
There may be many such groups consisting of verify start and verify end.
All signals of the top layer of the RTL design are surrounded by verify start and verify end.
Step S202, library file preparation required by the reconfigurable chip verification platform:
this library file is an integral part of the verification platform, which can be continuously enriched and optimized.
The main components of the library files required for verification are not limited to the set of agent files of the common interface component associated with the design, including reference model and simulator files associated with the design.
The reference model in the chip design comprises a general convolutional neural network RCCN, an RCVC module, a depthwise convolution, reference models comprising all PE operators and the like, which are stored in respective exclusive directories.
The simulator of the processor in the chip design is stored in a special directory.
The set of agents for the universal interface associated with the chip design, this sequence component and the list of agents containing ahb, axi, apb of the amba bus, are stored in a proprietary named directory.
The memory model of the chip design, spm, fspm, dspm and other proxy files are stored in a specially named directory.
Step S203, a platform for implementing the verification method of the reconfigurable chip is developed.
Step S204, ready, starts the tool apparatus in step S203 to start operating.
The modified code for the top-level input file of the RTL design is as follows:
thus, a complete tool device runs out, and a complete module level verification environment is created, the directory structure of which is shown in FIG. 5.
If the verification environment of different module levels is created, only the step in step S201 in the implementation process needs to be modified.
It should be understood that although the present description is described in terms of various embodiments, not every embodiment includes only a single embodiment, and such description is for clarity purposes only, and those skilled in the art will recognize that the embodiments described herein as a whole may be suitably combined to form other embodiments as will be appreciated by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. A verification method of a reconfigurable chip is characterized by comprising the following steps:
normalizing RTL top-level file text according to a set format and a key field in format setting;
generating a verification environment frame according to the normalized RTL top-level file text;
and verifying the reconfigurable chip through the generated verification environment framework.
2. The verification method of the reconfigurable chip according to claim 1, further comprising:
reading an initial RTL top file text;
and dividing the initial RTL top file text into a plurality of sections of RTL top file texts.
3. The verification method of the reconfigurable chip according to claim 1, wherein the setting of the key in the format comprises: a program start field, a program end field, a verification input field and a verification output field; verifying the matched clock information and reset information in the reconfigurable chip; and the output field during verification comprises pin information corresponding to the reconfigurable chip pins.
4. The verification method of the reconfigurable chip according to claim 1, comprising:
and inputting the normalized RTL top-level file text, the reference model library file, the simulator library file, the simulation script file and the general agent file into a verification platform generating unit to generate a verification environment framework.
5. The verification method of the reconfigurable chip according to claim 4, wherein the verification platform generation unit includes a setting generation directory of verification files required for configuration of a plurality of verification environments; the setting generation catalog corresponds to the setting parameters of each functional module in the verification environment;
the verification method of the reconfigurable chip further comprises the following steps:
extracting corresponding key field contents from the normalized RTL top-level file text according to the key fields;
and generating the verification file in a plurality of setting generation catalogues according to the content of the key field.
6. The verification method of the reconfigurable chip according to claim 5, wherein the setting generation directory includes: the environment variable starts a script file, a test case file and a verification environment file.
7. A verification platform of a reconfigurable chip, comprising:
the formatting unit is configured to standardize the RTL top-level file text according to a set format and key fields in format setting;
the verification environment generating unit is configured to generate a verification environment frame according to the normalized RTL top-level file text;
a verification unit configured to verify the reconfigurable chip through the generated verification environment framework.
8. The verification platform of the reconfigurable chip according to claim 7, wherein the formatting unit is further configured to read an initial RTL top-level file text; and dividing the initial RTL top file text into a plurality of sections of RTL top file texts.
9. The verification platform of the reconfigurable chip of claim 7, wherein the keywords in the set format comprise: a program start field, a program end field, a verification input field and a verification output field; verifying the matched clock information and reset information in the reconfigurable chip; the output field during verification comprises pin information corresponding to the reconfigurable chip pin;
the verification environment generation unit further includes: a verification platform generation unit and a verification environment framework;
the verification environment generating unit is also configured to input the normalized RTL top-level file text, the reference model library file, the simulator library file, the simulation script file and the general agent file into the verification platform generating unit to generate the verification environment framework;
the verification platform generation unit comprises a plurality of setting generation catalogues of verification files required by verification environment configuration; the setting generation catalog corresponds to the setting parameters of each functional module in the verification environment;
the verification environment generation unit is also configured to extract corresponding key field contents from the normalized RTL top-level file text according to the key fields; generating the verification file in a plurality of setting generation directories according to the content of the key field;
the setting generation directory includes: the environment variable starts a script file, a test case file and a verification environment file.
10. The verification platform of the reconfigurable chip of claim 9, wherein the verification environment framework comprises: the system comprises a test case input unit, a virtual controller, a functional register model, a reference model, a comparison model, a plurality of reconfigurable processing units capable of processing various operation types and a plurality of input/output excitation driving modules;
the test case input unit is configured to receive the test case file;
the input of the virtual controller is connected with the test case input unit and receives a test case file from the test case input unit; the output of the virtual controller is connected with the reconfigurable processing unit and the functional register model;
the reconfigurable processing unit drives the verification unit through the input/output excitation driving module according to the processing information in the test case file, and verifies the reconfigurable chip; the output of the input/output excitation driving module is connected with the reference model and the comparison model; sending input/output verification data to the reference model and the comparison model;
the reconfigurable processing unit drives the verification unit to verify the reconfigurable chip to acquire processor verification data according to the processing information in the test case file;
the output of the functional register model is connected with the reference model, and the reference model acquires reference operation information from the test case file;
the reference model acquires reference data according to the reference operation information and the input/output verification data and outputs the reference data to the comparison model;
the comparison model acquires current verification data according to the input/output verification data and the processor verification data;
and the comparison model compares the reference data with the current verification data to obtain a verification result.
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| CN116719729A (en) * | 2023-06-12 | 2023-09-08 | 南京金阵微电子技术有限公司 | Universal verification platform, universal verification method, medium and electronic equipment |
| CN116719729B (en) * | 2023-06-12 | 2024-04-09 | 南京金阵微电子技术有限公司 | Universal verification platform, universal verification method, medium and electronic equipment |
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