CN115913137A

CN115913137A - Transimpedance amplifier integrating automatic reset and rapid burst response

Info

Publication number: CN115913137A
Application number: CN202211449174.7A
Authority: CN
Inventors: 余长亮; 冯峻峰; 柴焦
Original assignee: Wuhan Fisilink Microelectronics Technology Co Ltd
Current assignee: Wuhan Fisilink Microelectronics Technology Co Ltd
Priority date: 2022-11-18
Filing date: 2022-11-18
Publication date: 2023-04-04

Abstract

The invention relates to a transimpedance amplifier integrating automatic reset and quick burst response, which comprises a transimpedance amplifier front-end circuit, a reset signal automatic generation circuit and an adjustable low-pass filter circuit, wherein the reset signal automatic generation circuit is communicated with the transimpedance amplifier front-end circuit; the adjustable low-pass filter circuit is communicated with an output signal of the transimpedance amplifier front-end circuit and is communicated with a reset signal RST and an inverted reset signal RSTB generated by the reset signal automatic generation circuit; the adjustable low-pass filter circuit is used for controlling an MOS variable resistor and an MOS switch arranged in the adjustable low-pass filter circuit according to the reset signal RST and the reverse reset signal RSTB and forming a low-pass filter with adjustable cut-off frequency, and signals output by the low-pass filter with adjustable cut-off frequency accord with the mean interval of voltage signals output by the front-end circuit of the transimpedance amplifier. The MCU is not required to provide an external RESET signal to complete the quick burst response of chips such as a trans-impedance amplifier, a limiting amplifier and a CDR.

Description

Transimpedance amplifier integrating automatic reset and rapid burst response

Technical Field

The invention relates to the field of semiconductor integrated circuit technology and optical communication, in particular to a transimpedance amplifier integrating automatic reset and rapid burst response.

Background

In an optical access network, downlink traffic data (traffic data transmitted from an OLT to an ONU) is transmitted in a broadcast form, and uplink traffic data (traffic data transmitted from an ONU to an OLT) is transmitted in a time division multiplex burst. In order to increase the effective data amount in the upstream burst data packet, the burst response time of an optical receiving component on the OLT side is usually required to be reduced to several hundred ns, but the current commercial trans-impedance amplifier (TIA) cannot meet the burst response time requirement even if working independently without coordination of an external control signal, and the problems of mutual influence of upstream signals of different ONUs and data transmission failure are easily caused. To address this problem, in the related art, an internal MCU provides a RESET signal to a transimpedance amplifier inside a burst mode optical receiving component and a burst mode limiting amplifier and CDR (Clock and Data recovery, clock and Data restorer) on a PCB of an OLT optical module, and before each burst signal packet arrives, the RESET signal is sent to allow the transimpedance amplifier to complete a RESET operation quickly. But this solution increases the complexity of the operation of the OLT optical module to some extent.

In order to reduce the complexity and cost of system implementation, in other technologies, the uplink service transmission adopts a time division multiplexing burst mode, that is, different ONU uplink data are respectively allocated in different complementary overlapping time periods in the time domain to perform uplink service data transmission. This requires that the OLT optical module internal upstream signal receiving channel link (including optical receiving components, limiting amplifiers and CDRs, etc.) must have fast burst response capability and correctly receive the upstream traffic data sent by the different ONUs. An OLT optical module product in the related art generates a matched RESET signal through an internal MCU according to a time slot interval allocated by a system to each subordinate ONU, and outputs the RESET signal to each component and chip (including an optical receiving component, a limiting amplifier, a CDR, and the like) on an uplink signal receiving channel link, and controls a gap (guard time) between uplink data packets of the ONU by each component and chip on the uplink signal receiving channel link to quickly complete a RESET operation and a fast response burst signal. However, in the scheme, the difficulty and the realizability of the conventional trans-impedance amplifier, limiting amplifier, CDR and other chips for realizing self rapid burst response need to be considered, and the complexity and the difficulty of the operation of the OLT optical module are increased to a certain extent.

Disclosure of Invention

The embodiment of the invention provides a transimpedance amplifier integrating automatic RESET and rapid burst response, which does not need an MCU (microprogrammed control unit) to provide an external RESET signal to complete rapid burst response of chips such as the transimpedance amplifier, a limiting amplifier, a CDR (clock recovery register) and the like, and can reduce the working complexity and the realization difficulty of an OLT (optical line terminal) optical module.

In one aspect, an embodiment of the present invention provides a transimpedance amplifier integrating an automatic reset and a fast burst response, including:

a transimpedance amplifier front-end circuit for converting a single-ended input current signal to a single-ended output voltage signal;

the automatic reset signal generating circuit is communicated with the transimpedance amplifier front-end circuit and is used for generating a digital intensity signal after time delay according to the intensity of a voltage signal output by the transimpedance amplifier front-end circuit and automatically generating a reset signal RST and an inverted reset signal RSTB through an exclusive-OR gate and an inverter;

the adjustable low-pass filter circuit is communicated with an output signal of the transimpedance amplifier front-end circuit and is communicated with a reset signal RST and an inverted reset signal RSTB generated by the reset signal automatic generation circuit;

the adjustable low-pass filter circuit is used for controlling an MOS variable resistor and an MOS switch arranged in the adjustable low-pass filter circuit according to the reset signal RST and the reverse reset signal RSTB and forming a low-pass filter with adjustable cut-off frequency, and signals output by the low-pass filter with the adjustable cut-off frequency accord with the mean interval of voltage signals output by the front-end circuit of the transimpedance amplifier.

In some embodiments, the reset signal auto-generation circuit further comprises:

the signal intensity monitoring circuit is communicated with the transimpedance amplifier front-end circuit and is used for outputting a corresponding analog intensity signal according to the intensity of the voltage signal output by the transimpedance amplifier front-end circuit;

the signal intensity judgment circuit is communicated with the output end of the signal intensity monitoring circuit and is used for carrying out digital judgment on the analog intensity signal output by the signal intensity monitoring circuit and outputting a digital intensity signal according to a judgment result;

the delay circuit is communicated with the output end of the signal intensity judging circuit and is used for outputting a digital intensity delay signal corresponding to the digital intensity signal output by the signal intensity judging circuit;

an exclusive-or gate, an input end of which is connected to the output end of the signal strength decision circuit and the output end of the delay circuit, respectively, and which is configured to perform exclusive-or processing on the received digital strength signal and the received digital strength delay signal to obtain a reset signal RST;

and the input end of the inverter is communicated with the output end of the exclusive-OR gate, and the inverter is used for carrying out inversion operation on the reset signal RST output by the exclusive-OR gate to obtain an inverted reset signal RSTB.

In some embodiments, the delay circuit comprises:

the clock generating circuit is used for automatically generating and outputting a clock signal according to a preset frequency;

and the input end of the D trigger is communicated with the output end of the signal intensity judging circuit and is used for generating a digital intensity delay signal corresponding to the digital intensity signal output by the signal intensity judging circuit under the control of the clock signal.

In some embodiments, the signal strength monitoring circuit comprises: the circuit comprises an NMOS (N-channel metal oxide semiconductor) tube MN (30), an NMOS tube MN (31), an NMOS tube MN (32), an NMOS tube MN (33), an NMOS tube MN (34), a current source Ibias, a triode Q (31), a triode Q (32), a triode Q (33), a triode Q (34), a triode Q (35), a resistor R (31), a resistor R (32), a resistor R (33), a resistor R (34), a resistor R (35), a resistor R (36), a resistor R (37), a capacitor C (31) and a differential-to-single-ended amplifier;

the first port of the current source Ibias is connected with a power supply VCC, and the second port of the current source Ibias is simultaneously connected with an NMOS tube MN (30), an NMOS tube MN (31), an NMOS tube MN (32), an NMOS tube MN (33) and an NMOS tube MN (34);

the source electrode of the NMOS tube MN (30) is grounded, and the drain electrode and the grid electrode of the NMOS tube MN are connected with the second port of the current source Ibias;

the source electrode of the NMOS tube MN (31) is grounded, the drain electrode of the NMOS tube MN is simultaneously connected with the emitter electrode of the triode Q (31), the first port of the capacitor C (31) and the first port of the resistor R (33), and the grid electrode of the NMOS tube MN (31) is connected with the second port of the current source Ibias;

the source electrode of the NMOS tube MN (32) is grounded, the drain electrode of the NMOS tube MN is simultaneously connected with the emitter electrode of the triode Q (32), the second port of the capacitor C (31) and the second port of the resistor R (33), and the grid electrode of the NMOS tube MN (32) is connected with the second port of the current source Ibias;

the source electrode of the NMOS tube MN (33) is grounded, and the grid electrode of the NMOS tube MN is connected with the second port of the current source Ibias;

the source electrode of the NMOS tube MN (34) is grounded, and the grid electrode of the NMOS tube MN is connected with the second port of the current source Ibias;

the base electrode of the triode Q (31) is connected with an input port INN, and the collector electrode of the triode Q (31) is simultaneously connected with the first port of the resistor R (31), the base electrode of the triode Q (33) and the first port of the resistor R (34);

the base electrode of the triode Q (32) is connected with the input port INP, and the collector electrode of the triode Q (32) is simultaneously connected with the first port of the resistor R (32), the base electrode of the triode Q (34) and the first port of the resistor R (35);

the collectors of the triode Q (33) and the triode Q (34) are both connected with a power supply VCC, and the emitter of the triode Q (33) is in short circuit with the emitter of the triode Q (34) and then is connected with the drain of the NMOS transistor MN (33) and the first input port of the differential-to-single-ended amplifier;

the collector electrode of the triode Q (35) is connected with a power supply VCC, and the emitter electrode of the triode Q is connected with a first port of the resistor R (36);

the second ports of the resistor R (31) and the resistor R (32) are both connected with a power supply VCC;

the second port of the resistor R (34) and the second port of the resistor R (35) are connected with the base electrode of the triode Q (35) after being in short circuit,

a second port of the resistor R (36) is simultaneously connected with a second input port of a differential input pair of the differential-to-single-ended amplifier, a drain electrode of the NMOS transistor MN (34) and a first port of the resistor R (37);

the second port of the resistor R (37) is connected with the output end of the differential-to-single-ended amplifier;

the output end of the front-end circuit of the transimpedance amplifier is connected with one port of the input end of the signal intensity judgment circuit through a resistor R (21), and the other port of the input end of the signal intensity judgment circuit is connected with a fixed reference voltage;

and the output end of the differential-to-single-ended amplifier is used for outputting an analog intensity signal corresponding to the intensity of the voltage signal output by the transimpedance amplifier front-end circuit.

In some embodiments, the signal strength decision circuit comprises: an NMOS transistor MN (41), a PMOS transistor MP (42), a PMOS transistor MP (43) and an inverter (41);

the grid electrode of the NMOS transistor MN (41) is connected with the output end of the signal intensity monitoring circuit, the grid electrode of the PMOS transistor MP (41) and the grid electrode of the PMOS transistor MP (42), the source electrode of the NMOS transistor MN41 is grounded, and the drain electrode of the NMOS transistor MN41 is simultaneously connected with the drain electrode of the PMOS transistor MP (41), the grid electrode of the PMOS transistor MP (43) and the input port of the phase inverter (41);

the source electrode of the PMOS tube MP (41) is connected with the drain electrode of the PMOS tube MP (42) and the source electrode of the PMOS tube MP (43);

the source electrode of the PMOS tube MP (42) is connected with a power supply VCC;

the drain electrode of the PMOS pipe MP (43) is grounded;

the output of the inverter (41) outputs the digital intensity signal.

In some embodiments, the adjustable low-pass filter circuit comprises:

the resistor R (21) is connected with a resistor R (22), a first port of the resistor R (21) is communicated with the output end of the transimpedance amplifier front-end circuit, a second port of the resistor R (21) is communicated with a source electrode of the MOS variable resistor M (22) and a first port of the resistor R (22), and the resistor R (21) is used for reducing the influence of parasitic parameters of the resistor R (22) on the bandwidth of the output end of the transimpedance amplifier front-end circuit;

a MOS variable resistor M (22), the grid of which is communicated with the output end of the exclusive-OR gate and the drain of which is communicated with the second port of the resistor R (22), wherein the MOS variable resistor M (22) is used for changing the high-low state of the resistance value according to the reset signal RST output by the exclusive-OR gate;

the source of the MOS switch M (21) is grounded, the grid of the MOS switch M is communicated with the output end of the inverter, the drain of the MOS switch M is communicated with the second port of the capacitor C (21), and the MOS switch M (21) is used for changing the on-off state of the MOS switch according to an inverted reset signal RSTB output by the inverter;

a capacitor C (21) having a first port in communication with a second port of the resistor R (22);

a capacitor C (22) having a first port connected to a second port of the resistor R (22) and a second port connected to ground;

the resistor R (22), the MOS variable resistor M (22), the MOS switch M (21), the capacitor C (21) and the capacitor C (22) are used for forming the low-pass filter with the adjustable cut-off frequency according to the reset signal RST and the reversed-phase reset signal RSTB and enabling an output signal of a second port of the resistor R (22) to be in accordance with an average value interval of an output voltage signal of the transimpedance amplifier front-end circuit.

In a second aspect, a differential limiting amplifier circuit integrating automatic reset and fast burst response, includes:

the automatic reset signal generating circuit is used for generating a delayed digital intensity signal according to the intensity of the output voltage signal of the differential limiting amplifier and automatically outputting a reset signal RST and an inverted reset signal RSTB through an exclusive-OR gate and an inverter;

the adjustable high-pass filter circuit is connected with the input end signal INP and the input end signal INN and is communicated with the reset signal RST and the reverse reset signal RSTB output by the reset signal automatic generation circuit;

the adjustable high-pass filter circuit is used for controlling a variable capacitor and an MOS (metal oxide semiconductor) tube arranged in the adjustable high-pass filter circuit according to the reset signal RST and the reverse reset signal RSTB and forming a high-pass filter with adjustable cut-off frequency, and signals output by the high-pass filter with adjustable cut-off frequency accord with the signal rate characteristics and the amplitude characteristics of input end signals INP and INN;

and the input end of the differential limiting amplifier is communicated with the output end of the high-pass filter circuit.

In a third aspect, an embodiment of the present invention further provides a differential limiting amplifier circuit integrating automatic reset and fast burst response, where the differential limiting amplifier circuit is characterized in that,

the adjustable high-pass filter circuit comprises a variable capacitor C (611), a capacitor C (612), an MOS transistor M (61), a variable capacitor C (621), a capacitor C (622), an MOS transistor M (62) and a resistor R (61);

a first port of the variable capacitor C (611) is connected to the input end signal INN and a first port of the capacitor C (612), a second port of the variable capacitor C (611) is connected to the source of the MOS transistor M (61), a first port of the resistor R (61) and a first input end of the differential input pair of the differential limiting amplifier, and a control end of the variable capacitor C (611) is connected to the reset signal RST;

the second port of the capacitor C (612) is connected to the drain of the MOS transistor M (61), and the gate of the MOS transistor M (61) is connected to the inverted reset signal RSTB;

a first port of the variable capacitor C (621) is connected to the input terminal signal INP and a first port of the capacitor C (622) at the same time, a second port of the variable capacitor C (621) is connected to the source of the MOS transistor M (62), a second port of the resistor R (61), and a second input terminal of the differential input pair of the differential limiting amplifier, and a control terminal of the variable capacitor C (621) is connected to the reset signal RST;

the second port of the capacitor C (622) is connected to the drain of the MOS transistor M (62), and the gate of the MOS transistor M (62) is connected to the inverted reset signal RSTB.

the input end of the signal intensity monitoring circuit is communicated with the output signal of the differential limiting amplifier and is used for outputting a corresponding analog intensity signal according to the intensity of the output signal of the differential limiting amplifier;

the delay circuit is communicated with the output end of the signal strength judging circuit and is used for outputting a digital strength delay signal corresponding to the digital strength signal output by the signal strength judging circuit;

In some embodiments, an output buffer stage is further communicated between the output end of the differential limiting amplifier and the input end of the signal strength monitoring circuit, and a pair of differential output ends of the differential limiting amplifier is connected to a pair of differential input ends of the output buffer stage, and a pair of differential output ends of the output buffer stage is connected to a pair of differential input ends of the signal strength monitoring circuit.

The embodiment of the invention provides a transimpedance amplifier integrating automatic reset and quick burst response. The reset signal can be generated in the chip to realize quick reset and quick response to burst data signals, and the method can be applied to chips such as trans-impedance amplifiers, limiting amplifiers and CDRs in the light receiving assembly. By adopting the automatic RESET and rapid burst response circuit provided by the embodiment of the invention, the MCU is not required to provide an external RESET signal to complete rapid burst response of chips such as a trans-impedance amplifier, a limiting amplifier, a CDR and the like, so that the working complexity and the realization difficulty of an OLT optical module can be reduced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic circuit diagram of a transimpedance amplifier integrating automatic reset and fast burst response according to an embodiment of the present invention;

FIG. 2 is a signal strength monitoring circuit according to an embodiment of the present invention;

fig. 3 is a circuit for determining signal strength according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a transimpedance amplifier integrating automatic reset and fast burst response according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a circuit structure of a delay unit according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a differential amplitude limiting amplifying circuit integrating automatic reset and fast burst response according to an embodiment of the present invention;

fig. 7 is a simulation result diagram of the transimpedance amplifier integrating the automatic reset and the fast burst response according to the embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.

As shown in fig. 1, an embodiment of the present invention provides a transimpedance amplifier structure integrating automatic reset and fast burst response, including:

the adjustable low-pass filter circuit is used for controlling an MOS variable resistor and an MOS switch arranged in the adjustable low-pass filter circuit according to the reset signal RST and the reverse reset signal RSTB and forming a low-pass filter with adjustable cut-off frequency, and signals output by the low-pass filter with adjustable cut-off frequency accord with the mean interval of voltage signals output by the front-end circuit of the transimpedance amplifier.

It should be noted that, as shown IN fig. 1, an input port IN of the front-end circuit of the transimpedance amplifier, that is, an input port of the transimpedance amplifier, is connected to an output port of the external photodetector.

As shown in fig. 1, the transimpedance amplifier with integrated automatic reset and fast burst response provided in this embodiment further includes a single-ended to differential amplifier, a differential amplifier, and an output buffer stage; the first input port of the differential input end of the single-ended-to-differential amplifier is communicated with the output end of the front-end circuit of the transimpedance amplifier and can be used for converting a single-ended voltage signal output by the transimpedance amplifier into a differential voltage signal; a pair of input ends of the differential amplifier is communicated with the output end of the single-ended-to-differential amplifier, and a pair of output ends of the differential amplifier is communicated with a pair of input ends of the output buffer stage; the differential amplifier is mainly used for amplifying differential voltage signals output by the single-ended-to-differential amplifier, and the output buffer stage is used for realizing an output impedance matching function and providing a certain output voltage signal amplitude.

It can be understood that, by using the automatic reset and fast burst response circuit provided by the embodiment of the present invention, a reset signal can be generated in a chip by itself to implement fast reset and fast response to a burst data signal, and the circuit can be applied to chips such as a transimpedance amplifier, a limiting amplifier, and a CDR in an optical receiving component. The MCU is not required to provide an external RESET signal to complete the rapid burst response of chips such as a trans-impedance amplifier, a limiting amplifier and a CDR, and the working complexity and the realization difficulty of an OLT optical module can be reduced.

In some embodiments, the reset signal automatic generation circuit further comprises:

the input end of the exclusive-or gate is respectively connected with the output end of the signal strength judging circuit and the output end of the delay circuit, and the exclusive-or gate is used for carrying out exclusive-or processing on the received digital strength signal and the received digital strength delay signal to obtain a reset signal RST;

It will be appreciated that the above-described,as shown in FIG. 1, the signal strength monitoring circuit can be used to monitor the output voltage signal OUT of the transimpedance amplifier front-end circuit _front1 And outputs a corresponding analog intensity signal SI; the signal intensity judgment circuit can be used for carrying out digital judgment on the analog intensity signal SI output by the signal intensity monitoring circuit, and when the intensity signal SI is larger than or equal to a certain value, the output digital intensity signal DSI is at a high level, otherwise, the output digital intensity signal DSI is at a low level.

As shown in fig. 1, in some embodiments, the delay circuit includes:

It should be noted that, the clock generating circuit is used for automatically generating and outputting a clock signal CLK, and the frequency thereof may be generally selected from about 50 to 200 MHz; the D flip-flop can generate a digital strength delay signal Q _ DSI with delay relative to the digital strength signal DSI under the control of the clock signal CLK;

in some embodiments, as shown in fig. 4, the clock generation circuit and the D flip-flop may be replaced by a delay, and the output of the delay is a delayed digital strength signal Q _ DSI, which is connected to one input of the xor gate. The delayer may have a plurality of digital input control ports for controlling the amount of delay time generated by the delayer, and as shown in fig. 5, K digital input control ports TD1 and td2.

In a specific embodiment, the schematic circuit structure of the delay device shown in fig. 5 is a multistage cascade controllable delay device based on an inverter delay unit with digital switch control, where NMOS transistors MN521, MN5211 and PMOS transistor MP521 are the first inverter delay unit, NMOS transistors MN522, MN5221 and PMOS transistor MP522 are the second inverter delay unit, and NMOS transistors MN52K, MN52K1 and PMOS transistor MP52K are the kth inverter delay unit. The internal components and connections of the K inverter delay cells are the same.

Taking the first inverter delay cell as an example, the internal devices and connection relationships are as follows: the gate of the NMOS transistor MN521 is an input terminal, and is connected to the gate of the PMOS transistor MP521 and the source of the NMOS switch transistor NM 5211; the drain electrode of the NMOS tube MN521 is an output electrode and is connected with the drain electrode of the PMOS tube MP521 and the drain electrode of the NMOS switch tube NM 5211; the source electrode of the NMOS pipe MN521 is grounded; the source electrode of the PMOS pipe MP521 is connected with a power supply VCC; the gate of the NMOS switch NM5211 is the delay control terminal TD1. If the delay control end TD1 is low, the NMOS switch tube NM5211 is turned off, the inverter delay unit composed of the NMOS tube MN521 and the PMOS tube MP521 is in a working state, and the delay of the output end signal of the inverter delay unit relative to the input end signal thereof is determined by the characteristics of the inverter; if the delay control terminal TD1 is high, the NMOS switch tube NM5211 is turned on, and the input signal of the inverter delay unit is directly transmitted to the output terminal of the inverter delay unit through the turned-on NMOS switch tube NM 5211. The input end of the first phase inverter delay unit is the input end of the multistage cascade controllable delayer, the output end of the Kth phase inverter delay unit is the output end of the multistage cascade controllable delayer, and the output end of the (K-1) th phase inverter delay unit is connected with the input end of the Kth phase inverter delay unit.

It should be noted that the NMOS switch tube NM5211 switch must be a high-speed switch unit, which may be a high-speed NMOS switch tube, and it needs to be a switch with small size and fast response speed, and can complete fast on and off according to the gate control voltage; the switch can also be a switch formed by connecting a high-speed NMOS and a PMOS in parallel, or other high-speed switch circuits.

As shown in fig. 2, in some embodiments, the signal strength monitoring circuit comprises: the circuit comprises an NMOS tube MN30, an NMOS tube MN31, an NMOS tube MN32, an NMOS tube MN33, an NMOS tube MN34, a current source Ibias, a triode Q31, a triode Q32, a triode Q33, a triode Q34, a triode Q35, a resistor R31, a resistor R32, a resistor R33, a resistor R34, a resistor R35, a resistor R36, a resistor R37, a capacitor C31 and a differential-to-single-ended amplifier.

The first port of the current source Ibias is connected with a power supply VCC, and the second port of the current source Ibias is simultaneously connected with an NMOS tube MN30, an NMOS tube MN31, an NMOS tube MN32, an NMOS tube MN33 and an NMOS tube MN34;

the source electrode of the NMOS tube MN30 is grounded, and the drain electrode and the grid electrode of the NMOS tube MN are connected with the second port of the current source Ibias;

the source electrode of the NMOS tube MN31 is grounded, the drain electrode of the NMOS tube MN31 is simultaneously connected with the emitter electrode of the triode Q31, the first port of the capacitor C31 and the first port of the resistor R33, and the grid electrode of the NMOS tube MN31 is connected with the second port of the current source Ibias;

the source electrode of the NMOS tube MN32 is grounded, the drain electrode of the NMOS tube MN is connected with the emitter electrode of the triode Q32, the second port of the capacitor C31 and the second port of the resistor R33, and the grid electrode of the NMOS tube MN32 is connected with the second port of the current source Ibias;

the source electrode of the NMOS tube MN33 is grounded, and the grid electrode of the NMOS tube MN is connected with the second port of the current source Ibias;

the source electrode of the NMOS tube MN34 is grounded, and the grid electrode of the NMOS tube is connected with the second port of the current source Ibias;

the base electrode of the triode Q31 is connected with the input port INN, and the collector electrode of the triode Q31 is connected with the first port of the resistor R31, the base electrode of the triode Q33 and the first port of the resistor R34;

the base electrode of the triode Q32 is connected with the input port INP, and the collector electrode of the triode Q32 is connected with the first port of the resistor R32, the base electrode of the triode Q34 and the first port of the resistor R35;

the collectors of the triode Q33 and the triode Q34 are both connected with a power supply VCC, and the emitter of the triode Q33 and the emitter of the triode Q34 are connected with the drain of the NMOS pipe MN33 and the first input port of the differential input pair of the differential-to-single-ended amplifier after being in short circuit;

the collector of the triode Q35 is connected with a power supply VCC, and the emitter of the triode Q35 is connected with a first port of the resistor R36;

the second ports of the resistor R31 and the resistor R32 are both connected with a power supply VCC;

the second port of the resistor R34 and the second port of the resistor R35 are connected with the base electrode of the triode Q35 after being in short circuit,

the second port of the resistor R36 is connected to the second input port of the differential input pair of the differential-to-single-ended amplifier, the drain of the NMOS transistor MN34, and the first port of the resistor R37;

the second port of the resistor R37 is connected with the output end of the differential-to-single-ended amplifier;

the output end of the front-end circuit of the transimpedance amplifier is connected with one port of the input end of the signal intensity judgment circuit through a series resistor R21, and the other port of the input end of the signal intensity judgment circuit is connected with a fixed reference voltage;

the output end of the differential-to-single-ended amplifier is used for outputting analog signals corresponding to the amplitude and the speed of the voltage signals output by the transimpedance amplifier front-end circuit.

It can be understood that, in this embodiment, the differential amplifier with the equalization compensation function is composed of an NMOS transistor MN30, an NMOS transistor MN31, an NMOS transistor MN32, a current source Ibias, a transistor Q31, a transistor Q32, a resistor R31, a resistor R32, a resistor R33, and a capacitor C31; the signal power/peak value monitoring circuit is composed of an NMOS tube MN33, an NMOS tube MN34, a triode Q33, a triode Q34, a triode Q35, a resistor R34, a resistor R35, a resistor R36, a resistor R37 and a differential-to-single-ended amplifier.

As shown in fig. 3, in some embodiments, the signal strength decision circuit includes: an NMOS tube MN41, a PMOS tube MP42, a PMOS tube MP43 and a phase inverter 41;

the gate of the NMOS transistor MN41 is connected to the output terminal of the signal strength monitoring circuit, the gate of the PMOS transistor MP41 is connected to the gate of the PMOS transistor MP42, the source of the NMOS transistor MN41 is grounded, and the drain of the NMOS transistor MN41 is connected to the drain of the PMOS transistor MP41, the gate of the PMOS transistor MP43, and the input port of the inverter 41; the source electrode of the PMOS tube MP41 is connected with the drain electrode of the PMOS tube MP42 and the source electrode of the PMOS tube MP 43; the source electrode of the PMOS tube MP42 is connected with a power supply VCC; the drain electrode of the PMOS pipe MP43 is grounded; the output of inverter 41 outputs a digital intensity signal.

As shown in fig. 1, in some embodiments, the adjustable low-pass filter circuit includes: a resistor R21, a resistor R22, a MOS variable resistor M22, a MOS switch M21, a capacitor C21 and a capacitor C22; wherein the content of the first and second substances,

the output end of the transimpedance amplifier front-end circuit at the first port of the resistor R21 is communicated, and the source of the MOS variable resistor M22 at the second port thereof is communicated with the first port of the resistor R22, it should be noted that the resistor R21 is a low-resistance resistor, which can be generally several hundred ohms to thousands of ohms, and can be used to reduce the influence of parasitic parameters of the resistor R22 on the bandwidth of the output end of the transimpedance amplifier front-end circuit.

The resistor R22 can be a high-resistance resistor, which is used to form a low-pass filter with the capacitors C21 and C22 to obtain the output voltage signal OUT of the front-end circuit of the transimpedance amplifier _front Mean interval signal OUT _{front_avg} ；

The gate of the MOS variable resistor M22 is communicated with the output end of the xor gate, and the drain thereof is communicated with the second port of the resistor R22, and the MOS variable resistor M22 is configured to change the high-low state of the resistance value according to the reset signal RST output by the xor gate;

the source of the MOS switch M21 is grounded, the grid of the MOS switch M21 is communicated with the output end of the inverter, the drain of the MOS switch M21 is communicated with the second port of the capacitor C21, and the MOS switch M21 is used for changing the on-off state of the MOS switch according to an inverted reset signal RSTB output by the inverter;

a first port of the capacitor C21 is communicated with a second port of the resistor R22; a first port of the capacitor C22 is communicated with a second port of the resistor R22, and the second port of the capacitor C is grounded; it should be noted that C21 is a large capacitance capacitor, C22 is a small capacitance capacitor, and the capacitors C21 and C22 and the high resistance resistor R22 may form a low-pass filter;

the resistor R22, the MOS variable resistor M22, the MOS switch M21, the capacitor C21, and the capacitor C22 are configured to form a low-pass filter with an adjustable cut-off frequency according to the reset signal RST and the inverted reset signal RSTB, and enable an output signal of a second port of the resistor R22 to conform to an average interval of an output voltage signal of the front-end circuit of the transimpedance amplifier.

As shown in fig. 1, it is understood that the MOS variable resistor M22 and the MOS switch M21 are controlled by the reset signal RST and the inverted reset signal RSTB, and that M22 and M21 are controlled by the MOS variable resistor M22 and the MOS switch M21. When RST is high, RSTB is low, M22 is in a conducting low-resistance state, the resistance value after M22 is connected with a high-resistance resistor R22 in parallel is in a low-resistance state, and M21 is in a closing stateIn this state, the path from the large capacitor C21 to ground is cut off, and at this time, M22, the high-resistance resistor R22 and the small-capacitance capacitor C22 form a low-pass filter with a high cut-off frequency of 3dB (e.g., above 100 MHz), and output an average signal OUT _{front_avg} Rapidly converging to the output voltage signal OUT of the front-end circuit of the transimpedance amplifier _front Around the mean value of (c). When RST is low, RSTB is high, M22 is in a turn-off high-resistance state, the resistance value of M22 and a high-resistance resistor R22 after being connected in parallel is in a high-resistance state, meanwhile, M21 is in a turn-on state, a path from a large capacitor C21 to the ground is communicated, at the moment, the M22, the high-resistance resistor R22, the large capacitor C21 and the small capacitor C22 form a low-pass filter with low 3dB cut-off frequency (such as below 100 KHz), and an output average value signal OUT is _{front_avg} Convergence is stabilized on the output voltage signal OUT of the front-end circuit of the transimpedance amplifier _front Around the mean value of (c).

In a specific embodiment, as shown in fig. 1, it is preferable to connect the input terminal of the signal strength monitoring circuit to the second port of the resistor R21, i.e. the input terminal of the signal strength monitoring circuit is OUT _front1 A signal;

the output port SI of the signal intensity monitoring circuit is connected with the input end of the signal intensity judging circuit; an output port DSI of the signal strength judging circuit is connected with an input port D of the D trigger;

an output port CLK of the clock generation circuit is connected with a clock signal input port of the D flip-flop; an output port Q of the D flip-flop outputs a signal Q _ DSI;

an output port DSI of the signal strength judging circuit is also connected with a first input port of the exclusive-OR gate, and an output signal Q _ DSI of the D flip-flop is connected with a second input port of the exclusive-OR gate;

the output port signal of the exclusive-or gate is RST, and is simultaneously connected with the gate of the MOS variable resistor M22 and the input port of the inverter 21;

the output port signal of the inverter 21 is RSTB, and it is connected to the gate of the MOS variable resistor M21.

The second port of the resistor R22 is connected with the drain of the MOS variable resistor M22, the first port of the capacitor C21, the first port of the capacitor C22 and the single-end-to-differential amplifierThe second input port of the amplifier differential input end is connected, and the output signal of the second port of the resistor R22 is OUT _front Of the mean value signal OUT _{front_avg} ；

The second port of the capacitor C21 is connected to the drain of the MOS variable resistor M21;

the source electrode of the MOS variable resistor M21 is grounded; the second port of the capacitor C22 is connected to ground.

A pair of differential output ports of the single-ended to differential amplifier is connected with a pair of differential input ports of the differential amplifier;

a pair of differential output ports of the differential amplifier is connected with a pair of differential input ports of the output buffer stage; the pair of differential output ports of the output buffer stage are OUTP and OUTN (i.e., the differential output ports of the transimpedance amplifier).

In consideration of the fact that the parasitic capacitance parameters such as R22, M22, C1, and C2 are large, the direct connection to OUT is performed _front Will result in OUT _front The bandwidth of the node is severely degraded. Using a resistor R21 (OUT after passing through the resistor R21) _front1 Output to signal strength monitoring circuit) is for the purpose of isolating OUT _front Node and large parasitic capacitance behind.

It will be appreciated that the present embodiment provides an automatic reset and fast burst response circuit suitable for use in a transimpedance amplifier, as shown in figures 1 and 4. After a burst signal comes, a reset signal RST pulse signal and an inverted reset signal RSTB pulse signal with a certain time width (such as tens to hundreds of ns) are rapidly generated, and a 3dB cut-off frequency high/low adjustable low-pass filter circuit consisting of a low-resistance resistor R21, a high-resistance resistor R22, a large-capacitance capacitor C21, a small-capacitance capacitor C22, an MOS variable resistor M22 and an MOS switch M21 is controlled by RST and RSTB.

At the reset signalIn the effective period of the pulse signals of RST and the reverse reset signal RSTB, RST is high, RSTB is low, M22 is in a conducting low-resistance state, the resistance value after M22 is connected with a high-resistance resistor R22 in parallel is in a low-resistance state, meanwhile, M21 is in a turn-off state, the path from a large capacitor C21 to the ground is disconnected, the large capacitor C21 does not work, at the moment, the M22, the high-resistance resistor R22 and the small-capacitance capacitor C22 form a low-pass filter with high 3dB cut-off frequency (above 100 MHz), and in the state, an average value signal OUT output by a low-pass filter circuit network _{front_avg} Quickly converge to its input voltage signal OUT _front Around the mean value of (c).

In the invalid period of the pulse signals of the reset signal RST and the inverse reset signal RSTB, RST is low, RSTB is high, M22 is in a turn-off high-resistance state, the resistance value after M22 is connected with a high-resistance resistor R22 in parallel is in a high-resistance state, meanwhile, M21 is in a turn-on state, a path from a large capacitor C21 to the ground is communicated, at the moment, the M22, the high-resistance resistor R22, the large-capacitance capacitor C21 and the small-capacitance capacitor C22 form a low-pass filter with a low 3dB cut-off frequency (for example, below 100 KHz), and in the state, an average value signal OUT output by a low-pass filter circuit network is output _{front_avg} Converges and stabilizes at its input voltage signal OUT _front Around the mean value of (c).

The embodiment of the present invention further provides a differential amplitude limiting amplifying circuit integrating automatic reset and fast burst response, which includes:

the adjustable high-pass filter circuit is connected with the input end signal INP and the input end signal INN and is communicated with the reset signal RST and the reversed-phase reset signal RSTB output by the reset signal automatic generation circuit;

the adjustable high-pass filter circuit is used for controlling a variable capacitor and an MOS (metal oxide semiconductor) tube arranged in the adjustable high-pass filter circuit according to the reset signal RST and the reverse reset signal RSTB and forming a high-pass filter with adjustable cut-off frequency, and signals output by the adjustable high-pass filter conform to the signal rate characteristics and the amplitude characteristics of the input end signals INP and INN;

It can be understood that the high-pass filter is used for filtering out the dc component in the signal, the rate characteristic refers to the signal rate, for example, 10Gbps, 25Gbps, etc., the amplitude characteristic refers to the signal swing, and the signal rate and the signal swing need to be kept consistent after passing through the high-pass filter.

As shown in fig. 6, in some embodiments, the adjustable high-pass filter circuit includes a variable capacitor C611, a capacitor C612, a MOS transistor M61, a variable capacitor C621, a capacitor C622, a MOS transistor M62, and a resistor R61; wherein, the first and the second end of the pipe are connected with each other,

a first port of the variable capacitor C611 is connected with the input end signal INN and a first port of the capacitor C612, a second port of the variable capacitor C611 is connected with the source of the MOS transistor M61, a first port of the resistor R61 and a first input end of a differential input pair of the differential limiting amplifier, and a control end of the variable capacitor C611 is connected with a reset signal RST;

the second port of the capacitor C612 is connected to the drain of the MOS transistor M61, and the gate of the MOS transistor M61 is connected to the inverted reset signal RSTB;

a first port of the variable capacitor C621 is connected to the input end signal INP and a first port of the capacitor C622 at the same time, a second port of the variable capacitor C621 is connected to the source of the MOS transistor M62, a second port of the resistor R61, and a second input end of the differential input pair of the differential limiting amplifier, and a control end of the variable capacitor C621 is connected to the reset signal RST;

the second port of the capacitor C622 is connected to the drain of the MOS transistor M62, and the gate of the MOS transistor M62 is connected to the inverted reset signal RSTB.

As shown in fig. 6, in some embodiments, the reset signal automatic generation circuit further includes:

the input end of the exclusive-or gate is respectively connected with the output end of the signal intensity judging circuit and the output end of the delay circuit, and the exclusive-or gate is used for carrying out exclusive-or processing on the received digital intensity signal and the digital intensity delay signal to obtain a reset signal RST;

and the input end of the phase inverter is communicated with the output end of the exclusive-OR gate, and the phase inverter is used for carrying out inversion operation on the reset signal RST output by the exclusive-OR gate to obtain an inverted reset signal RSTB.

As shown in fig. 6, in some embodiments, an output buffer stage is further communicated between the output terminal of the differential limiting amplifier and the input terminal of the signal strength monitoring circuit, and a pair of differential output terminals of the differential limiting amplifier is connected to a pair of differential input terminals of the output buffer stage, and a pair of differential output terminals of the output buffer stage is connected to a pair of differential input terminals of the signal strength monitoring circuit. The output buffer stage is used for realizing output impedance matching function and providing certain output voltage signal amplitude

As shown in fig. 6, the output port DSI of the signal strength decision circuit is connected to the input port D of the D flip-flop; an output port CLK of the clock generation circuit is connected with a clock signal input port of the D flip-flop; an output port Q of the D flip-flop outputs a signal Q _ DSI; the output port DSI of the signal strength judging circuit is also connected with the first input port of the exclusive-OR gate, and the output signal Q _ DSI of the D flip-flop is connected with the second input port of the exclusive-OR gate; the output port signal of the exclusive-or gate is RST, and the output port signal of the exclusive-or gate is simultaneously connected with the control end of the variable capacitor C611, the control end of the variable capacitor C621 and the input port of the inverter 61; the output port signal of the inverter 61 is RSTB, and it is simultaneously connected to the gate of the MOS transistor M61 and the gate of the MOS transistor M62.

It can be understood that, as shown in fig. 6, the present embodiment provides a circuit structure of a differential limiting amplifier circuit integrating automatic reset and fast burst response, and the reset signal automatic generation circuit rapidly generates a reset signal RST pulse signal and an inverted reset signal RSTB pulse signal of a certain time width (e.g., tens to hundreds of ns) in the beginning of a burst signal, and controls a high-pass filter circuit network with low-frequency cutoff frequency adjustable in high/low, which is composed of a variable capacitor C611, a capacitor C612, a MOS transistor M61, a variable capacitor C621, a capacitor C622, a MOS transistor M62, and a resistor R61, through RST and RSTB.

In the pulse signal effective period of the reset signal RST and the inverse reset signal RSTB, the RST is high, the RSTB is low, the MOS tubes M61 and M62 are in a conductive low-resistance state, and the variable capacitors C611 and C621 are in a low-capacitance state; the capacitor C612 is connected in parallel with the variable capacitor C611 in the low capacitance state by conducting the low-resistance MOS tube M61, and the capacitor C622 is connected in parallel with the variable capacitor C621 in the low capacitance state by conducting the low-resistance MOS tube M62; at this time, the circuit network formed by the capacitor C612, the MOS transistor M61 and the variable capacitor C611, and the circuit network formed by the capacitor C622, the MOS transistor M62 and the variable capacitor C621 can be equivalent to a low-capacitance capacitor, and form a high-pass filter with a high low-frequency cutoff frequency (e.g., above 100 MHz) with the resistor R61, in this state, the output signal of the high-pass filter circuit network can be converged to a state consistent with the input signal INP/INN quickly.

In the inactive period of the pulse signals of the reset signal RST and the reverse reset signal RSTB, the RST is low, the RSTB is high, the MOS tubes M61 and M62 are in an off high-resistance state, and the variable capacitors C611 and C621 are in a high-capacitance state; a path of the capacitor C612 connected with the variable capacitor C611 in parallel through the MOS transistor M61 is disconnected, and a path of the capacitor C622 connected with the variable capacitor C621 in parallel through the MOS transistor M62 is also disconnected; at this time, the circuit network formed by the capacitor C612, the MOS transistor M61 and the variable capacitor C611, and the circuit network formed by the capacitor C622, the MOS transistor M62 and the variable capacitor C621 can be equivalent to a high-capacitance capacitor, and form a high-pass filter with a low frequency cut-off frequency (e.g. below hundreds KHz) with the resistor R61, in this state, the output signal of the high-pass filter circuit network converges and stabilizes in a state consistent with the input signal INP/INN.

FIG. 7 (a) is a diagram of simulation results, wherein,/R1/PLUS is the input current signal of the transimpedance amplifier, which is a burst signal, no signal for a starting time, followed by a longer period of random data signal, followed by a further period of no signal state, followed by a longer period of random data signal, and a further period of no signal state; the/OUTFont is an output port signal of the front-end circuit of the transimpedance amplifier; the/OUTFontavg is an average value signal after low-pass filtering processing is carried out on a signal of an output port of the front-end circuit of the transimpedance amplifier; the/CLK is an output port signal of the clock generating circuit; the/SI is an output port signal of the signal intensity monitoring circuit; the/DSI is an output port signal of the signal strength judging circuit; the/Q _ DSI is an output signal which is input to the D trigger and processed by the D trigger; RST is an automatically generated reset signal; the/RSTB is an inverted signal of the reset signal/RST; the/OUTP and/OUTN are a pair of differential output port signals of the transimpedance amplifier.

As can be seen from fig. 7 (a), a reset pulse signal/RST occurs automatically about hundreds of ns after the occurrence of the random data signal and about tens of ns after the end of the random data signal; in a period of time immediately after the random data signal comes and the reset pulse signal/RST is inactive (low), the/outbontavg changes very slowly toward the mean state of the random data signal,

as shown in fig. 7 (b), during the time period after the random data signal comes and the reset pulse signal/RST is active (high), the/outbontavg can quickly reach the average state of the random data signal from the initial voltage state (the response time of the/outbontavg in fig. 7 is about 30 ns), and at the same time, the differential output port signal/OUTP and/OUTN of the transimpedance amplifier also quickly reach the state of outputting the normal signal from the signal setup state (the response time of the/OUTP and/OUTN in fig. 7 is also about 30 ns). During the time period after the random data signal is ended and the reset pulse signal/RST is active (high), the/outbontavg can quickly return to the initial voltage state from the average state of the random data signal, and at the same time, the differential output port signals/OUTP and/OUTN of the transimpedance amplifier also quickly return to the signal initial state from the initial voltage state.

According to the embodiment of the invention, the RESET signal can be automatically generated in the chip to realize quick RESET and quick response to the burst data signal, the MCU is not needed to provide an external RESET signal for chips such as a transimpedance amplifier, a limiting amplifier and a CDR to achieve the purpose of quick burst response in the OLT optical module, and the complexity and the working difficulty of realizing the signal quick response of an uplink burst link in an OLT optical module product can be effectively reduced. In addition, the method can also be applied to chips such as trans-impedance amplifiers, limiting amplifiers and CDRs in the light receiving component.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable storage media, which may include computer readable storage media (or non-transitory media) and communication media (or transitory media).

It is noted that, in the present invention, relational terms such as "first" and "second", and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of additional like elements in a process, method, article, or apparatus that comprises the element.

The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated auto-reset and fast burst response transimpedance amplifier, comprising:

the automatic reset signal generating circuit is communicated with the transimpedance amplifier front-end circuit and is used for generating a delayed digital intensity signal according to the intensity of the voltage signal output by the transimpedance amplifier front-end circuit and automatically generating a reset signal RST and an inverted reset signal RSTB through an exclusive-OR gate and an inverter;

2. An integrated auto-reset and fast burst response transimpedance amplifier according to claim 1, wherein said reset signal auto-generation circuit further comprises:

3. An integrated automatic reset and fast burst response transimpedance amplifier according to claim 2, characterized in that said delay circuit comprises:

4. An integrated automatic reset and fast burst response transimpedance amplifier according to claim 2, wherein said signal strength monitoring circuit comprises: the device comprises an NMOS (N-channel metal oxide semiconductor) tube MN (30), an NMOS tube MN (31), an NMOS tube MN (32), an NMOS tube MN (33), an NMOS tube MN (34), a current source Ibias, a triode Q (31), a triode Q (32), a triode Q (33), a triode Q (34), a triode Q (35), a resistor R (31), a resistor R (32), a resistor R (33), a resistor R (34), a resistor R (35), a resistor R (36), a resistor R (37), a capacitor C (31) and a differential-to-single-ended amplifier;

the base electrode of the triode Q (31) is connected with the input port INN, and the collector electrode of the triode Q (31) is simultaneously connected with the first port of the resistor R (31), the base electrode of the triode Q (33) and the first port of the resistor R (34);

the collecting electrodes of the triode Q (33) and the triode Q (34) are connected with a power supply VCC, and the emitting electrode of the triode Q (33) is connected with the emitting electrode of the triode Q (34) in a short circuit mode and then connected with the drain electrode of the NMOS pipe MN (33) and the first input port of the differential-to-single-ended amplifier in the differential input pair;

the collector of the triode Q (35) is connected with a power supply VCC, and the emitter of the triode Q is connected with a first port of the resistor R (36);

a second port of the resistor R (36) is simultaneously connected with a second input port in a differential input pair of the differential-to-single-ended amplifier, a drain electrode of the NMOS transistor MN (34) and a first port of the resistor R (37);

the output end of the front-end circuit of the transimpedance amplifier is connected with one port of the input end of the signal intensity judging circuit through a resistor R (21), and the other port of the input end of the signal intensity judging circuit is connected with a fixed reference voltage;

5. An integrated automatic reset and fast burst response transimpedance amplifier according to claim 2, wherein said signal strength decision circuit comprises: an NMOS transistor MN (41), a PMOS transistor MP (42), a PMOS transistor MP (43) and an inverter (41);

the drain electrode of the PMOS pipe MP (43) is grounded;

the output of the inverter (41) outputs the digital intensity signal.

6. An integrated automatic reset and fast burst response transimpedance amplifier according to claim 2, wherein said adjustable low-pass filter circuit comprises:

the resistor R (22), the MOS variable resistor M (22), the MOS switch M (21), the capacitor C (21) and the capacitor C (22) are used for forming the low-pass filter with the adjustable cut-off frequency according to the reset signal RST and the inverted reset signal RSTB and enabling an output signal of a second port of the resistor R (22) to accord with an average value interval of an output voltage signal of the transimpedance amplifier front-end circuit.

7. A differential amplitude limiting amplifier circuit integrating automatic reset and fast burst response, comprising:

the adjustable high-pass filter circuit is used for controlling a variable capacitor and an MOS (metal oxide semiconductor) tube arranged in the adjustable high-pass filter circuit according to the reset signal RST and the reverse reset signal RSTB and forming a high-pass filter with adjustable cut-off frequency, and signals output by the high-pass filter with adjustable cut-off frequency accord with the signal rate characteristics and the amplitude characteristics of the signals INP and INN at the input end;

8. The differential limiting amplifier circuit integrating automatic reset and fast burst response as recited in claim 7,

9. The differential limiting amplifier circuit integrating automatic reset and fast burst response as claimed in claim 7, wherein said reset signal automatic generation circuit further comprises:

10. The differential limiting amplifier circuit integrating automatic reset and fast burst response as recited in claim 9,

an output buffer stage is communicated between the output end of the differential limiting amplifier and the input end of the signal intensity monitoring circuit, a pair of differential output ends of the differential limiting amplifier is connected with a pair of differential input ends of the output buffer stage, and a pair of differential output ends of the output buffer stage is connected with a pair of differential input ends of the signal intensity monitoring circuit.