CN115912963A - MMC type VSC-HVDC system submodule capacitance voltage balance control method - Google Patents

Abstract

The invention relates to a capacitance and voltage balance control method for a submodule of an MMC type VSC-HVDC system, which comprises the following steps: setting the allowable fluctuation range of the capacitor voltage of the submodule toU _{c_rate} (100±ε) Percent; setting a retention factor h; if the bridge arm current charges the bridge arm sub-modules, the sub-modules with lower capacitor voltage are triggered preferentially; for capacitor voltage lower thanU _{c_rate} (100‑ε) % of sub-module capacitor, keeping its voltage value unchanged; for a capacitor voltage higher thanU _{c_rate} (100‑ε) % and the last control period is not investedThe sub-module capacitor multiplies the voltage value by h; if the bridge arm current discharges the bridge arm sub-modules, the sub-modules with higher capacitor voltage are triggered preferentially; for a capacitor voltage higher thanU _{c_rate} (100+ε) % of sub-module capacitor, keeping its voltage value unchanged; for capacitor voltage lower thanU _{c_rate} (100+ε) % and the submodule capacitor not put into the last control period, and the voltage value is divided by h. The method can reduce the switching frequency of the switching device on the premise of ensuring the voltage balance of the sub-module capacitor, thereby reducing the switching loss and improving the overall operation performance of the system.

Description

MMC type VSC-HVDC system submodule capacitance voltage balance control method

Technical Field

The invention belongs to the technical field of electric power, and particularly relates to a capacitance and voltage balance control method for a submodule of an MMC type VSC-HVDC system.

Background

The Modular Multilevel Converter (MMC) has a modular topological structure, has the inherent advantages of good harmonic characteristics, low switching frequency, no need of a filter device, strong expandability and the like, and is widely concerned and applied in the fields of high voltage and high power such as flexible direct current transmission, flexible multi-state switches of a power distribution network, electric energy routers, offshore wind power grid connection and the like.

The modular multilevel converter needs a large number of sub-modules (SMs) to be connected in series, and the average value of the capacitor voltage of each suspension sub-module is stabilized at a rated value so as to ensure the normal and stable operation of the modular multilevel converter. However, the sub-module capacitor voltage-sharing effect of the modular multilevel converter and the switching frequency of the Insulated Gate Bipolar Transistor (IGBT) are two important indicators for controlling the balance between each other.

With the development of MMC-HVDC to higher voltage level and larger capacity, the number of sub-modules in the MMC-HVDC is increased by geometric times, so that the balance of capacitance and voltage of the sub-modules becomes an important problem which cannot be avoided in the engineering application of the modular multilevel converter.

Disclosure of Invention

The invention aims to provide a Modular Multilevel Converter (MMC) type voltage stabilizing control method for a voltage of a submodule capacitor of a voltage stabilizing and stabilizing converter-high voltage direct current (VSC-HVDC) system, which can reduce the switching frequency of a switching device on the premise of ensuring the voltage of the submodule capacitor to be balanced, thereby reducing the switching loss and improving the overall operation performance of the system.

In order to realize the purpose, the invention adopts the technical scheme that: a capacitance and voltage balance control method for a submodule of an MMC type VSC-HVDC system comprises the following steps:

setting the allowable fluctuation range of the capacitor voltage of the submodule to be U _{c_rate} (100. + -. ε)%, wherein U _{c_rate} The capacitance voltage rated value is, and epsilon is a set fluctuation range threshold value; setting a holding factor h;

if the bridge arm current charges the bridge arm sub-modules, the sub-modules with lower capacitor voltage are triggered preferentially; for capacitor voltage lower than U _{c_rate} (100-epsilon)% of the submodule capacitors, and the voltage value of the submodule capacitors is kept unchanged to ensure that the submodule capacitors are preferentially put into use; for capacitor voltages higher than U _{c_rate} (100-epsilon)% of the sub-module capacitors which were not switched on in the previous control period, the voltage value of the sub-module capacitors is multiplied by a holding factor h, thereby reducing the possibility that the sub-module capacitors are switched on in the next control period and increasing the capacitor voltage to be higher than U _{c_rate} (100-epsilon)% and possibility of sub-module in throw-in state at last cycle keeping throw-in;

if the bridge arm current discharges the bridge arm sub-modules, the sub-modules with higher capacitor voltage are triggered preferentially; for capacitor voltages higher than U _{c_rate} (100 + epsilon)% of the sub-module capacitor, and the voltage value of the sub-module capacitor is kept unchanged to ensure that the sub-module capacitor is preferentially put into use; for capacitor voltages below U _{c_rate} (100 + epsilon)% of the sub-module capacitors which were not switched on in the previous control period, dividing the voltage value by the holding factor h, thereby reducing the possibility of switching on in the next control period and increasing the capacitor voltage to be lower than U _{c_rate} (100 + epsilon)% and the possibility that the submodule in the thrown state at the last cycle remains thrown;

if the bridge arm current charges the bridge arm submodule, the capacitance voltage is higher than that of the bridge arm submodule

And the last control period is put intoThe module capacitor multiplies the voltage value of the module capacitor by a holding factor h to reduce the possibility of putting the module capacitor into the next control period, thereby limiting the voltage fluctuation of the module capacitor to U _{c_rate} (100 ± epsilon)% of; wherein i represents the bridge arm current value, T _s Representing the control cycle duration, and C representing the sub-module capacitance;

if the bridge arm current discharges to the bridge arm submodule, the capacitor voltage is lower than that

And the voltage value of the sub-module capacitor which is put into the previous control period is multiplied by a holding factor h to reduce the possibility that the sub-module capacitor is put into the next control period, so that the voltage fluctuation of the capacitor is limited to U _{c_rate} (100. + -. ε)% of the total amount of the composition.

Further, the sub-modules are half-bridge sub-modules.

Further, ∈ =8,h =1.05.

Compared with the prior art, the invention has the following beneficial effects: the method introduces a maintenance factor, sets upper and lower limits of allowable fluctuation of capacitor voltage, and strictly limits the capacitor voltage within an allowable fluctuation range by adjusting a sub-module switch modulation wave, thereby ensuring the balance of the sub-module capacitor voltage, remarkably reducing the switching frequency of the sub-module, further reducing the switching loss and improving the overall operation performance of the system.

Drawings

Fig. 1 is a topology structure diagram of a three-phase modular multilevel converter in an embodiment of the present invention;

FIG. 2 is a topology structure diagram of an MMC sub-module in an embodiment of the present invention;

FIG. 3 is a comparison table of three switch states of the MMC sub-module in the embodiment of the present invention;

fig. 4 is an MMC type dc power transmission system structure in an embodiment of the present invention;

FIG. 5 shows the capacitor voltage fluctuation and trigger pulse waveform of the upper bridge arm submodule on the lower rectifying side A phase when epsilon =5 in the embodiment of the invention;

fig. 6 shows the capacitance-voltage fluctuation and trigger pulse waveform of the lower rectifying side a phase upper bridge arm submodule when epsilon =8 in the embodiment of the invention.

Detailed Description

The invention is further explained below with reference to the drawings and the embodiments.

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

A typical three-phase Modular Multilevel Converter (MMC) structure is shown in fig. 1, where point O represents a zero potential reference point and the voltage between the positive and negative dc buses is U _dc . The converter is provided with six bridge arms, wherein each bridge arm is provided with N identical Submodules (SM), a bridge arm inductor (L) and a bridge arm equivalent resistor (R), and the upper bridge arm and the lower bridge arm of each phase are combined to be called a phase unit.

The three-phase modularized multi-level converter is highly modularized, can easily adapt to application scenes with different voltage levels and different capacities by increasing and decreasing the number of sub-modules of each bridge arm, is convenient for realizing large-scale design, shortens the project research and development period, reduces the research and development difficulty and reduces the research and development cost. Different from the traditional VSC topology, the energy distribution of the three-phase modularized multi-level converter is in each sub-module capacitor, so that the capacitor impact current in the case of direct-current side fault can be greatly reduced, and the system fault protection capability and the system reliability are improved.

There are three main sub-module topologies, namely Half-bridge sub-module (Half-bridge sm, HBSM), full-bridge sub-module (Full-bridge sm, FBSM), and double-bin sub-module (Clamp-double sm, CDSM). Compared with the latter two topologies, although the half-bridge sub-module cannot clear the direct current fault through the current converter due to the freewheeling effect of the diode, the half-bridge sub-module is widely used in practical engineering due to the advantages of small loss, low cost, simple control and the like.

FIG. 2 is a diagram of the topology of a half-bridge submodule, where T ₁ And T ₂ Represents an insulated gate bipolar transistor, D ₁ And D ₂ Respectively representing an anti-parallel diode, C ₀ Representing the sub-module dc capacitance. u. of _c Represents the capacitor voltage u _sm Representing the voltage across the submodule, i _sm Representing the current flowing into the submodule. As is evident from fig. 2, each sub-module is connected in series AB to the main circuit topology, while MMC supports the bus voltage by means of the capacitor voltage in the respective sub-module.

Under normal operating conditions, T ₁ And T ₂ And the switch is in a complementary switch state and is alternately switched on and off. The analysis shows in table 1 in fig. 3, the submodules have three working states, which are: a locked state, an engaged state, and a removed state.

When T is ₁ And T ₂ When a turn-off signal is applied, referred to as a latch-up condition, according to the antiparallel diode D ₁ And D ₂ The conduction situation is divided into two working modes, namely a mode (a) and a mode (b). For modes (a), D ₁ Conduction, submodule current passing D ₁ The capacitor is charged and the output voltage is the capacitor voltage. For modes (b), D ₂ Conduction, sub-module current passing D ₂ The capacitor is bypassed and the output voltage is 0.

When T is ₁ Applying a turn-on signal, T ₂ When the off signal is applied, this is called an on state, and two operation modes, namely, a mode (c) and a mode (d), can be divided according to the current flowing direction of the submodule. For modes (c), D ₁ Is turned on and T ₁ Subject to a reverse voltage, in the off state despite the application of an on signal, the submodule current passing D ₁ The capacitor is charged and the output voltage is the capacitor voltage. For mode (d), T ₁ On, D ₁ The submodule current passes through T when the submodule is in a closed state due to the reverse voltage ₁ The capacitor is discharged and the output voltage is the capacitor voltage.

When T is ₁ Applying a shutdown signal, T ₂ When the switch-on signal is applied, which is called the cut-off state, the sub-module can be divided into two operation modes, namely a mode (e) and a mode (f), according to the current flowing direction of the sub-module. For mode (e), T ₂ Is turned on and D ₂ The sub-module current passes through T when the sub-module is in the off state due to the reverse voltage ₂ The capacitor is bypassed and the output voltage is 0. For mode (f), D ₂ Is turned on and T ₂ Subject to a reverse voltage, in the off state despite the application of an on signal, the submodule current passing D ₂ The capacitor is bypassed and the output voltage is 0.

From the above analysis it can be seen that when the sub-module enters the steady state mode, there is one and only one tube in the conducting state. Furthermore, if T is to be determined ₁ And D ₁ Viewed as s ₁ ，T ₂ And D ₂ Viewed as s ₂ Then when the submodule is in the input state, s ₁ Opening s ₂ Is turned off, and the current can pass through s ₁ Bidirectional flow is realized, and the external voltage of the sub-modules is the capacitor voltage. Similarly, when the submodule is in the cut-out state, s ₁ Turn-off s ₂ On, current can pass through s ₂ Bidirectional flow is realized, and the external voltage of the sub-modules is 0. And for the latched state, s ₁ And s ₂ The conduction is not constant.

The total direct-current voltage control of the three-phase modular multilevel converter and the parallel structure of the 3 phase units can maintain the direct-current voltage balance of the phase units, and the voltage balance between the capacitor voltages of the upper bridge arm submodule and the lower bridge arm submodule can be realized along with the switching rotation of the switching states of the upper bridge arm submodule and the lower bridge arm submodule of the phase units. Therefore, the capacitance voltage balance control of the three-phase modular multilevel converter can be carried out by taking one bridge arm as a unit.

The conventional capacitor voltage balancing strategy is as follows:

1. detecting the voltage value of each SM capacitor through a voltage sensor;

2. detecting the current direction of each bridge arm through a current sensor;

3. and (4) controlling the number N of modules input by the output bridge arm in real time according to the valve group stage, and sequencing bridge arm voltages by the controller.

Analysis shows that the N submodules with the lowest voltage are put in when the current i direction charges the submodules, and the N submodules with the highest voltage are put in when the current i direction discharges the submodules, so that voltage balance of the bridge arm submodules is realized.

Assume that the bridge arm current of the a-phase bridge arm charges the submodules put into the bridge arm in a period of time. In a control period, the controller charges the N sub-modules with the lowest voltage to increase the voltage, and the cut-off voltage of the rest sub-modules is kept unchanged. Due to the balance control effect and the short switching period, the voltage difference of each submodule is small, so that the voltage of the submodule charged in the period is higher than that of the submodule cut off. In the next control cycle, the new N submodules with the lowest voltage are charged through voltage sequencing, and the submodules which are cut off before are put into use in the cycle. Obviously, under this strategy, the switching frequency of each submodule is close to the control period, so that large switching loss is caused.

The traditional voltage balancing strategy pursues the balancing effect caused by the extremely high capacitance and voltage of the bridge arm submodule without considering the switching frequency of the submodule. In practical engineering, the capacitance voltage balancing effect and the sub-module switching frequency are key indexes for measuring the MMC system.

The embodiment provides a capacitance and voltage balance control method for a submodule of an MMC type VSC-HVDC system, wherein a capacitance and voltage allowable fluctuation range is set, and a submodule with out-of-limit capacitance and voltage is focused, so that balance control over voltage balance and switching frequency is realized. The method specifically comprises the following steps:

step 1, setting the allowable fluctuation range of the capacitor voltage of the submodule to be U _{c_rate} (100. + -. ε)%, where U _{c_rate} Epsilon is a set fluctuation range threshold value for the rated value of the capacitor voltage; the hold factor h is set.

Step 2, if the bridge arm current charges the bridge arm submoduleIf yes, the submodule with lower capacitor voltage is triggered preferentially; for capacitor voltages below U _{c_rate} (100-epsilon)% of the submodule capacitors, and the voltage value of the submodule capacitors is kept unchanged to ensure that the submodule capacitors are preferentially put into use; for capacitor voltages higher than U _{c_rate} (100-epsilon)% of the sub-module capacitors which are not switched in the previous control period, the voltage value of the sub-module capacitors is multiplied by a holding factor h which is slightly larger than 1, so that the possibility that the sub-module capacitors are switched in the next control period is reduced, and the capacitor voltage is increased to be higher than U _{c_rate} (100-epsilon)% and the possibility of the submodule being in the throw-in state in the last cycle remains thrown in.

Step 3, if the bridge arm current discharges the bridge arm sub-modules, the sub-modules with higher capacitor voltage are triggered preferentially; for capacitor voltages higher than U _{c_rate} (100 + epsilon)% of the submodule capacitors, and the voltage value of the submodule capacitors is kept unchanged to ensure that the submodule capacitors are preferentially put into use; for capacitor voltage lower than U _{c_rate} (100 + epsilon)% of the capacitor of the submodule which has not been switched on in the previous control period, the voltage value of the capacitor of the submodule is divided by a holding factor h which is slightly larger than 1, thereby reducing the possibility that the capacitor of the submodule is switched on in the next control period and increasing the voltage of the capacitor to be lower than U _{c_rate} (100 + epsilon)% and the submodule that was in the put state in the previous cycle remains a possibility of putting.

Step 4, if the bridge arm current charges the bridge arm submodule, the capacitor voltage is higher than the capacitor voltage

And the voltage value of the sub-module capacitor which is put into the previous control period is multiplied by a retention factor h which is slightly larger than 1, so that the possibility of putting into the next control period is reduced, and the capacitor voltage fluctuation is strictly limited to U _{c_rate} (100 ± epsilon)% of; wherein i represents the bridge arm current value, T _s Representing the control cycle duration and C the sub-module capacitance.

Step 5, if the bridge arm current discharges to the bridge arm submodule, the capacitor voltage is lower than the capacitor voltage

And the voltage value of the sub-module capacitor which is put into the previous control period is multiplied by oneA holding factor h slightly larger than 1 reduces the possibility of putting into the next control period, thereby strictly limiting the fluctuation of the capacitor voltage to U _{c_rate} (100. + -. ε)% of the total amount of the composition.

According to the method, the voltage balance is mainly put on the out-of-limit sub-module capacitor voltage, the sub-module capacitor voltage which is not out-of-limit is adjusted according to the steps 2 and 3, and the sub-module capacitor which is not out-of-limit but has out-of-limit risk is adjusted according to the steps 4 and 5. According to the steps, the original switching state can be kept on the premise that the capacitor voltage is strictly limited within the allowable fluctuation range, and the switching frequency is reduced. Preferably, ε =8,h =1.05.

In this embodiment, a two-end MMC-type VSC-HVDC system shown in fig. 4 is built on MATLAB/Simulink, and simulation verification proves that the system is feasible. The MMC and control system parameters in the simulation are shown in table 2.

TABLE 2 simulation System parameters

Simulation verification takes an upper bridge arm of an a phase on an inversion side as a research object. Fig. 5 is a simulation waveform diagram of the fluctuation of the capacitor voltage of each submodule of the phase-a upper bridge arm and a submodule trigger pulse waveform diagram, wherein the allowable voltage fluctuation range is 5%, namely epsilon is 5, and the retention factors (h) are respectively 1.02, 1.05, 1.08 and 1.1.

Fig. 6 is a simulation waveform diagram of the capacitor voltage fluctuation of each submodule of the phase a upper bridge arm and a submodule trigger pulse waveform diagram, wherein the voltage fluctuation range is 8%, namely epsilon is 5, and the retention factors are respectively 1.02, 1.05, 1.08 and 1.1.

As can be seen from fig. 5 and 6, the capacitor voltage fluctuation of each sub-module under the strategy proposed by the present invention is not much different from that of the conventional method, and the switching frequency is significantly reduced.

As can be seen from the data in fig. 5 and 6 summarized in table 3, by changing the holding factor and the allowable voltage fluctuation range, the capacitor voltage fluctuation can be strictly limited within the set allowable fluctuation range, and the average switching frequency is greatly reduced. Under the condition that the epsilon =5,h =1.05, the average switching frequency is reduced by 81.7%, and under the condition that the epsilon =8,h =1.05, the average switching frequency is reduced by 90.38%, so that the method has great engineering application value.

TABLE 3 average switching frequency and maximum fluctuation percentage of sub-module capacitor voltage at different h and ε

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While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. However, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present invention are within the protection scope of the technical solution of the present invention.

Claims (3)

1. A capacitance and voltage balance control method for a submodule of an MMC type VSC-HVDC system is characterized by comprising the following steps:

setting the allowable fluctuation range of the capacitor voltage of the submodule to be U _{c_rate} (100. + -. ε)%, where U _{c_rate} The capacitance voltage rated value is, and epsilon is a set fluctuation range threshold value; setting a retention factor h;

if the bridge arm current charges the bridge arm sub-modules, the sub-modules with lower capacitor voltage are triggered preferentially; for capacitor voltages below U _{c_rate} (100-epsilon)% of the submodule capacitors, and the voltage value of the submodule capacitors is kept unchanged to ensure that the submodule capacitors are preferentially put into use; for capacitor voltages higher than U _{c_rate} (100-epsilon)% of the sub-module capacitors which were not switched on in the previous control cycle, the voltage value of the sub-module capacitors is multiplied by a holding factor h, thereby reducing the possibility that the sub-module capacitors are switched on in the next control cycle and increasing the capacitor voltage to be higher than U _{c_rate} (100-epsilon)% and possibility of sub-module in throw-in state at last cycle keeping throw-in;

if the bridge arm current discharges the bridge arm sub-modules, the sub-modules with higher capacitor voltage are triggered preferentially; for capacitor voltages higher than U _{c_rate} (100 + epsilon)% of the submodule capacitors, and the voltage value of the submodule capacitors is kept unchanged to ensure that the submodule capacitors are preferentially put into use; for capacitor voltage lower than U _{c_rate} (100 + epsilon)% of the sub-module capacitors which were not switched on in the previous control period, dividing the voltage value by the holding factor h, thereby reducing the possibility of switching on in the next control period and increasing the capacitor voltage to be lower than U _{c_rate} (100 + epsilon)% of the possibility that the submodule which was in the on state in the previous cycle remains on;

if the bridge arm current charges the bridge arm submodule, the capacitance voltage is higher than that of the bridge arm submodule

And the voltage value of the sub-module capacitor which is put into the previous control period is multiplied by a holding factor h to reduce the possibility that the sub-module capacitor is put into the next control period, so that the voltage fluctuation of the capacitor is limited to U _{c_rate} (100 ± epsilon)% of; wherein i represents the bridge arm current value, T _s Representing the control cycle duration, C represents the sub-module capacitance;

if the bridge arm current discharges to the bridge arm submodule, the voltage of the capacitor is lower than that of the bridge arm submodule

And the voltage value of the sub-module capacitor which is put into the previous control period is multiplied by a holding factor h to reduce the possibility that the sub-module capacitor is put into the next control period, so that the voltage fluctuation of the capacitor is limited to U _{c_rate} (100. + -. ε)% of the total amount of the composition.

2. The method according to claim 1, wherein the sub-module is a half-bridge sub-module.

3. The capacitance-voltage equalization control method of the submodule of the MMC type VSC-HVDC system according to claim 1, characterized in that ε =8,h =1.05.

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