CN116094352A - MMC VSC-HVDC system submodule average frequency optimization control method - Google Patents

MMC VSC-HVDC system submodule average frequency optimization control method Download PDF

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CN116094352A
CN116094352A CN202211519944.0A CN202211519944A CN116094352A CN 116094352 A CN116094352 A CN 116094352A CN 202211519944 A CN202211519944 A CN 202211519944A CN 116094352 A CN116094352 A CN 116094352A
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submodule
bridge arm
capacitance
voltage
sub
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王金柯
陈大玮
晁武杰
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Electric Power Research Institute of State Grid Fujian Electric Power Co Ltd
State Grid Fujian Electric Power Co Ltd
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Electric Power Research Institute of State Grid Fujian Electric Power Co Ltd
State Grid Fujian Electric Power Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4833—Capacitor voltage balancing
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/36—Arrangements for transfer of electric power between ac networks via a high-tension dc link
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/60—Arrangements for transfer of electric power between AC networks or generators via a high voltage DC link [HVCD]

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  • Power Engineering (AREA)
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Abstract

The invention relates to an MMC type VSC-HVDC system submodule average frequency optimization control method, which comprises the following steps: setting the allowable fluctuation range of the capacitance voltage of the sub-module asU c_rate (100±ε) The%; adjusting a set holding factor h by a dual-loop PI controller; if the bridge arm current charges the bridge arm submodule, the submodule with lower capacitance voltage is preferentially triggered; for capacitor voltages lower thanU c_rate (100‑ε) % submodule capacitance, keeping the voltage value unchanged; for capacitor voltages higher thanU c_rate (100‑ε) % and the submodule capacitance which is not put into the previous control period is multiplied by h; if bridge arm current pairs bridge arm sub-dieThe submodule with higher capacitor voltage is preferentially triggered when the block discharges; for capacitor voltages higher thanU c_rate (100+ε) % submodule capacitance, keeping the voltage value unchanged; for capacitor voltages lower thanU c_rate (100+ε) % and the submodule capacitance not put into the last control period, the voltage value is divided by h. The method is favorable for comprehensive optimization control of the switching frequency of the sub-module and the balance of the capacitor voltage.

Description

MMC VSC-HVDC system submodule average frequency optimization control method
Technical Field
The invention belongs to the technical field of power, and particularly relates to a submodule average frequency optimization control method of an MMC (modular multilevel converter) -HVDC (high voltage direct current) system based on capacitor voltage balance.
Background
The modularized multi-level converter (modular multilevel converter, MMC) has the advantages of modularized topological structure, good harmonic characteristic, low switching frequency, redundancy control, strong expandability, strong fault protection capability, no need of a filter device and the like, and is widely focused and applied in the fields of medium-high voltage and high power such as flexible direct current transmission, flexible multi-state switches of a power distribution network, electric energy routers, offshore wind power grid connection and the like.
The modular multilevel converter needs a plurality of sub-modules (SMs) to be connected in series, however, the capacitance voltage of the sub-modules is not constant, and along with the difference of factors such as charging time, parameters, loss and the like of each sub-module when the MMC operates, the capacitance voltage has certain discreteness, and if the capacitance voltage is not controlled, the sub-modules are damaged, so that the system is paralyzed. However, the submodule capacitance equalizing effect of the modularized multi-level converter and the switching frequency of the insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT) are important indexes of mutual equilibrium, so that how to perform equilibrium control on the submodule capacitance equalizing effect and the switching frequency of the insulated gate bipolar transistor have important theoretical and engineering values.
Disclosure of Invention
The invention aims to provide an MMC-HVDC system submodule average frequency optimization control method which is beneficial to comprehensive optimization control of submodule switching frequency and capacitor voltage balance.
In order to achieve the above purpose, the invention adopts the following technical scheme: an MMC VSC-HVDC system submodule average frequency optimization control method comprises the following steps:
let the allowable fluctuation range of the capacitance voltage of the sub-module be U c_rate (100.+ -. ε)%, wherein U c_rate For the rated value of the capacitor voltage, epsilon is a set fluctuation range threshold value; adjusting a set holding factor h by a dual-loop PI controller;
if the bridge arm current charges the bridge arm submodule, the submodule with lower capacitance voltage is preferentially triggered; for capacitor voltages below U c_rate The submodule capacitance of (100-epsilon)% keeps the voltage value unchanged so as to ensure the preferential input of the submodule capacitance; for capacitor voltages higher than U c_rate (100-epsilon)% and the submodule capacitance not put into operation in the previous control period, multiplying the voltage value thereof by a holding factor h, thereby reducing the possibility of putting into operation in the next control period and increasing the capacitance voltage to be higher than U c_rate (100- ε)% and the likelihood that the submodule in the put-in state in the last period remains put-in;
if the bridge arm current discharges the bridge arm submodule, the submodule with higher capacitance voltage is preferentially triggered; for capacitor voltages higher than U c_rate Sub-module capacitance of (100+ε)% is kept constant to ensure that it is put into priority; for capacitor voltages below U c_rate (100+ε)% and the sub-module capacitance not being put into the previous control period, dividing its voltage value by a hold factor h, thereby reducing the likelihood of its being put into the next control period and increasing the capacitance voltage below U c_rate (100+ε)% and the possibility that the submodule in the put-in state in the last cycle remains put-in.
Further, the sub-module is a half-bridge sub-module.
Further, the value of the retention factor h is determined by a dual-loop PI controller based on the retention factor, specifically:
obtaining the average switching frequency f of the sub-module through the frequency measurement module ava Average switching frequency f with a given submodule ref Comparing the calculated errors, then inputting the calculated errors into a first PI link, and calculating and outputting a given bridgeArm maximum capacitance voltage difference DeltaU ref Will DeltaU ref Voltage difference with maximum capacitance of bridge arm, i.e. difference DeltaU between maximum value and minimum value of bridge arm capacitance voltage imb And comparing the calculated errors, inputting a second PI link, and calculating to obtain the value of the retention factor h.
Further, the frequency measurement module takes a bridge arm as a unit, and calculates the instantaneous value f of the bridge arm switching frequency in each control period ins Setting the length of a sampling window, and averaging the instantaneous value of the switching frequency in the sampling window to obtain the average switching frequency f of the submodule in the period of time ava The method comprises the steps of carrying out a first treatment on the surface of the The sampling window length l is taken as:
Figure BDA0003973382570000021
wherein k is a positive integer; f (f) s Is the frequency of the alternating current power grid; t (T) s Is a switching control period.
The instantaneous value of the bridge arm switching frequency is obtained by dividing the number of the switch state changes of the submodules of the bridge arm in two continuous control periods by twice the number of the submodules of the bridge arm and then dividing by the switch control period:
Figure BDA0003973382570000022
wherein N is sum The number of the switch state changes of the submodule in two continuous control periods; n is the number of bridge arm submodules; t (T) s Is a switching control period;
then the submodule average switching frequency f ava Expressed as:
Figure BDA0003973382570000023
compared with the prior art, the invention has the following beneficial effects: the method corrects and sets the retention factor through a double-closed-loop PI controller on the basis of a retention factor capacitor voltage balance strategy, and further performs optimal control on the average frequency of the sub-module, thereby realizing comprehensive optimal control on the switching frequency and the capacitor voltage balance of the sub-module and improving the overall operation performance of the system.
Drawings
Fig. 1 is a topology diagram of a three-phase modular multilevel converter in an embodiment of the invention;
FIG. 2 is a topology diagram of an MMC sub-module in an embodiment of the invention;
FIG. 3 is a table showing three switching states of MMC sub-modules according to an embodiment of the present invention;
FIG. 4 is a control block diagram of a double loop PI controller based on a retention factor in an embodiment of the invention;
fig. 5 is a schematic diagram of an MMC dc power transmission system according to an embodiment of the invention;
FIG. 6 is a graph of steady state simulation waveforms in an embodiment of the present invention;
FIG. 7 is a simulated waveform diagram of a step change in frequency reference in an embodiment of the invention;
fig. 8 is a simulated waveform diagram at variable power in an embodiment of the invention.
Detailed Description
The invention will be further described with reference to the accompanying drawings and examples.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.
Typical three-phase mouldThe block multilevel converter (MMC) structure is shown in figure 1, wherein the point O represents zero potential reference point, and the voltage between positive and negative DC buses is U dc . The converter has six bridge arms, wherein each bridge arm is composed of N identical Submodules (SM), bridge arm inductance (L) and bridge arm equivalent resistance (R), and the upper and lower bridge arms of each phase are combined together to be called a phase unit.
The three-phase modularized multi-level converter is highly modularized, can be easily adapted to application scenes with different voltage grades and different capacities by increasing and decreasing the number of sub-modules of each bridge arm, is convenient for realizing large-scale design, shortens project research and development period, reduces research and development difficulty and reduces research and development cost. Different from the traditional VSC topology, the energy of the three-phase modularized multi-level converter is distributed in each submodule capacitor, so that capacitor impact current during direct-current side faults can be greatly reduced, and the system fault protection capability and the system reliability are improved.
The sub-module topologies are mainly three, namely a Half-bridge sub-module (Half-bridgeSM, HBSM), a Full-bridge sub-module (Full-bridgeSM, FBSM) and a double-box sub-module (Clamp-double SM, CDSM). Compared with the latter two topologies, the half-bridge submodule cannot clear direct-current faults through the converter due to the follow current effect of the diode, but has the advantages of small loss, low cost, simple control and the like, so that the half-bridge submodule is widely used in actual engineering.
FIG. 2 is a topology of a half-bridge sub-module, where T 1 And T 2 Represents an insulated gate bipolar transistor, D 1 And D 2 Respectively represent anti-parallel diodes, C 0 Representing the submodule dc capacitance. u (u) c Represents the capacitance voltage, u sm Representing the voltage across the submodule, i sm Representing the current flowing into the submodule. As is evident from fig. 2, each sub-module is connected in series via AB to the main circuit topology, while MMC supports the bus voltage via the capacitor voltage in the respective sub-module.
Under normal working condition, T 1 And T 2 In a complementary switching state, alternately turned on and off. The sub-modules have three working states as shown in table 1 in fig. 3 through analysis, and the working states are respectively: in the locked-out state,a throw-in state, a cut-off state.
When T is 1 And T 2 When the turn-off signal is applied, this time called the latch-up state, according to the anti-parallel diode D 1 And D 2 The conduction situation is divided into two working modes, namely a mode (a) and a mode (b). For mode (a), D 1 Conduction, submodule current through D 1 The capacitor is charged and the output voltage is the capacitor voltage. For mode (b), D 2 Conduction, submodule current through D 2 The capacitor bypass output voltage is set to 0.
When T is 1 Applying an on signal, T 2 When the off signal is applied, the operation mode is referred to as an on state, and may be divided into two operation modes, i.e., a mode (c) and a mode (d), according to the current flowing direction of the sub-module. For mode (c), D 1 Turned on, T 1 Is subjected to reverse voltage, and is in an off state despite the application of an on signal, and the submodule current passes through D 1 The capacitor is charged and the output voltage is the capacitor voltage. For mode (d), T 1 Conduction, D 1 The submodule current passes through T because of being in a closed state when being subjected to reverse voltage 1 The capacitor is discharged and the output voltage is the capacitor voltage.
When T is 1 Applying a turn-off signal T 2 When an on signal is applied, the operation mode is called a cut-off state, and can be divided into two operation modes according to the current flowing direction of the submodule, namely a mode (e) and a mode (f). For mode (e), T 2 Conduct, and D 2 The submodule current passes through T because of being in an off state when being subjected to reverse voltage 2 The capacitor is bypassed and the output voltage is 0. For mode (f), D 2 Turned on, T 2 Is subjected to reverse voltage, and is in an off state despite the application of an on signal, and the submodule current passes through D 2 The capacitor bypass output voltage is set to 0.
From the above analysis it can be seen that when the sub-module enters steady state mode, there is and only one tube in the conductive state. In addition, if T is to be 1 And D 1 Regarded as s 1 ，T 2 And D 2 Regarded as s 2 Then, when the sub-module is in the put-in state,s 1 open s 2 Turn off, the current can pass through s 1 The bidirectional flow is realized, and the external voltage of the submodule is capacitor voltage. Similarly, when the sub-module is in the cut-out state, s 1 Switch off s 2 On, the current can pass through s 2 Bidirectional flow is realized, and the external voltage of the submodule is 0. And for the locked state s 1 Sum s 2 Conduction is indefinite.
The total direct current voltage control of the three-phase modularized multi-level converter and the parallel structure of the 3 phase units can maintain the direct current voltage balance of the phase units, and along with the alternation of the switching states of the upper bridge arm submodule and the lower bridge arm submodule of the phase units, the voltage balance between the capacitor voltages of the upper bridge arm submodule and the lower bridge arm submodule can be realized. Therefore, the capacitance-voltage balance control of the three-phase modularized multi-level converter can be performed by taking one bridge arm as a unit.
The embodiment provides an MMC-HVDC system submodule average frequency optimization control method, which specifically comprises the following steps:
step 1, setting the allowable fluctuation range of the capacitance voltage of the sub-module as U c_rate (100.+ -. ε)%, wherein U c_rate For the rated value of the capacitor voltage, epsilon is a set fluctuation range threshold value; the set holding factor h is regulated by a dual loop PI controller.
Step 2, if the bridge arm current charges the bridge arm submodule, the submodule with lower capacitance voltage is preferentially triggered; for capacitor voltages below U c_rate The submodule capacitance of (100-epsilon)% keeps the voltage value unchanged so as to ensure the preferential input of the submodule capacitance; for capacitor voltages higher than U c_rate (100-epsilon)% and the submodule capacitance not put into operation in the previous control period, multiplying the voltage value thereof by a holding factor h, thereby reducing the possibility of putting into operation in the next control period and increasing the capacitance voltage to be higher than U c_rate (100- ε)% and the possibility that the submodule in the put-in state in the last cycle remains put-in.
Step 3, if the bridge arm current discharges the bridge arm submodule, the submodule with higher capacitance voltage is preferentially triggered; for capacitor voltages higher than U c_rate Sub-module capacitance of (100+ε)% is kept constant to ensure its priorityThrowing; for capacitor voltages below U c_rate (100+ε)% and the sub-module capacitance not being put into the previous control period, dividing its voltage value by a hold factor h, thereby reducing the likelihood of its being put into the next control period and increasing the capacitance voltage below U c_rate (100+ε)% and the possibility that the submodule in the put-in state in the last cycle remains put-in.
According to the method, the probability of keeping the original switching state of the submodule is increased by introducing the keeping factor h, frequent switching of the submodule is avoided, and the average switching frequency of the submodule is reduced. Obviously, when the holding factor is smaller (i.e., the holding factor is closer to 1), the difference in capacitance voltage of the bridge arm submodule is smaller, and the average switching frequency is lower. The value of the holding factor h is determined by constructing a double-loop PI controller based on the holding factor, and the control of the switching frequency and the capacitor voltage consistency is realized by utilizing the relation between the holding factor and the capacitor voltage consistency and the switching frequency. The specific implementation block diagram of the dual-loop PI controller is shown in fig. 4, and specifically includes:
obtaining the average switching frequency f of the sub-module through the frequency measurement module ava Average switching frequency f with a given submodule ref Comparing the calculated errors, then inputting the calculated errors into a first PI link, and calculating and outputting the maximum capacitance voltage difference delta U of a given bridge arm ref Will DeltaU ref Voltage difference delta U with bridge arm maximum capacitance imb And (namely, the difference between the maximum value and the minimum value of the bridge arm capacitor voltage) is compared with the calculated error, and then a second PI link is input, so that the value of the holding factor h is calculated.
Specifically, the frequency measurement module takes a bridge arm as a unit, and calculates the instantaneous value f of the bridge arm switching frequency in each control period ins Setting the length of a sampling window, and averaging the instantaneous value of the switching frequency in the sampling window to obtain the average switching frequency f of the submodule in the period of time ava The method comprises the steps of carrying out a first treatment on the surface of the The sampling window length l is taken as:
Figure BDA0003973382570000061
where k is a positive integer, i.e. k=1, 2,3，…；f s Is the frequency of the alternating current power grid; t (T) s Is a switching control period.
The instantaneous value of the bridge arm switching frequency is obtained by dividing the number of the switch state changes of the submodules of the bridge arm in two continuous control periods by twice the number of the submodules of the bridge arm and then dividing by the switch control period:
Figure BDA0003973382570000062
wherein N is sum The number of the switch state changes of the submodule in two continuous control periods; n is the number of bridge arm submodules; t (T) s Is a switching control period;
then the submodule average switching frequency f ava Expressed as:
Figure BDA0003973382570000063
in the embodiment, a two-end MMC type VSC-HVDC system shown in figure 5 is built in MATLAB/Simulink, and simulation verification proves that the method is feasible. MMC and control system parameters in the simulation are shown in Table 2.
Table 2 simulation system parameters
Figure BDA0003973382570000071
Simulation verification will develop verification of the feasibility of the invention from several aspects as follows. And (1) simulating results under the steady state of the system. (2) simulation results when the frequency reference value is changed in a step mode. (3) simulation results under variable power.
The simulation verification takes an a-phase upper bridge arm of the inversion side as a research object. Fig. 6 is a waveform diagram of capacitor voltage fluctuation of each sub-module, an average switching frequency waveform diagram of the sub-module, an instantaneous switching frequency waveform diagram of the sub-module, a waveform diagram of the maximum capacitor voltage difference of the bridge arm and a waveform diagram of a holding factor of the bridge arm on a phase respectively. As shown in fig. 6, during steady state operation of the system, given a sub-module average frequency of 100Hz, the sub-module capacitance voltage maximum fluctuation is less than 5.6%, the sub-module average switching frequency fluctuation is less than 4%, the bridge arm maximum capacitance voltage difference is stabilized at 8.25V, and the factor h is kept stabilized at 1.0325.
And the diagram 7 is a waveform diagram of capacitance and voltage fluctuation of each sub-module, an average switching frequency waveform diagram of the sub-module, an instantaneous switching frequency waveform diagram of the sub-module, a waveform diagram of the maximum capacitance and voltage difference of the bridge arm and a waveform diagram of a holding factor of each sub-module of the a-phase upper bridge arm from top to bottom. As shown in fig. 7, the given value of the submodule controller is stepped from 150Hz to 100Hz at 0.6s, the average switching frequency is converged to the given value of 100Hz within 0.05s after the step, no obvious overshoot phenomenon occurs in the transient process, and the system transition is stable.
And in fig. 8, from top to bottom, a waveform diagram of capacitance voltage fluctuation of each sub-module, an average switching frequency waveform diagram of the sub-module, an instantaneous switching frequency waveform diagram of the sub-module, a waveform diagram of the maximum capacitance voltage difference of the bridge arm, a waveform diagram of a holding factor and a waveform diagram of active and reactive power transmitted by the system are respectively shown in the upper bridge arm of the a-phase. As shown in FIG. 8, the active power transmitted by the system in 0.6-0.72 s is 0.2-0.3 MW, the average switching frequency fluctuation of the submodule is small in the process, the given value can be effectively tracked, and the capacitance voltage of the submodule keeps running stably before and after the power of the system changes.
In summary, as shown by the simulation results, the method can realize accurate balanced control of the frequency and the voltage of the sub-module under the dynamic and steady states of the system, has good dynamic and steady state performance, and meets the actual requirements of engineering.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the invention in any way, and any person skilled in the art may make modifications or alterations to the disclosed technical content to the equivalent embodiments. However, any simple modification, equivalent variation and variation of the above embodiments according to the technical substance of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims (4)

1. The MMC type VSC-HVDC system submodule average frequency optimization control method is characterized by comprising the following steps of:
let the allowable fluctuation range of the capacitance voltage of the sub-module be U c_rate (100.+ -. ε)%, wherein U c_rate For the rated value of the capacitor voltage, epsilon is a set fluctuation range threshold value; adjusting a set holding factor h by a dual-loop PI controller;
if the bridge arm current charges the bridge arm submodule, the submodule with lower capacitance voltage is preferentially triggered; for capacitor voltages below U c_rate The submodule capacitance of (100-epsilon)% keeps the voltage value unchanged so as to ensure the preferential input of the submodule capacitance; for capacitor voltages higher than U c_rate (100-epsilon)% and the submodule capacitance not put into operation in the previous control period, multiplying the voltage value thereof by a holding factor h, thereby reducing the possibility of putting into operation in the next control period and increasing the capacitance voltage to be higher than U c_rate (100- ε)% and the likelihood that the submodule in the put-in state in the last period remains put-in;
if the bridge arm current discharges the bridge arm submodule, the submodule with higher capacitance voltage is preferentially triggered; for capacitor voltages higher than U c_rate Sub-module capacitance of (100+ε)% is kept constant to ensure that it is put into priority; for capacitor voltages below U c_rate (100+ε)% and the sub-module capacitance not being put into the previous control period, dividing its voltage value by a hold factor h, thereby reducing the likelihood of its being put into the next control period and increasing the capacitance voltage below U c_rate (100+ε)% and the possibility that the submodule in the put-in state in the last cycle remains put-in.
2. The MMC VSC-HVDC system sub-module average frequency optimization control method according to claim 1, characterized in that the sub-module is a half-bridge sub-module.
3. The MMC VSC-HVDC system submodule average frequency optimization control method according to claim 1, characterized in that the value of the retention factor h is determined by a double loop PI controller based on the retention factor, in particular:
obtaining the average switching frequency f of the sub-module through the frequency measurement module ava Average with given submoduleSwitching frequency f ref Comparing the calculated errors, then inputting the calculated errors into a first PI link, and calculating and outputting the maximum capacitance voltage difference delta U of a given bridge arm ref Will DeltaU ref Voltage difference with maximum capacitance of bridge arm, i.e. difference DeltaU between maximum value and minimum value of bridge arm capacitance voltage imb And comparing the calculated errors, inputting a second PI link, and calculating to obtain the value of the retention factor h.
4. The MMC-HVDC system submodule average frequency optimization control method according to claim 3, wherein the frequency measurement module takes a bridge arm as a unit and calculates the bridge arm switching frequency instantaneous value f in each control period ins Setting the length of a sampling window, and averaging the instantaneous value of the switching frequency in the sampling window to obtain the average switching frequency f of the submodule in the period of time ava The method comprises the steps of carrying out a first treatment on the surface of the The sampling window length l is taken as:
Figure FDA0003973382560000021
wherein k is a positive integer; f (f) s Is the frequency of the alternating current power grid; t (T) s Is a switching control period.
The instantaneous value of the bridge arm switching frequency is obtained by dividing the number of the switch state changes of the submodules of the bridge arm in two continuous control periods by twice the number of the submodules of the bridge arm and then dividing by the switch control period:
Figure FDA0003973382560000022
wherein N is sum The number of the switch state changes of the submodule in two continuous control periods; n is the number of bridge arm submodules; t (T) s Is a switching control period;
then the submodule average switching frequency f ava Expressed as:
Figure FDA0003973382560000023
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CN202211519944.0A 2022-11-30 2022-11-30 MMC VSC-HVDC system submodule average frequency optimization control method Pending CN116094352A (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117977919A (en) * 2024-03-29 2024-05-03 南昌工程学院 High-frequency suppression method for modularized multi-level converter and flexible direct current transmission system
CN117977919B (en) * 2024-03-29 2024-06-04 南昌工程学院 High-frequency suppression method for modularized multi-level converter and flexible direct current transmission system

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