CN115911006A - Packaging structure - Google Patents

Abstract

The application relates to the technical field of semiconductors, in particular to a packaging structure, which comprises a substrate, at least one first type wafer and at least one second type wafer, wherein the at least one first type wafer and the at least one second type wafer are positioned above the substrate, and each first type wafer and each second type wafer need to be isolated from each other; at least one set of capacitive structures for achieving isolation between the first type of wafer and the second type of wafer, wherein the capacitive structures are disposed outside the first type of wafer and the second type of wafer. By not placing the capacitor structure on the wafer, the production cost of the packaging structure is greatly reduced, the capacitance value of the parasitic capacitor of the packaging structure is also reduced, and the reliability of the packaging structure is greatly improved.

Description

Packaging structure

Technical Field

The present application relates to the field of semiconductor technology, and more particularly, to a package structure.

Background

In order to realize the isolation transmission of signals, the prior art is generally divided into three types, namely optical coupling transmission, electromagnetic transmission and capacitive transmission. Among them, the capacitive transmission technology is widely used because of its small chip area and high reliability. In the prior art, as shown in fig. 1, an isolation capacitor is located on a Die (Die) inside a chip, where the Die 11 is referred to as the primary side of the chip, the Die 12 is referred to as the secondary side of the chip, and the Die and the leads of the chip are connected by bonding wires. The isolation capacitor is a parallel plate capacitor composed of two metal layers of the chip. In order to realize a high insulation withstand voltage of the isolation capacitor, the distance between two plates of the parallel plate capacitor is generally larger than 10um.

In the prior art, to achieve a spacing between two plates>10um, two methods are generally used, method one: wafer 11 and wafer 12 are stacked with multiple layers of metal such that the separation between the two parallel plates of the isolation capacitor is >10um, and the cross-section of the parallel plate capacitor is shown in fig. 2. Taking 7 layers of intermetal dielectrics as an example, the intermetal dielectrics are generally made of silicon dioxide, the number of layers of the intermetal dielectrics is adjusted according to the insulation and voltage resistance level of the parallel plate capacitor, the higher the insulation and voltage resistance level of the parallel plate capacitor is, the more the number of layers of the intermetal dielectrics is, the isolation capacitor formed by the first metal structure 21a1 and the second metal structure 21b1 and the other isolation capacitor formed by the first metal structure 21a2 and the second metal structure 21b2 in fig. 2 are, and as the opposite area between the second metal structure 21b1 and the substrate of the isolation capacitor is large, the parasitic capacitor C is formed between the second metal structure 21b1 and the substrate _para And a parasitic capacitance C _para Is large, and likewise, the parasitic capacitance C between the second metal structure 21b2 of the other isolation capacitor and the substrate _para Is also large. In addition, in order to enhance signals, the driving capability of signals on the primary side needs to be increased, a differential amplifier needs to be designed on the secondary side, the design of the first method increases the cost and reduces the reliability, and in addition, the number of photomasks is increased by the process of stacking the dielectrics between the multiple metal layers, so that the cost of tape-out is greatly increased, and the production and manufacturing period is prolonged.

The second method comprises the following steps: different from the first method, as shown in fig. 3, the distance between the two electrode plates of the isolation capacitor is larger than 10um by using the metal interlayer dielectric with thicker partial thickness, and as can be seen from fig. 3, the third metal interlayer dielectric and the fourth metal interlayer dielectricThe texture is thickened and this scheme requires a reduced number of photomask layers compared to method one. However, the thicker third and fourth intermetal dielectrics can make the fabrication of the vias thereon more difficult. In addition, the same as the first method is that the facing area between the second metal structure 21b2 of the isolation capacitance and the Substrate (Substrate) is large, and thus the parasitic capacitance C is large _para The capacitance value of the second method is very large, the signal driving capability of the primary side still needs to be increased, a differential amplifier needs to be designed on the secondary side usually, the cost is increased and the reliability is reduced due to the design of the second method.

How to reduce the cost and how to improve the reliability of the circuit are technical problems which need to be solved urgently in an isolated chip.

Disclosure of Invention

In view of the above, it is necessary to provide a package structure to solve the technical problems of high manufacturing cost and low reliability of the package structure in the prior art.

An embodiment of the present application provides a package structure, including: the wafer-to-wafer separation device comprises a substrate, at least one first type wafer and at least one second type wafer, wherein the at least one first type wafer and the at least one second type wafer are positioned above the substrate, and each first type wafer and each second type wafer need to be separated; at least one capacitive structure for achieving isolation between the first type of wafer and the second type of wafer, wherein the capacitive structure is disposed outside the first type of wafer and the second type of wafer.

In one embodiment, the one capacitor structure includes one capacitor unit, and the capacitor unit includes: go up metal structure and metal structure down, it is located to go up metal structure the upper surface of base plate, metal structure is located the lower surface of base plate down, it sets up with metal structure down to go up metal structure relatively.

In one embodiment, the capacitor structure includes two groups of capacitor units, each of the capacitor units includes an upper metal structure and a lower metal structure, the upper metal structure is located on the upper surface of the substrate, the lower metal structure is located on the lower surface of the substrate, the upper metal structure and the lower metal structure in the same group are arranged oppositely, and the point positions of the lower metal structures in the two groups of capacitor units are the same.

In one embodiment, the lower metal structures of the two groups of capacitor units are connected through metal leads.

In one embodiment, two groups of the capacitor units share the same lower metal structure.

In one embodiment, the lower metal structure is exposed outside the package structure.

In one embodiment, the lower metal structure is encapsulated by insulation.

In one embodiment, within the package structure, the respective electrodes of the first type of die are connected to the upper metal structures of the respective capacitive elements by metal leads; the respective electrodes of the second type of die are connected to the lower metal structure of the respective capacitive cell by metal leads.

In one embodiment, within the package structure, the respective electrodes of the first type of die are connected to the upper metal structures of the respective capacitive elements by metal leads; the corresponding electrode of the second type wafer is connected to the other upper metal structure of the corresponding capacitor unit through a metal lead.

In one embodiment, a plurality of patterned first metal connection structures located on an upper surface of the substrate; the partial electrodes of the first type wafer and the second type wafer are connected to the first metal connecting structure through metal leads; a plurality of patterned second metal connection structures located on the lower surface of the substrate; and the conductive through hole is positioned in the substrate and used for electrically connecting the first metal connecting structure and the second metal connecting structure.

In one embodiment, the first type of die is placed on a top surface of a corresponding first metal connection structure; the second type wafer is placed on the upper surface of another corresponding first metal connection structure.

In one embodiment, the first metal connection structure and the lower metal structure do not overlap in a vertical direction.

In one embodiment, the first metal connection structure carrying the first type of wafer has a first ground potential; the first metal connection structure bearing the second type of wafer has a second ground potential, and the first ground potential and the second ground potential are different.

In one embodiment, the first type wafer and the second type wafer are located on opposite sides of the substrate, and the capacitor structure is located between the first type wafer and the second type wafer.

Compared with the related art, the packaging module provided by the embodiment of the application has the advantages that the isolation capacitor is not arranged on the wafer, so that the production cost of the isolation type chip is greatly reduced, the capacitance value of the parasitic capacitor is reduced, and the reliability of the packaging structure or the isolation type chip is improved. Therefore, the invention effectively overcomes various defects in the prior art and further has high industrial utilization value.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below to provide a more thorough understanding of the application.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the conventional technologies of the present application, the drawings used in the description of the embodiments or the conventional technologies will be briefly introduced below, it is obvious that the drawings in the description below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

FIG. 1 is a schematic diagram of a prior art package of a spacer chip;

FIG. 2 is a schematic cross-sectional view of a wafer during a first method of forming isolation capacitors on the wafer according to the prior art;

FIG. 3 is a schematic cross-sectional view of a wafer in a second prior art method when an isolation capacitor is on the wafer;

FIG. 4a is a schematic diagram of a package structure according to one embodiment of the present application;

FIG. 4b isbase:Sub>A cross-sectional view at A-A of FIG. 4base:Sub>A;

FIG. 5a is a schematic diagram of a package structure according to one embodiment of the present application;

FIG. 5B is a cross-sectional view at B-B in FIG. 5 a;

FIG. 6a is a schematic diagram of a package structure according to an embodiment of the present application;

FIG. 6b is a cross-sectional view at C-C of FIG. 6 a;

FIG. 7 is a schematic diagram of a package structure according to one embodiment of the present application;

fig. 8 is a schematic diagram of a package structure according to an embodiment of the present application.

Reference numerals

11. A first type of wafer; 12. a second type of wafer; 21. a first capacitor structure; 21a1, a first upper metal structure; 21a2, a second upper metal structure; 21b1, a first lower metal structure; 21b2, a second lower metal structure; 22. a second capacitor structure; 31. a first parasitic capacitance; 32. a second parasitic capacitance; 33. a third parasitic capacitance; 34. a fourth parasitic capacitance; 41. a first layer of inter-metal dielectric; 42. a second layer of inter-metal dielectric; 43. a third inter-metal layer dielectric; 44. a fourth layer of inter-metal dielectrics; 45. a fifth intermetal dielectric layer; 46. a sixth layer of inter-metal dielectrics; 47. a passivation layer; 51. a first metal connection structure; 52. a second metal connection structure; 6. a substrate; 7. a substrate; 8. a through hole; 9. and a metal lead.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided in the present application without any inventive step are within the scope of protection of the present application.

It is obvious that the drawings in the following description are only examples or embodiments of the present application, and that it is also possible for a person skilled in the art to apply the present application to other similar contexts on the basis of these drawings without inventive effort. Moreover, it should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the specification. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by one of ordinary skill in the art that the embodiments described herein may be combined with other embodiments without conflict.

Unless otherwise defined, technical or scientific terms referred to herein should have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Reference to "a," "an," "the," and similar words throughout this application are not to be construed as limiting in number, and may refer to the singular or the plural. The present application is directed to the use of the terms "including," "comprising," "having," and any variations thereof, which are intended to cover non-exclusive inclusions; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. Reference to "connected," "coupled," and the like in this application is not intended to be limited to physical or mechanical connections, but rather can include electrical connections, whether direct or indirect. The term "plurality" as referred to herein means two or more. "and/or" describes an association relationship of associated objects, meaning that three relationships may exist, for example, "A and/or B" may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. Reference herein to the terms "first," "second," "third," and the like, are merely to distinguish similar objects and do not denote a particular ordering for the objects.

Fig. 4base:Sub>A isbase:Sub>A schematic front view ofbase:Sub>A package structure according to an embodiment of the present application, and fig. 4b isbase:Sub>A cross-sectional view taken alongbase:Sub>A-base:Sub>A in fig. 4base:Sub>A, as shown in fig. 4base:Sub>A and 4b, in the embodiment, the package structure includes: a substrate 7 and at least one first type wafer 11 and at least one second type wafer 12 located above the substrate 7, each first type wafer 11 and second type wafer 12 requiring isolation therebetween.

The package structure further comprises at least one capacitor structure 21, in the embodiment of the present application, the number of the capacitor structures 21 is 2, the capacitor structures 21 are used for realizing the isolation between the first type wafer 11 and the second type wafer 12, wherein the capacitor structures 21 are disposed outside the first type wafer 11 and the second type wafer 12.

As shown in fig. 4a and 4b, in the present embodiment, the number of capacitor structures includes 2, namely, a capacitor structure 21 and a capacitor structure 22, and the number of capacitor structures is related to a given circuit on a wafer.

In the embodiment of the present application, the first type of chip 11 and the second type of chip 12, which are commonly referred to as dies, are chips that have not been packaged after the dicing test, and only the bonding pads (pads) for packaging, which are commonly referred to as electrodes of the chips, are provided on the dies, which cannot be directly applied to actual circuits. The bare chip is easily affected by the temperature, impurities and physical force of the external environment and is easily damaged, so the bare chip can be used as a basic component only by being sealed in a closed space and leading out corresponding pins. The wafer (die) is a small piece of semiconductor material on which the given functional circuitry is fabricated.

As shown in fig. 4a and 4b, in the embodiment of the present application, the package structure further includes a plurality of patterned first metal connection structures 51 located on the upper surface of the substrate 7; the respective electrodes of the first type wafer 11 and the second type wafer 12 are connected to the first metal connection structure 51 through metal leads 9. The package structure further comprises a plurality of patterned second metal connection structures 52 located on the lower surface of the substrate 7, and a conductive via 8 located in the substrate 7, the conductive via 8 being used to electrically connect the first metal connection structure 51 and the second metal connection structure 52.

In the present embodiment, the first type wafer 11 is placed on the upper surface of a corresponding first metal connection structure 51; the second type wafer 12 is placed on the upper surface of another corresponding first metal connection structure 51. Specifically, the first type wafer 11 is fixedly bonded to one of the first metal connection structures 51 through a conductive adhesive, and the second type wafer 12 is fixedly bonded to the other first metal connection structure 51 through a conductive adhesive.

In the embodiment of the present application, the first metal connection structure 51 is a layer of metal, and the first metal connection structure 51 has the following functions in a chip package: 1. the first metal connection structure 51 may implement an integrated package of the multifunctional module; 2. the first metal connection structure 51 performs a function of rapid heat dissipation.

Specifically, the second metal connection structure 52 is also a layer of metal, and the second metal connection structure 52 may be directly exposed as a chip pin in a chip package, or may be electrically connected to the chip pin.

In the present embodiment, the first metal connection structure 51 carrying the first type wafer 11 has a first ground potential; the first metal connection structure 51 carrying the second type of die 12 has a second ground potential, the first ground potential and the second ground potential being different.

In the embodiment of the present application, the first type wafer 11 and the second type wafer 12 are respectively located on two opposite sides of the substrate 7, and the capacitor structure 21 is located between the first type wafer 11 and the second type wafer 12.

In the embodiment of the present application, as shown in fig. 4b, a first parasitic capacitor 31 is formed between the upper metal structure 21a1 and the first metal connection structure 51, a second parasitic capacitor 32 is formed between the lower metal structure 21b and the first metal connection structure 51, a fourth parasitic capacitor 34 is formed between the upper metal structure 21a2 and the other first metal connection structure 51, and a third parasitic capacitor 33 is formed between the lower metal structure 21b and the other first metal connection structure 51, because a facing area between the upper metal structure 21a1 and the first metal connection structure 51 is small, and a facing area between the lower metal structure 21b and the first metal connection structure 51 is also small, a capacitance value of the second parasitic capacitor 32 and the first parasitic capacitor 31 is small, and based on the same reason, a capacitance value of the third parasitic capacitor 33 and the fourth parasitic capacitor 34 is small, a transmission signal of an isolated chip manufactured by using the package structure will not be attenuated too much, and reliability of the entire package structure is improved. Therefore, the manufacturing cost of the packaging structure is greatly reduced, and the reliability of the packaging structure is greatly improved.

In the embodiment of the present application, as shown in fig. 4b, the first metal connection structure 51 and the lower metal structure do not overlap in the vertical direction, and therefore, no facing area between the first metal connection structure 51 and the lower metal structure is small, and therefore, the capacitance values of the second parasitic capacitor 32 and the third parasitic capacitor 33 are small.

The package structure in the embodiment of the present application is packaged by any one of LGA, PGA, and BGA packaging methods. Specifically, LGA is called Land Grid Array, translating into chinese is Grid Array Package, PGA Package, english is called Pin Grid Array Package, chinese meaning is called Pin Grid Array Package, BGA is called ball Grid Array, or ball Grid Array Package.

In summary, in the embodiments of the present application, the capacitor structure between the first type wafer and the second type wafer is disposed on the package substrate, and compared with the prior art, the first type wafer and the second type wafer can both use a common low-voltage process, so that the manufacturing cost of the first type wafer and the second type wafer is greatly reduced. In addition, in the embodiment of the application, because the upper metal structure and the lower metal structure of the capacitor unit are respectively arranged on the upper surface and the lower surface of the substrate, the dead-against area between the capacitor structure and the first type wafer and between the capacitor structure and the second type wafer is very small, the parasitic capacitance of the capacitor unit to the ground is very small, and therefore, the embodiment of the application can also reduce the influence of the parasitic capacitance, so that the transmission signal of the isolated chip manufactured by adopting the packaging structure cannot be greatly attenuated, and the reliability of the whole packaging structure is greatly improved.

In one embodiment, as shown in fig. 5a and 5B, fig. 5a is a schematic front view of a package structure according to one embodiment of the present application, and fig. 5B is a cross-sectional view at B-B in fig. 5 a. A capacitor structure 21 comprises a capacitor unit, the capacitor unit comprises an upper metal structure 21a and a lower metal structure 21b, the upper metal structure 21a is located on the upper surface of the substrate 7, the lower metal structure 21b is located on the lower surface of the substrate 7, and the upper metal structure 21a and the lower metal structure 21b are oppositely arranged.

In the package structure of the present embodiment, the respective electrodes of the first type of die 11 are connected to the upper metal structures 21a of the respective capacitor cells through the metal leads 9; the corresponding electrodes of the second type chip 12 are connected to the lower metal structures 21b of the corresponding capacitor units through the metal leads 9, and similarly, the substrate may be provided with conductive through holes 8, and the conductive through holes 8 are used for electrically connecting the second type chip 12 with the lower metal structures 21b of the corresponding capacitor units.

In other embodiments, one group of capacitor structures 21 may also include two groups of capacitor units, as shown in fig. 6a and 6b, where fig. 6a is a front schematic view of a package structure according to one embodiment of the present application, and fig. 6b is a cross-sectional view at C-C in fig. 6 a. The capacitor unit comprises an upper metal structure and a lower metal structure, the upper metal structure is located on the upper surface of the substrate, the lower metal structure is located on the lower surface of the substrate, the upper metal structure and the lower metal structure in the same group are arranged oppositely, and the potentials of the lower metal structures of the two groups of capacitor units are the same.

Specifically, as shown in fig. 6a and 6b, the capacitor structure 21 includes a first capacitor unit composed of an upper metal structure 21a1 and a lower metal structure 21b1, and a second capacitor unit composed of an upper metal structure 21a2 and a lower metal structure 21b2, where the upper metal structure 21a1 and the lower metal structure 21b1 are disposed opposite to each other, and the upper metal structure 21a2 and the lower metal structure 21b2 are disposed opposite to each other. The lower metal structure 21b1 and the lower metal structure 21b2 are connected together by a metal wire 9.

In the package structure of the present embodiment, the respective electrodes of the first type of die 11 are connected to the upper metal structures 21a1 of the respective capacitor cells through the metal leads 9; the respective electrodes of the second type wafer 12 are connected to the further upper metal structure 21a2 of the respective capacitive cell by means of metal leads 9.

In other embodiments, two capacitor units may share the same lower metal structure. As shown in fig. 4a and 4b, which are not described herein.

In one embodiment, the lower metal structure is exposed outside the package structure.

In one embodiment, the lower metal structure is encapsulated with insulation.

In one embodiment, fig. 7 is a schematic front view of a package structure according to one embodiment of the present application, as shown in fig. 7, in the present embodiment, the number of the capacitor structures 21 is 8, the first type of chip 11 is fixedly attached to the first metal connection structure 51 through a conductive adhesive, the second type of chip 12 is fixedly attached to another first metal connection structure 51 through a conductive adhesive, corresponding electrodes of the first type of chip 11 are connected to upper metal structures of corresponding capacitor units through metal leads 9, corresponding electrodes of the second type of chip 12 are connected to lower metal structures of corresponding capacitor units through metal leads 9, in the present embodiment, a group of capacitor structures may include 1 capacitor unit or 2 capacitor units, lower metal structures of 2 capacitor units are connected through metal leads, or 2 capacitor units share a lower metal structure, in the present embodiment, a group of capacitor structures may include 1 capacitor unit. The packaging structure also comprises other first metal connecting structures 51, the first metal connecting structures 51 are fixedly connected to the upper surface of the packaging substrate 7, corresponding electrodes of the first type of wafer 11 are connected to the corresponding first metal connecting structures 51 through metal leads 9, corresponding electrodes of the second type of wafer 12 are connected to the other first metal connecting structures 51 corresponding to the second type of wafer 12 through metal leads 9, the packaging structure also comprises a plurality of second metal connecting structures 52 and conductive through holes 8, and the conductive through holes 8 are used for electrically connecting the first metal connecting structures 51 and the second metal connecting structures 52.

The embodiment of the application can realize 4-channel bidirectional isolation, 4 paths of signals are transmitted by adopting 8 differential lines, and each differential line is provided with two capacitors which are connected in series, so that 16 capacitor structures are totally formed. All of these capacitor structures are designed on the package substrate, so the first type wafer 11 and the second type wafer 12 can be manufactured by a common low-voltage process, instead of the stacking of multiple metal layers in the prior art, and the cost of the wafer manufactured by the common low-voltage process is greatly reduced compared with the wafer manufactured by the stacking of multiple metal layers. In addition, in the embodiment of the application, because the capacitance value of the parasitic capacitance is greatly reduced, the parasitic capacitance of the differential line to the ground can also be greatly reduced.

In summary, in the embodiment of the present application, the capacitor structure between the first type wafer 11 and the second type wafer 12 is disposed on the package substrate, and compared with the prior art, both the first type wafer 11 and the second type wafer 12 can use a common low-voltage process, so that the manufacturing cost of the first type wafer and the second type wafer is greatly reduced. Similarly, because the upper metal structure and the lower metal structure of the capacitor unit are respectively arranged on the upper surface and the lower surface of the substrate, the dead-against area between the capacitor structure and the first type wafer and the second type wafer is very small, so the parasitic capacitance of the capacitor unit to the ground is very small, and the influence of the parasitic capacitance can be reduced, so the transmission signal of the isolation type chip manufactured by adopting the packaging structure cannot be greatly attenuated, and the reliability of the whole packaging structure is greatly improved.

In one embodiment, fig. 8 is a schematic front view of a package structure according to one embodiment of the present application, as shown in fig. 8, in this embodiment, the number of the capacitor structures 21 is 4, the number of the second type of die is 2, and the second type of die is a second type of die 12a and a second type of die 12b, respectively, the first type of die 11 is fixedly attached to the first metal connection structure 51 by a conductive adhesive, and the second type of die 12b is also fixedly attached to the first metal connection structure 51 different from the first two by a conductive adhesive.

In this embodiment, a group of capacitor structures may include 1 capacitor unit, or may include 2 capacitor units, and the lower metal structures of the 2 capacitor units are connected by a metal lead, or the 2 capacitor units share one lower metal structure. The corresponding electrodes of the first type wafer 11 are connected to the upper metal structures of the corresponding capacitor units through metal leads 9, the corresponding electrodes of the second type wafer 12 are connected to the other upper metal structures of the corresponding capacitor units through metal leads 9, the first type wafer 11 and the second type wafer 12a are isolated through two groups of capacitor structures, and the first type wafer 11 and the second type wafer 12b are isolated through the other two groups of capacitor structures.

The package structure further comprises other first metal connection structures 51, the first metal connection structures 51 are fixedly connected to the upper surface of the package substrate 7, the corresponding electrodes of the first type of die 11 are connected to the corresponding first metal connection structures 51 through metal leads 9, and the corresponding electrodes of the second type of die 12 are connected to the other first metal connection structures 51 corresponding to the second type of die 12 through metal leads 9. The package structure further includes a plurality of second metal connection structures 52 and through holes 8, where the through holes 8 are used to electrically connect the first metal connection structures 51 and the second metal connection structures 52.

This embodiment can realize 2 passageway isolation half-bridge drives, and 2 way signals adopt 4 differential lines to transmit, has two electric capacity units to establish ties on every differential line, so total has 8 isolation capacitance. All these capacitors are designed on the substrate, so that the first type wafer 11, the second type wafer 12a and the second type wafer 12b can use common low-voltage process, and the manufacturing cost can be great. In addition, the parasitic capacitance of the differential line to the ground can be greatly reduced.

In summary, in the embodiment of the present application, the isolation capacitor between the primary side control circuit and the secondary side control circuit is disposed on the package substrate, and compared with the prior art, both the first chip and the second chip can use a common low voltage process, thereby greatly reducing the manufacturing cost of the chip. In addition, the influence of parasitic capacitance generated between the second metal structure and the substrate is eliminated, and the parasitic capacitance of the isolation capacitor to the ground is very small, so that transmission signals are not greatly attenuated, and the reliability is greatly improved.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

In the description herein, references to "some embodiments," "other embodiments," "desired embodiments," or the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, a schematic description of the above terminology may not necessarily refer to the same embodiment or example.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several implementation modes of the present application, and the description thereof is specific and detailed, but not construed as limiting the scope of the claims. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (14)

1. A package structure, comprising:

a substrate, a plurality of first electrodes and a plurality of second electrodes,

at least one wafer of a first type and at least one wafer of a second type located above the substrate,

each wafer of the first type and each wafer of the second type need to be isolated from each other;

at least one capacitive structure for achieving isolation between the first type of wafer and the second type of wafer, wherein the capacitive structure is disposed outside the first type of wafer and the second type of wafer.

2. The package structure of claim 1,

the capacitor structure comprises a capacitor unit, the capacitor unit comprises an upper metal structure and a lower metal structure, the upper metal structure is located on the upper surface of the substrate, the lower metal structure is located on the lower surface of the substrate, and the upper metal structure and the lower metal structure are arranged oppositely.

3. The package structure of claim 1,

the capacitor structure comprises two groups of capacitor units, each capacitor unit comprises an upper metal structure and a lower metal structure, the upper metal structure is located on the upper surface of the substrate, the lower metal structure is located on the lower surface of the substrate, the upper metal structure and the lower metal structure are arranged oppositely and are in the same group, and the potentials of the lower metal structures of the capacitor units are the same.

4. The package structure of claim 3, wherein the lower metal structures of the two sets of capacitor units are connected by metal leads.

5. The package structure of claim 3, wherein the two sets of capacitor units share a same lower metal structure.

6. The encapsulation structure according to claim 2, 4 or 5,

the lower metal structure is exposed outside the packaging structure.

7. The package structure of claim 2 or 4 or 5,

the lower metal structure is encapsulated by insulation.

8. The package structure of claim 2,

within the package structure, the respective electrodes of the first type of die are connected to the upper metal structure of the respective capacitive unit by metal leads; the respective electrodes of the second type of die are connected to the lower metal structure of the respective capacitive cell by metal leads.

9. The encapsulation structure according to claim 3, 4 or 5,

within the package structure, the respective electrodes of the first type of die are connected to the upper metal structure of the respective capacitive unit by metal leads; the corresponding electrode of the second type wafer is connected to the other upper metal structure of the corresponding capacitor unit through a metal lead.

10. The package structure of claim 1, further comprising:

a plurality of patterned first metal connection structures located on an upper surface of the substrate;

the partial electrodes of the first type wafer and the second type wafer are connected to the first metal connecting structure through metal leads;

a plurality of patterned second metal connection structures located on the lower surface of the substrate;

and the conductive through hole is positioned in the substrate and used for electrically connecting the first metal connecting structure and the second metal connecting structure.

11. The package structure of claim 10,

the first type wafer is placed on the upper surface of a corresponding first metal connecting structure;

the second type wafer is placed on the upper surface of another corresponding first metal connection structure.

12. The package structure of claim 11,

the first metal connection structure carrying the first type of wafer has a first ground potential; the first metal connection structure bearing the second type of wafer has a second ground potential, and the first ground potential and the second ground potential are different.

13. The package structure of claim 10, wherein the first metal connection structure and the lower metal structure do not overlap in a vertical direction.

14. The package structure of claim 1,

the first type wafer and the second type wafer are respectively positioned on two opposite sides of the substrate, and the capacitor structure is positioned between the first type wafer and the second type wafer.

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