CN115910942A - 包括带有暴露的接触部的凹陷的半导体封装和半导体模块 - Google Patents

包括带有暴露的接触部的凹陷的半导体封装和半导体模块 Download PDF

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CN115910942A
CN115910942A CN202211126624.9A CN202211126624A CN115910942A CN 115910942 A CN115910942 A CN 115910942A CN 202211126624 A CN202211126624 A CN 202211126624A CN 115910942 A CN115910942 A CN 115910942A
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semiconductor
semiconductor package
recess
electrical connector
pad
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CN202211126624.9A
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J·特罗伊
I·尼基廷
B·施默尔泽
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10659—Different types of terminals for the same component, e.g. solder balls combined with leads
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    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10742—Details of leads
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    • H05K2201/10939—Lead of component used as a connector

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Abstract

本文公开了一种半导体封装(10；20)，其包括：衬底(11)；设置在衬底(11)上的至少一个半导体管芯(12)；与半导体管芯(12)连接的至少一个电连接器(13)；覆盖衬底(11)、至少一个半导体管芯(12)并至少部分覆盖电连接器(13)的包封体(14)，包封体(14)包括形成到包封体(14)的主表面中的凹陷(14A)；其中，至少一个电连接器(13)在凹陷(14A)内暴露。

Description

包括带有暴露的接触部的凹陷的半导体封装和半导体模块
技术领域
本公开涉及半导体封装和包括这样的半导体封装的半导体模块。
背景技术
在半导体工业中，正不断努力以提高集成密度。由于印刷电路板上的面积相当的昂贵，更高的集成度对客户是有利的。此外，为了提高性能，在栅极连接和栅极驱动器之间的距离需要尽可能短。另一方面，需要保持信号引脚(栅极、感测)和电源引脚(源极、漏极)之间的最小距离，从而实现所需的爬电和净空距离。这限制了用于更高的电压域的具有标准引线构造的最小封装尺寸。
此外，大的封装仍然需要保持低的封装弯曲，从而与散热器有足够的热接触。一种解决方案是采用更厚的封装。然而，这种增加的体积通常不具有额外的好处。
由于这些原因和其它原因，需要本公开。
发明内容
本公开的第一方面涉及一种半导体封装，包括：衬底；设置在衬底上的至少一个半导体管芯；与半导体管芯连接的至少一个电连接器；覆盖衬底、至少一个半导体管芯并至少部分覆盖电连接器的包封体，该包封体包括形成到包封体的主表面中的凹陷，其中，至少一个电连接器在凹陷内暴露。
本公开的第二方面涉及一种半导体模块，包括：半导体封装，该半导体封装包括：衬底；设置在衬底上的至少一个半导体管芯，该半导体管芯包括至少一个电连接器；覆盖衬底、至少一个半导体管芯并至少部分覆盖电连接器的包封体，该包封体包括形成到包封体的主表面中的凹陷，其中，至少一个电连接器在凹陷内暴露；以及设置在凹陷中或凹陷上的印刷电路板，该印刷电路板包括设置在其上的栅极驱动器芯片，该栅极驱动器芯片与暴露的电连接器电连接。
附图说明
附图被包括进来以提供对实施例的进一步理解，并且被并入并且构成本说明书的一部分。附图示出了实施例，并且与描述一起用于解释实施例的原理。其它实施例和实施例的许多预期的优点将是容易理解的，因为通过参考以下的详细描述，它们变得更好理解。
附图的元件未必相对于彼此成比例。相似的附图标记指代对应的相似部分。
图1A和图1B示出了半导体封装的示例的示意性的横截面侧视图(A)和透视图(B)。
图2示出了提供有压配销和栅极驱动器芯片的半导体封装的示例的透视图。
图3示出了半导体模块的示例的示意性的横截面侧视图，该半导体模块包括通过压配销连接到半导体封装的印刷电路板。
图4示出了半导体模块的示例的示意性的透视图，该半导体模块在其后表面上包括多个无源器件。
图5A和图5B示出了包括位于凹陷的底表面上的多个暴露的导线的半导体封装的透视图(A)，以及包括图5A的半导体封装的半导体模块的透视图。
图6示出了半导体模块的示例的示意性的横截面侧视图，该半导体模块包括连接到半导体封装的印刷电路板，在该半导体封装中半导体管芯包括分流器，并且导线环路在分流器的两个相对端连接到分流器。
图7A至图7C以俯视图(A)和横截面侧视图(B)示出了半导体模块，在该半导体模块中半导体封装的凹陷沿一个横向维度延伸直到包封体的相对的边缘，并且示出了半导体模块的俯视图(C)，在该半导体模块中PCB延伸到相邻的半导体封装。
具体实施方式
在以下详细描述中，参考了形成本文的一部分的附图，并且在附图中以图示的方式示出了可以实践本公开的具体实施例。在这方面，参考正被描述的(多个)图的取向使用方向性术语，例如“顶部”、“底部”、“前”、“后”、“前导”、“尾随”等。因为实施例的部件可以定位在多个不同的取向上，所以方向性术语用于说明的目的并且绝不是限制性的。应当理解，可以利用其它实施例并且可以做出结构的或逻辑的改变，而不背离本公开的范围。因此，以下详细描述不应当被视为限制性意义，并且本公开的范围由所附权利要求限定。
应当理解，除非另有特别说明，否则本文描述的各个示例性的实施例的特征可以相互组合。
如在本说明书中采用的，术语“接合”、“附接”、“连接”、“耦接”和/或“电连接/电耦接”并不意味着表示元件或层必须直接接触在一起；在“接合”、“附接”、“连接”、“耦接”和/或“电连接/电耦接”的元件之间可以分别提供介于中间的元件或层。然而，根据本公开，上述术语可以可选地还具有元件或层直接接触在一起的特定含义，即，在“接合”、“附接”、“连接”、“耦接”和/或“电连接/电耦接”的元件之间没有分别提供介于中间的元件或层。
此外，相对于形成于或位于表面“之上”的部分、元件或材料层使用的词语“之上”在本文中可以用于表示该部分、元件或材料层“间接地”位于(例如，放置于、形成于、沉积于等)暗指的表面上，其中一个或多个额外的部分、元件或层布置在暗指的表面和该部分、元件或材料层之间。然而，相对于形成于或位于表面“之上”的部分、元件或材料层使用的词语“之上”可以可选地还具有特定含义，即部分、元件或材料层“直接地”位于(例如、放置于、形成于、沉积于等)暗指的表面上，例如与暗指的表面直接接触。
详细说明
图1A和图1B示出了半导体封装的示例的示意性的横截面侧视图(A)和透视图(B)。
更具体地，图1示出了包括引线框架11的半导体封装10，引线框架11包括水平基板11.1和从封装10延伸出的外部引线11.2。至少一个半导体管芯12设置在引线框架11的水平基板11.1上。半导体管芯12可以是类似于例如IGBT管芯或MOSFET管芯的半导体晶体管管芯12。为此，半导体晶体管管芯12在它的上主面上包括源极焊盘12A、栅极焊盘12B，并且可能还包括源极感测焊盘。
半导体封装10还包括至少一个电连接器13，电连接器13与半导体管芯12连接。电连接器13可以是接合导线、带或夹具，并且它可以与半导体晶体管管芯12的栅极焊盘12B连接。
半导体封装10还包括包封体14，包封体14覆盖水平基板11.1、至少一个半导体管芯12并至少部分覆盖电连接器13，包封体14包括形成到包封体14的主表面中的凹陷14A。至少一个电连接器13在凹陷14A的底表面处暴露。
在图1A和图1B的实施例中，仅示出了一个暴露的电连接器13，其与半导体晶体管管芯12的栅极焊盘12B连接。然而，有可能布置多个暴露的电连接器(特别是接合导线)，以用于不同的目的。
特别地，两个或更多个半导体晶体管管芯有可能设置在凹陷14A的底表面上。半导体晶体管管芯可以互连以形成电路，类似于例如半桥电路、全桥电路、DC-DC转换器、DC-AC转换器或AC-DC转换器。在这些电路中的每个电路中，相应的半导体晶体管管芯的栅极焊盘可以与类似于图1A和图1B的电连接器13的电导体连接，并且这些电连接器的部分或全部可以在凹陷14A的底表面处暴露。
在图1A和图1B的实施例中，半导体封装10还包括虚设焊盘，其中，电连接器13以一端与栅极焊盘12B连接并且以另一端与虚设焊盘连接。
电连接器13也有可能以其两端与栅极焊盘连接，从而不需要虚设焊盘。
凹陷14A的高度可以是包封体14的厚度的一半。包封体14的厚度可以在从4mm至6mm的范围内。除此之外，凹陷14A可以具有矩形或二次型的形状。
图2示出了提供有压配销和栅极驱动器芯片的半导体封装的示例的透视图。
如图2所示的半导体封装20可以类似于结合图1A和图1B示出和描述的半导体封装10，从而使用相同的附图标记。除了图1A和图1B的半导体封装10之外，半导体封装20还包括压配销21，特别是弹簧针21，其连接到暴露的接合导线13。弹簧针21用于将印刷电路板连接到封装(例如，这可以在客户侧完成)的目的。此外，除了图1A和图1B的半导体封装10之外，半导体封装20还包括应用到凹陷14A的底表面的栅极驱动器芯片22。栅极驱动器芯片22与半导体晶体管管芯的栅极焊盘连接，由此提供驱动器芯片和栅极焊盘之间的短距离。弹簧针21可以附接到暴露的接合导线13，并且栅极驱动器芯片22可以通过类似于例如焊接、粘合剂接合或胶合的常规方式附接到凹陷14A的底表面。
图3示出了半导体模块的示例的示意性的横截面侧视图，该半导体模块包括通过压配销连接到半导体封装的印刷电路板。
如图3所示的半导体模块100包括半导体封装20，该半导体封装20可以类似于结合图2示出和描述的半导体封装20，从而使用相同的附图标记。因此，半导体封装20包括包封体14和形成在包封体14的主表面中的凹陷14A。
与图2相比，出于简单和清楚的原因，图3中省略了半导体封装20的一些细节。特别地，半导体封装20可以包括引线框架，该引线框架包括水平基板和从半导体封装20延伸出的外部引线。至少一个半导体管芯可以设置在引线框架的水平基板上。半导体管芯可以是类似于例如IGBT管芯或MOSFET管芯的半导体晶体管管芯。半导体晶体管管芯可以在它的上主面上包括源极焊盘、栅极焊盘，并且可能还包括源极感测焊盘。类似于例如接合导线13的电连接器13在包封体14的凹陷14A的底表面处暴露。接合导线13可以与半导体晶体管管芯的栅极焊盘连接。
半导体模块100还包括印刷电路板(PCB)50，其通过压配销21连接到半导体封装。PCB可以是例如可于商业上获得的所谓的穿孔板(perfboard)，穿孔板是包括多个穿孔的PCB，优选地是具有相当低密度的穿孔的PCB。然后可以使用穿孔中的一个与压配销21连接。
PCB还可以通过其它方式与半导体封装连接。特别地，半导体封装不需要具有压配销，并且PCB可以通过将它的面向凹陷的主表面焊接、粘合剂接合或胶合到半导体封装的主表面来连接到半导体封装。
PCB 50还包括设置在面向凹陷14A的主面上的栅极驱动器芯片51。栅极驱动器芯片51与半导体晶体管管芯的栅极焊盘连接，由此提供驱动器芯片51和栅极焊盘之间的短距离。
PCB 50还可以在它的主表面中的一个或两个上包括无源器件，例如电阻器、电容器或线圈。
图4示出了半导体模块的示例的示意性的透视图，该半导体模块在其后表面上包括多个无源器件。
图4的半导体模块200包括半导体封装30，半导体封装30可以类似于结合图1A、图1B或图2示出和描述的半导体封装10或20中的任一个。因此，半导体封装30包括包封体34和形成到包封体34的主表面中的凹陷34A。特别地，半导体封装30可以包括引线框架31，引线框架31包括水平基板(在图中不可见)和从半导体封装30延伸出的外部引线31.1。至少一个半导体管芯(图中不可见)可以设置在引线框架31的水平基板上。半导体管芯可以是类似于例如IGBT管芯或MOSFET管芯的半导体晶体管管芯。半导体晶体管管芯可以在它的上主面上包括源极焊盘、栅极焊盘，并且可能还包括源极感测焊盘。类似于例如接合导线(图中不可见)的电连接器在包封体34的凹陷34A的底表面处暴露。接合导线可以与半导体晶体管管芯的栅极焊盘连接。
半导体模块200还包括印刷电路板(PCB)150，PCB 150连接到半导体封装30，这可以以与结合图3描述的相同方式通过压配销(如弹簧针)来完成，或者通过将PCB 150的主表面与半导体封装30焊接、粘合剂接合或胶合在一起来完成。在图4的实施例中，这里提供的是，PCB 150具有略小于凹陷34A的内部尺寸的外部尺寸，并且PCB插入到凹陷34A中。
PCB 150可以包括栅极驱动器芯片(图中不可见)，类似于图3的实施例，该栅极驱动器芯片设置在面向凹陷34A的主表面上。此外，PCB 150可以包括多个无源器件151，其设置在远离凹陷34A的主表面上。无源器件151可以例如是电阻器、电容器或线圈。此外，这样的无源器件也可以设置在面向凹陷34A的主表面上。
图5A和图5B示出了包括位于凹陷的底表面上的多个暴露的导线的半导体封装的透视图(A)以及包括图5A的半导体封装的半导体模块的透视图。
图5A的半导体封装40可以类似于结合图1A、图1B或图2示出和描述的半导体封装10或20中的任一个。相应地，半导体封装40包括包封体44和形成到包封体44的主表面中的凹陷44A。特别地，半导体封装40可以包括引线框架41，引线框架41包括水平基板(图中不可见)和从半导体封装40延伸出的外部引线41.1。两个或更多个半导体管芯(图中不可见)可以设置在引线框架41的水平基板上。半导体管芯可以是类似于例如IGBT管芯或MOSFET管芯的半导体晶体管管芯，或者是半导体二极管管芯。半导体晶体管管芯可以均在它的上主面上包括源极焊盘、栅极焊盘，并且可能还包括源极感测焊盘。多个类似于例如接合导线43的电连接器43在包封体44的凹陷44A的底表面处暴露。接合导线43可以与半导体晶体管管芯的栅极焊盘连接。
如图5B所示的半导体模块300包括图5A的半导体封装40，并且还包括印刷电路板(PCB)250，PCB 250连接到半导体封装40，这可以以与结合图3描述的相同方式通过压配销(如弹簧针)来完成，或者通过将PCB 250的主表面与半导体封装40焊接、粘合剂接合或胶合在一起来完成。类似于图4的实施例，这里提供的是，PCB 250具有略小于凹陷44A的内部尺寸的外部尺寸，并且PCB 250插入到凹陷44A中
PCB 250可以包括设置在主表面上的栅极驱动器芯片(图中不可见)，类似于图3和图4的实施例，该主表面面向凹陷44A。此外，PCB 250可以包括设置在远离凹陷44A的主表面上的多个无源器件251。无源器件251可以例如是电阻器、电容器或线圈。此外，这样的无源器件也可以设置在面向凹陷44A的主表面上。
图6示出了半导体模块的示例的示意性的横截面侧视图，该半导体模块包括连接到半导体封装的印刷电路板，在该半导体封装中半导体管芯包括分流器，并且导线环路在分流器的两个相对端连接到分流器。
图6的半导体封装50可以类似于结合图1A、图1B或图2示出和描述的半导体封装10或20中的任一个。相应地，半导体封装50包括包封体54和形成到包封体54的主表面中的凹陷54A。特别地，半导体封装40可以包括类似于图1或图2的半导体封装10或20的进一步细节，例如引线框架、引线、半导体管芯(例如半导体晶体管管芯或半导体二极管管芯)。然而，对于图6的实施例更重要的是以下内容。
即，半导体封装50还包括连接在两个电源接触部52和53之间的分流器51，提供分流器51以允许电流的测量。为此，分流器51通过相应的两个焊接层在分流器51的相对端上连接到两个电源接触部52和53。此外，两个导线环路55和56附接在两个电源接触部52和53上方的分流器51的相对端上。
半导体模块400包括半导体封装50，并且还包括印刷电路板(PCB)350，PCB 350连接到半导体封装50，这可以如先前结合图3至图5B的实施例所描述的那样来完成。类似于图4的实施例，这里提供的是，PCB 350具有小于凹陷54A的内部尺寸的外部尺寸，并且PCB 350插入到凹陷54A中。
PCB 350还包括位于其下主面处的两个接触焊盘351和352，两个接触焊盘351和352连接到半导体封装50的两个导线环路55和56。两个接触焊盘351和352可以与适当的电路系统相连接以确定测量的电流。
应该提到的是，除了导线环路55和56，也可以使用简单的线性接合，例如接合导线。然而，已经表明，就电流测量中的非常低的误差而言，使用导线环路55和56是有利的。
图7A至图7C以俯视图(A)和沿图7A中的线B-B的横截面侧视图(B)示出了半导体模块，在该半导体模块中半导体封装的凹陷沿一个横向维度延伸直到包封体的相对的边缘，并且示出了半导体模块的俯视图(C)，在该半导体模块中PCB延伸到相邻的半导体封装。
图7A至图7C的半导体模块500包括半导体封装60，半导体封装60可以类似于结合图1A、图1B或图2所示和描述的半导体封装10或20中的任一个。因此，半导体封装60包括包封体64和形成到包封体64的主表面中的凹陷64A。特别地，半导体封装60可以包括引线框架61，引线框架61包括水平基板61.1和从半导体封装60延伸出的外部引线(未示出)。至少一个半导体管芯62可以设置在引线框架61的水平基板61.1上。半导体管芯62可以是类似于例如IGBT管芯或MOSFET管芯的半导体晶体管管芯。半导体晶体管管芯62可以在它的上主面上包括源极焊盘、栅极焊盘，并且可能还包括源极感测焊盘。类似于例如接合导线63的电连接器63在包封体64的凹陷64A的底表面处暴露。接合导线63可以与半导体晶体管管芯的栅极焊盘连接。
如图7A中可见的，半导体封装60与前述实施例的半导体封装的不同之处在于，凹陷64A延伸直到包封体64的相对的边缘。
半导体模块500还包括印刷电路板(PCB)450，PCB 450连接到半导体封装60，这可以以与结合图3描述的相同方式通过压配销(如弹簧针)来完成，或通过将PCB 450的主表面和半导体封装60焊接、粘合剂接合或胶合在一起来完成。在图7A至图7C的实施例中，这里提供的是，PCB 450具有略小于凹陷64A的内部尺寸的外部尺寸并且PCB 450插入到凹陷64A中。
PCB 450可以包括设置在主表面上的栅极驱动器芯片(未示出)，类似于图3的实施例，该主表面面向凹陷64A。此外，PCB 450可以包括设置在远离凹陷64A的主表面上的多个无源器件(未示出)。例如，无源器件可以是电阻器、电容器或线圈。此外，这样的无源器件也可以设置在面向凹陷64A的主表面上。
图7C的半导体模块600包括半导体封装60，其可以类似于图7A和图7B的半导体封装60，从而使用相同的附图标记。半导体封装60以与另一个半导体封装70横向并排的关系布置，可以以与半导体封装60类似的方式设计半导体封装70。此外，半导体模块600包括PCB550，PCB 550延伸超出半导体封装60的相对的边缘并且甚至延伸到相邻的半导体封装70的凹陷中。除此之外，PCB 550可以具有与图7A和图7B的PCB 450相似的性质。
还应提及的是，以上结合功率模块提及的任何示例、实施例、特征、评注或评论应当理解为也公开了用于提供或制造相应的器件特征的相应的方法步骤。
示例
在下文中，描述了本公开的具体示例。
示例1是一种半导体封装，包括：衬底；设置在衬底上的至少一个半导体管芯；与半导体管芯连接的至少一个电连接器；覆盖衬底、至少一个半导体管芯并至少部分覆盖电连接器的包封体，该包封体包括形成到包封体的主表面中的凹陷，其中，至少一个电连接器在凹陷内暴露。
示例2是根据示例1的半导体封装，其中，半导体管芯包括至少一个接触焊盘，并且电连接器以它的两端与接触焊盘连接。
示例3是根据示例1的半导体封装，还包括：虚设焊盘，其中，半导体管芯包括至少一个接触焊盘，并且电连接器以一端与接触焊盘连接并以另一端与虚设焊盘连接。
示例4是根据前述示例中任何一项的半导体封装，其中，半导体管芯是包括源极焊盘、栅极焊盘和源极感测焊盘中的一个或多个的半导体晶体管管芯，并且电连接器与源极焊盘、栅极焊盘或源极感测焊盘连接。
示例5是根据示例1的半导体封装，其中，半导体管芯包括分流器，并且电连接器与分流器连接。
示例6是根据前述示例中任何一项的半导体封装，其中，电连接器是导线、带或夹具中的一种。
示例7是根据前述示例中任何一项的半导体封装，其中，凹陷的高度小于包封体的高度的一半。
示例8是根据前述示例中任何一项的半导体封装，还包括：压配销、弹簧针或焊接焊盘中的一个或多个，其中的一个连接到暴露的电连接器。
示例9是根据前述示例中任何一项的半导体封装，其中，电连接器的材料基于Al、Cu或Au。
示例10是根据前述示例中任何一项的半导体封装，其中，半导体管芯基于Si、SiC或GaN。
示例11是根据前述示例中任何一项的半导体封装，其中，凹陷沿一个横向维度延伸直到包封体的相对的边缘。
示例12是根据前述示例中任何一项的半导体封装，其中，电连接器在凹陷的底表面处暴露。
示例13是一种半导体模块，包括：半导体封装，该半导体封装包括：衬底；设置在衬底上的至少一个半导体管芯，该半导体管芯包括至少一个电连接器；覆盖衬底、至少一个半导体管芯并至少部分覆盖电连接器的包封体，该包封体包括形成到包封体的主表面中的凹陷，其中，至少一个电连接器在凹陷内暴露；以及设置在凹陷中或凹陷上的印刷电路板，该印刷电路板包括设置在其上的栅极驱动器芯片，该栅极驱动器芯片与暴露的电连接器电连接。
示例14是根据示例13的半导体模块，其中，印刷电路板还包括设置在其上的一个或多个无源器件，该一个或多个无源器件至少部分地与暴露的电连接器电连接。
示例15是根据示例13或14的半导体模块，其中，印刷电路板通过压配销、弹簧针或焊接焊盘中的一个或多个连接到包封体，其中的一个连接到暴露的电连接器。
示例16是根据示例15的半导体模块，其中，压配销、弹簧针或焊接焊盘中的一个或多个连接到暴露的电连接器。
示例17是根据示例13至16中任何一项的半导体模块，其中，凹陷的高度小于包封体的高度的一半。
示例18是根据示例13至17中任何一项的半导体模块，其中，凹陷沿一个横向维度延伸直到包封体的相对的边缘。
示例19是根据示例18的半导体模块，其中，印刷电路板在包封体的相对的边缘之间延伸或者延伸超过包封体的相对的边缘中的一个或两个。
示例20是根据示例13至19中任何一项的半导体模块，其中，电连接器在凹陷的底表面处暴露。
此外，虽然可能仅相对于若干实施方式中的一个实施方式公开了本公开的实施例的特定特征或方面，但是这样的特征或方面可以与其它实施方式的一个或多个其它特征或方面相组合，这对于任何给定的或特定的应用可能是期望的和有利的。此外，就在详细描述或权利要求的任一个中使用术语“包括”、“具有”、“带有”或它们的其它变体而言，这些术语旨在以与术语“包括”类似的方式表示包含性的。此外，应该理解，可以在分立电路、部分集成的电路或完全集成的电路或编程模块中实现本公开的实施例。此外，术语“示例性的”仅意味着作为示例，而非最佳或最优。还应当理解，为了简单和易于理解的目的，本文描绘的特征和/或元件以相对于彼此的特定尺寸图示出，并且实际的尺寸可能与本文图示的尺寸实质上不相同。
虽然本文已经说明和描述了特定的实施例，但是本领域的普通技术人员将理解，可以用各种替代的和/或等同的实施方式代替所示和所描述的特定实施例，而不背离本公开的范围。本申请旨在涵盖本文讨论的特定实施例的任何修改或变化。因此，本公开旨在仅受权利要求及其等同物的限制。

Claims (20)

1.一种半导体封装(10；20)，包括：
衬底(11)；
设置在所述衬底(11)上的至少一个半导体管芯(12)；
与所述半导体管芯(12)连接的至少一个电连接器(13)；
覆盖所述衬底(11)、所述至少一个半导体管芯(12)并至少部分覆盖所述电连接器(13)的包封体(14)，所述包封体(14)包括形成到所述包封体(14)的主表面中的凹陷(14A)，
其中，所述至少一个电连接器(13)在所述凹陷(14A)内暴露。
2.根据权利要求1所述的半导体封装(10；20)，其中
所述半导体管芯(12)包括至少一个接触焊盘，并且所述电连接器(13)以它的两端与所述接触焊盘连接。
3.根据权利要求1所述的半导体封装(10；20)，还包括：
虚设焊盘，其中
所述半导体管芯(12)包括至少一个接触焊盘，并且所述电连接器(13)以一端与所述接触焊盘连接并以另一端与所述虚设焊盘连接。
4.根据前述权利要求中任何一项所述的半导体封装(10；20)，其中
所述半导体管芯(12)是包括源极焊盘、栅极焊盘和源极感测焊盘中的一个或多个的半导体晶体管管芯，并且所述电连接器(13)与所述源极焊盘、所述栅极焊盘或所述源极感测焊盘连接。
5.根据权利要求1所述的半导体封装(10；20)，其中
所述半导体管芯(12)包括分流器，并且所述电连接器与所述分流器连接。
6.根据前述权利要求中任何一项所述的半导体封装(10；20)，其中
所述电连接器(13)是导线、带或夹具中的一种。
7.根据前述权利要求中任何一项所述的半导体封装(10；20)，其中
所述凹陷(14A)的高度小于所述包封体(14)的高度的一半。
8.根据前述权利要求中任何一项所述的半导体封装(10；20)，还包括：
压配销、弹簧针或焊接焊盘中的一个或多个，所述压配销、弹簧针或焊接焊盘中的所述一个或多个中的一个连接到暴露的所述电连接器。
9.根据前述权利要求中任何一项所述的半导体封装(10；20)，其中
所述电连接器(13)的材料基于Al、Cu或Au。
10.根据前述权利要求中任何一项所述的半导体封装(10；20)，其中
所述半导体管芯(12)基于Si、SiC或GaN。
11.根据前述权利要求中任何一项所述的半导体封装(60)，其中
所述凹陷(64A)沿一个横向维度延伸直到所述包封体(64)的相对的边缘。
12.根据前述权利要求中任何一项所述的半导体封装(60)，其中
所述电连接器在所述凹陷的底表面处暴露。
13.一种半导体模块(100)，包括：
半导体封装(10)，包括：
衬底；
设置在所述衬底上的至少一个半导体管芯，所述半导体管芯包括至少一个电连接器；
覆盖所述衬底、所述至少一个半导体管芯并至少部分覆盖所述电连接器的包封体(14)，所述包封体(14)包括形成到所述包封体(14)的主表面中的凹陷(14A)；
其中，所述至少一个电连接器在所述凹陷(14A)内暴露；以及
设置在所述凹陷(14A)中或所述凹陷(14A)上的印刷电路板(50)，所述印刷电路板(50)包括设置在其上的栅极驱动器芯片(51)，所述栅极驱动器芯片(51)与暴露的所述电连接器电连接。
14.根据权利要求13所述的半导体模块(100)，其中
所述印刷电路板(50)还包括设置在其上的一个或多个无源器件，所述一个或多个无源器件至少部分地与暴露的所述电连接器电连接。
15.根据权利要求13或14所述的半导体模块(100)，其中
所述印刷电路板(50)通过压配销(21)、弹簧针或焊接焊盘中的一个或多个连接到所述包封体(14)，所述压配销(21)、弹簧针或焊接焊盘中的所述一个或多个中的一个连接到暴露的所述电连接器。
16.根据权利要求15所述的半导体模块(100)，其中
所述压配销、弹簧针或焊接焊盘中的一个或多个连接到暴露的所述电连接器。
17.根据权利要求13至16中任何一项所述的半导体模块(100)，其中
所述凹陷(14A)的高度小于所述包封体(14)的高度的一半。
18.根据权利要求13至17中任何一项所述的半导体模块(500)，其中
所述凹陷(64A)沿一个横向维度延伸直到所述包封体(64)的相对的边缘。
19.根据权利要求18所述的半导体模块(500；600)，其中
所述印刷电路板(450；550)在所述包封体的所述相对的边缘之间延伸或者延伸超过所述包封体(64)的所述相对的边缘中的一个或两个。
20.根据权利要求13至19中任何一项所述的半导体模块(500)，其中
所述电连接器在所述凹陷的底表面处暴露。
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