CN115910790A - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN115910790A CN115910790A CN202211316325.1A CN202211316325A CN115910790A CN 115910790 A CN115910790 A CN 115910790A CN 202211316325 A CN202211316325 A CN 202211316325A CN 115910790 A CN115910790 A CN 115910790A
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Abstract
In the semiconductor structure and the manufacturing method thereof provided by the invention, the drift region formed in the N-type deep well region in the PLDMOS device is along the direction far away from the top surface of the substrate, and the ion implantation concentration of the drift region is increased after being reduced. Therefore, the breakdown voltage of the PLDMOS device can be improved, the on-resistance can be reduced, and the performance of the PLDMOS device can be improved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a semiconductor structure and a method for manufacturing the same.
Background
The LDMOS is currently widely used in power management circuits due to its advantages of high voltage resistance, large current driving capability, very low power consumption, and integration with CMOS. The breakdown voltage and the on-resistance of the middle-high voltage PLDMOS are important electrical indexes of the device.
Fig. 1 is a schematic structural diagram of a middle-high voltage PLDMOS device in the prior art, and as shown in fig. 1, in the middle-high voltage PLDMOS device in the prior art, a substrate 1 is a P-type substrate, a deep well region 11 is formed in the substrate 1, the deep well region 11 is an N-type deep well, and each structure of the middle-high voltage PLDMOS device is formed in the deep well region 11 to realize isolation from the P-type substrate. The drift region 12 adopts a P-type deep well to realize higher breakdown voltage, and the deep well region 11 is used as a device channel region and has a depth greater than that of the drift region 12. If the concentration of ion implantation in the drift region 12 formed by the P-type deep well is low, the deep well region 11 formed by the N-type deep well below the drift region is not easy to be exhausted, and the breakdown voltage of the middle-high voltage PLDMOS device is not high; on the other hand, if the ion implantation concentration of the drift region 12 composed of the P-type deep well is high, although the depletion of the deep well region 11 composed of the N-type deep well below the drift region is increased, the drift region 12 composed of the P-type deep well cannot be completely depleted, and thus the breakdown voltage of the middle-high voltage PLDMOS device is still not high. Therefore, it is a long-term research topic of the skilled person to increase the breakdown voltage of the middle-high voltage PLDMOS device.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a manufacturing method thereof, and aims to solve the problem that in the prior art, the breakdown voltage and the on-resistance of a PLDMOS device cannot meet requirements at the same time, so that the performance of the PLDMOS device is low.
In order to solve the above problems, the present invention provides a semiconductor structure, wherein,
providing a substrate;
performing a first ion implantation process on the substrate to form a deep well region in the substrate;
forming a field oxide layer on the substrate, wherein the field oxide layer comprises a first field oxide structure and a second field oxide structure which are arranged at intervals;
performing a second ion implantation process on the substrate to form a drift region in the deep well region and locate the second field oxide structure in the drift region, wherein the depth of the drift region is less than that of the deep well region, and the ion implantation concentration of the drift region is increased after being decreased in a direction away from the top surface of the substrate;
and forming a gate polycrystalline silicon layer on the substrate, wherein the gate polycrystalline silicon layer is formed in the drift region.
Optionally, the drift region is divided into a first drift region, a second drift region and a third drift region in a direction away from the top surface of the substrate, wherein the ion implantation concentration of the first drift region is greater than the ion implantation concentration of the third drift region, and the ion implantation concentration of the third drift region is greater than the ion implantation concentration of the second drift region.
Optionally, an ion implantation amount of the first drift region is greater than an ion implantation amount of the third drift region, and an ion implantation amount of the third drift region is greater than an ion implantation amount of the second drift region.
Optionally, the ion implantation amount of the first drift region is at least 2e11 cm greater than that of the third drift region -2 。
Optionally, the ion implantation amount of the third drift region is at least 3e11 cm greater than that of the second drift region -2 。
Optionally, the ion implantation energy of the third drift region is greater than the ion implantation energy of the second drift region, and the ion implantation energy of the second drift region is greater than the ion implantation energy of the first drift region.
Optionally, the ion implantation energy of the third drift region is at least 300kev greater than the ion implantation energy of the second drift region.
Optionally, the ion implantation concentration of a region adjacent to the first drift region and the second drift region changes slowly, and/or the ion implantation concentration of a region adjacent to the second drift region and the third drift region changes slowly.
Optionally, after the gate polysilicon layer is formed, the method further includes:
performing a third ion implantation process to form a first heavily doped region and a second heavily doped region in the substrate, wherein the first heavily doped region is formed in the deep well region and located between the first field oxide structure and the gate polysilicon layer, and the second heavily doped region is formed in the drift region and located on the side of the second field oxide structure away from the gate polysilicon layer;
and executing a fourth ion implantation process to form a third heavily doped region in the substrate, wherein the third heavily doped region is formed in the deep well region and is positioned on one side of the first field oxide structure, which is far away from the polysilicon gate.
In addition, in order to solve the above problems, the present invention also provides a semiconductor structure prepared according to the method for manufacturing a semiconductor structure as described in any one of the above.
In the semiconductor structure and the manufacturing method thereof, the drift region formed in the N-type deep well region in the PLDMOS device is along the direction far away from the top surface of the substrate, and the ion implantation concentration of the drift region is increased after being reduced. Therefore, the breakdown voltage of the PLDMOS device can be improved, the on-resistance can be reduced, and the performance of the PLDMOS device can be improved.
Drawings
Fig. 1 is a schematic diagram of a prior art PLDMOS device structure;
FIG. 2 is a flow chart of a method of fabricating a semiconductor structure in an embodiment of the present invention;
fig. 3 to 7 are process diagrams of a method for fabricating a semiconductor structure according to an embodiment of the invention.
Wherein the reference numbers are as follows:
1-a substrate;
11-a deep well region;
12-a drift region; 121-a first drift region;
122-a second drift region; 123-a third drift region;
13-a first heavily doped region; 14-a second heavily doped region;
15-a third heavily doped region;
2-field oxygen layer;
21-a first field oxygen structure; 22-a second field oxygen structure;
3-a gate oxide layer;
a 4-gate polysilicon layer;
5-a metal plug layer; 51-a metal plug;
6-a metal electrode layer; 61-metal electrodes.
Detailed Description
A semiconductor structure and a method for fabricating the same according to the present invention are further described in detail with reference to the accompanying drawings and the embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are intended to be part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
FIG. 2 is a flow chart of a method of fabricating a semiconductor structure in an embodiment of the present invention; fig. 3 to 7 are process diagrams of a method for fabricating a semiconductor structure according to an embodiment of the invention. A method for manufacturing the semiconductor structure of the present embodiment is described below with reference to fig. 2 to 7.
In step S10, referring to fig. 2 in combination with fig. 3, a substrate 1 is provided.
In the present embodiment, the material forming the substrate 1 may include a semiconductor material, a conductor material, or any combination thereof; the substrate 1 may have a single-layer structure or a multi-layer structure. For example, the substrate 1 may be a semiconductor material such as Si, siGe, siGeC, siC, gaAs, inAs, inP, and other III/V or II/VI compound semiconductors; layered substrates such as, for example, si/SiGe, si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator may also be included.
In step S20, referring to fig. 2 in combination with fig. 3, a first ion implantation process is performed on the substrate 1 to form a deep well region 11 in the substrate 1.
In the present embodiment, the deep well region 11 is formed on the entire top surface of the substrate 1 and extends toward a direction away from the top surface of the substrate 1, and the depth of the deep well region 11 is smaller than the thickness of the substrate 1. In addition, in this embodiment, the ions implanted by the first ion implantation process are N-type ions, and the deep well region 11 is an N-type deep well. In addition, in the present embodiment, the substrate 1 is a P-type substrate.
In step S30, with continued reference to fig. 2 and with reference to fig. 4, a field oxide layer 2 is formed on the substrate 1, wherein the field oxide layer 2 includes a first field oxide structure 21 and a second field oxide structure 22. In this embodiment, the method for forming the field oxide layer 2 includes: and forming a mask layer on the substrate 1, etching and opening the field oxide region, and further growing a field oxide layer 2.
In step S40, with continuing reference to fig. 2 and with reference to fig. 5, a second ion implantation process is performed on the substrate 1 to form a drift region 12 in the deep well region 11 and locate the second field oxide structure 22 in the drift region 12, wherein the depth of the drift region 12 is smaller than the depth of the deep well region 11, and the ion implantation concentration of the drift region 12 is increased after being decreased in a direction away from the top surface of the substrate 1.
In this embodiment, since the drift region 12 formed in the N-type deep well region 11 in the PLDMOS device is along the direction away from the top surface of the substrate 1, the ion implantation concentration of the drift region 12 is increased after being decreased. Therefore, the breakdown voltage of the PLDMOS device can be improved, the on-resistance can be reduced, and the performance of the PLDMOS device can be improved.
Further, in this embodiment, the ions implanted by the second ion implantation process are P-type ions, the drift region is formed by a P-type deep well, and in this embodiment, the ion implantation concentration of the drift region 12 is increased after decreasing in a direction away from the top surface of the substrate 1 in the drift region 12. It can be understood that the ion implantation concentration of the drift region 12 tends to be high at both ends and low in the middle in the direction away from the top surface of the substrate 1. In this embodiment, the N-type ions include: phosphorus, arsenic or antimony ions. The P-type ions include: boron, gallium or indium ions.
Further, with continued reference to fig. 5 in conjunction with fig. 6, the drift region 12 is divided into a first drift region 121, a second drift region 122 and a third drift region 123 in a direction away from the top surface of the substrate, wherein the ion implantation concentration of the first drift region 121 is greater than the ion implantation concentration of the third drift region 123, and the ion implantation concentration of the third drift region 123 is greater than the ion implantation concentration of the second drift region 122.
The ion implantation amount of the first drift region 121 is greater than that of the third drift region 123, and the ion implantation amount of the third drift region 123 is greater than that of the second drift region 122. In addition to this, the present invention is,the ion implantation amount of the first drift region 121 is at least 2e11 cm greater than that of the third drift region 123 -2 . The ion implantation amount of the third drift region 123 is at least 3e11 cm larger than that of the second drift region 122 -2 。
Further, the ion implantation energy of the third drift region 123 is greater than the ion implantation energy of the second drift region 122, and the ion implantation energy of the second drift region 122 is greater than the ion implantation energy of the first drift region 121. In addition, the ion implantation energy of the third drift region 123 is at least 300kev greater than the ion implantation energy of the second drift region 122.
In addition, in the present embodiment, the ion implantation concentration of the region where the first drift region 121 and the second drift region 123 are adjacent changes slowly, and/or the ion implantation concentration of the region where the second drift region 122 and the third drift region 123 are adjacent changes slowly.
In step S50, as shown in fig. 5, a gate polysilicon layer 4 is formed on the substrate 1, and the gate polysilicon layer 4 is formed in the drift region 12.
In the present embodiment, a polysilicon material is deposited by a physical vapor deposition method to form the gate polysilicon layer 4. In addition, in this embodiment, before forming the gate polysilicon layer 4, the method further includes: a gate dielectric layer 3 is formed on the substrate 1, and the gate oxide layer 3 is at least positioned below the gate polysilicon gate layer 4. The gate dielectric layer 3 is formed by silicon oxide.
Further, with continued reference to fig. 5 in conjunction with fig. 7, the method further includes the following first step and second step after forming the gate polysilicon layer 4.
In the first step, a third ion implantation process is performed to form a first heavily doped region 13 and a second heavily doped region 14 in the substrate 1, wherein the first heavily doped region 13 is formed in the deep well region 11 and located between the first field oxide structure 21 and the gate polysilicon layer 4, and the second heavily doped region 14 is formed in the drift region 12 and located on a side of the second field oxide structure 22 away from the gate polysilicon layer 4.
Wherein, the ions implanted into the first heavily doped region 13 and the second heavily doped region 14 are P-type ions. In addition, the first heavily doped region 13 forms a source of the PLDMOS, and the second heavily doped region 14 forms a drain of the PLDMOS.
In the second step, a fourth ion implantation process is performed to form a third heavily doped region 15 in the substrate 1, where the third heavily doped region 15 is formed in the deep well region 11 and located on a side of the first field oxide structure 21 away from the gate polysilicon gate 4. In this embodiment, the third heavily doped region 15 constitutes the body contact region of the PLDMOS.
Further, with continued reference to fig. 7, after the fourth ion implantation process is performed, the method further includes the following steps.
Firstly, a metal plug layer 5 is formed, wherein the metal plug layer 5 includes a plurality of metal plugs 51, and one metal plug 51 is correspondingly disposed in each of the first heavily doped region 14, the second heavily doped region 15, and the third heavily doped region 16.
Next, a metal electrode layer 6 is formed on the metal plug layer 5, the metal electrode layer 6 includes a plurality of metal electrodes 61, and the metal electrodes 61 and the metal plugs 51 are electrically connected in a one-to-one correspondence. In the present embodiment, the material forming the metal plug layer 5 and the metal electrode 6 is copper.
Further, in the present embodiment, a semiconductor structure is also provided, and the semiconductor structure is prepared by the above-mentioned manufacturing method of the semiconductor structure.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
performing a first ion implantation process on the substrate to form a deep well region in the substrate;
forming a field oxide layer on the substrate, wherein the field oxide layer comprises a first field oxide structure and a second field oxide structure which are arranged at intervals;
performing a second ion implantation process on the substrate to form a drift region in the deep well region and locate the second field oxide structure in the drift region, wherein the depth of the drift region is less than that of the deep well region, and the ion implantation concentration of the drift region is increased after being decreased in a direction away from the top surface of the substrate;
and forming a gate polysilicon layer on the substrate, wherein the gate polysilicon layer is formed in the drift region.
2. The method of claim 1, wherein the drift region is divided into a first drift region, a second drift region and a third drift region in a direction away from the top surface of the substrate, wherein the first drift region has an ion implantation concentration greater than that of the third drift region, and wherein the third drift region has an ion implantation concentration greater than that of the second drift region.
3. The method of claim 2, wherein an ion implantation amount of the first drift region is greater than an ion implantation amount of the third drift region, and the ion implantation amount of the third drift region is greater than an ion implantation amount of the second drift region.
4. The method of claim 3, wherein an ion implantation amount of the first drift region is at least 2e11 cm greater than an ion implantation amount of the third drift region -2 。
5. The method of claim 3, wherein the third drift region is implanted with a greater ion implantation dose than the second drift regionThe ion implantation amount of the drift region is at least 3e11 cm larger -2 。
6. The method of claim 2, wherein an ion implantation energy of the third drift region is greater than an ion implantation energy of the second drift region, and the ion implantation energy of the second drift region is greater than an ion implantation energy of the first drift region.
7. The method of claim 2, wherein an ion implantation energy of the third drift region is at least 300kev greater than an ion implantation energy of the second drift region.
8. The method of claim 2, wherein an ion implantation concentration in a region adjacent to the first drift region and the second drift region varies slowly, and/or an ion implantation concentration in a region adjacent to the second drift region and the third drift region varies slowly.
9. The method of fabricating a semiconductor structure of claim 1, wherein after forming the gate polysilicon layer, the method further comprises:
performing a third ion implantation process to form a first heavily doped region and a second heavily doped region in the substrate, wherein the first heavily doped region is formed in the deep well region and is positioned between the first field oxide structure and the gate polysilicon layer, and the second heavily doped region is formed in the drift region and is positioned on one side of the second field oxide structure away from the gate polysilicon layer;
and executing a fourth ion implantation process to form a third heavily doped region in the substrate, wherein the third heavily doped region is formed in the deep well region and is positioned on one side of the first field oxide structure, which is far away from the polysilicon gate.
10. A semiconductor structure, characterized in that it is prepared according to the method for manufacturing a semiconductor structure according to any one of claims 1 to 9.
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| CN202211316325.1A CN115910790A (en) | 2022-10-26 | 2022-10-26 | Semiconductor structure and manufacturing method thereof |
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| CN202211316325.1A CN115910790A (en) | 2022-10-26 | 2022-10-26 | Semiconductor structure and manufacturing method thereof |
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