CN115910190A - Chip yield prediction method and device and computer readable storage medium - Google Patents
Chip yield prediction method and device and computer readable storage medium Download PDFInfo
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Abstract
The invention provides a chip yield prediction method, a chip yield prediction device and a computer readable storage medium. The method comprises the following steps: selecting a first preset number of chips meeting the process angle range; performing electrical test on the selected chip to obtain electrical parameters of each test item of each chip; calculating the position probability of each chip; calculating probability difference between two adjacent chips of a plurality of groups of position probabilities according to the position probability of each chip; for each test item, interpolating the electrical parameters of the two chips adjacent to each group of position probabilities according to the probability difference between the two chips adjacent to each group of position probabilities until a sample comprising a second preset number of electrical parameters is generated; and performing yield calculation according to the samples of the second preset number of electrical parameters corresponding to each test item. The invention can improve the reliability and the precision of the chip yield prediction.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for predicting chip yield, and a computer readable storage medium.
Background
Before mass production of chips, the overall evaluation of the chip production process is required, including specification setting, yield estimation, capacity arrangement and the like. The chip production process actually fluctuates, and the fluctuation conforms to the normal distribution. How to accurately predict the process distribution of mass-produced chips from a small number of chip samples and perform yield prediction is a difficult but compelling task. Especially for a brand-new product, the accuracy of yield prediction can directly influence the specification formulation and capacity arrangement of the product, and finally the market competitiveness and the yield of the product can be influenced.
At present, when chip yield is predicted, the reliability and precision of prediction are not high.
Disclosure of Invention
The chip yield prediction method, the chip yield prediction device and the computer readable storage medium can improve the reliability and the precision of the chip yield prediction.
In a first aspect, the present invention provides a method for predicting chip yield, the method comprising:
selecting a first preset number of chips meeting the process angle range;
performing electrical test on the selected chips to obtain electrical parameters of each test item of each chip;
calculating the position probability of each chip;
calculating probability differences between two chips adjacent to each other according to the position probability of each chip;
for each test item, interpolating the electrical parameters of the two chips adjacent to each group of position probabilities according to the probability difference between the two chips adjacent to each group of position probabilities until a sample comprising a second preset number of electrical parameters is generated;
and performing yield calculation according to the samples of the second preset number of electrical parameters corresponding to each test item.
Optionally, the selecting a first predetermined number of chips satisfying a process corner range includes: selecting a first predetermined number of chips with the electrical property of the NMOS and the PMOS in a preset range and evenly distributed on a scatter diagram.
Optionally, the calculating the position probability of each chip includes: and calculating the N-tube probability and the P-tube probability of the chip, and multiplying the N-tube probability and the P-tube probability to obtain the position probability of the chip.
Optionally, the calculating, according to the position probability of each chip, a probability difference between two chips adjacent to the plurality of groups of position probabilities includes: and for two chips adjacent to each group of position probability, the position probabilities of the two chips are differed to obtain the probability difference between the two chips.
Optionally, the interpolating the electrical parameters of the two chips adjacent to each group of position probabilities according to the probability difference between the two chips adjacent to each group of position probabilities includes: and interpolating the electrical parameters of the two chips adjacent to each group of position probabilities according to an arithmetic progression, an exponential progression or a logarithmic progression.
Optionally, interpolating, according to an arithmetic progression, electrical parameters of two chips adjacent to each group of position probabilities according to a probability difference between the two chips adjacent to each group of position probabilities includes: and determining a step length used for performing arithmetic series interpolation according to the probability difference between the two chips, the second preset number and the electrical parameters of the two chips, and performing arithmetic series interpolation on the electrical parameters of the two chips according to the step length.
In a second aspect, the present invention provides a chip yield prediction apparatus, comprising:
the selection unit is used for selecting a first preset number of chips meeting the process angle range;
the test unit is used for carrying out electrical test on the selected chip to obtain electrical parameters of each test item of each chip;
a first calculation unit for calculating a position probability of each chip;
a second calculation unit for calculating probability differences between two chips adjacent to each other in the plurality of groups of position probabilities, based on the position probability of each chip;
the interpolation unit is used for interpolating the electrical parameters of the two chips adjacent to each group of position probabilities according to the probability difference between the two chips adjacent to each group of position probabilities for each test item until a sample comprising a second preset number of electrical parameters is generated;
the yield calculation unit is used for performing yield calculation according to the samples of the second preset number of electrical parameters corresponding to each test item.
Optionally, the first calculating unit, configured to calculate the position probability of each chip, includes: and calculating the N-tube probability and the P-tube probability of the chip, and multiplying the N-tube probability and the P-tube probability to obtain the position probability of the chip.
Optionally, the second calculating unit is configured to, for two chips adjacent to each group of position probabilities, perform a difference between the position probabilities of the two chips to obtain a probability difference between the two chips.
Optionally, the interpolation unit is configured to interpolate the electrical parameters of the two chips adjacent to each group of position probabilities according to an arithmetic series, an exponential series, or a logarithmic series according to the probability difference between the two chips adjacent to each group of position probabilities.
Optionally, the interpolation unit is further configured to determine a step size used for performing arithmetic series interpolation according to the probability difference between the two chips, the second predetermined number, and the electrical parameters of the two chips, and perform arithmetic series interpolation on the electrical parameters of the two chips according to the step size.
In a third aspect, the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and when the computer instructions are executed by a processor, the computer instructions implement the chip yield prediction method.
According to the chip yield prediction method, the chip yield prediction device and the computer-readable storage medium, the statistical distribution rule is applied to the electrical distribution and interpolation processing is carried out according to the characteristic that the mass production process conforms to the statistical normal distribution, so that a large amount of electrical data conforming to the mass production distribution can be obtained according to a small batch of test samples, and further the product yield can be simulated and predicted.
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FIG. 1 is a flowchart illustrating a method for predicting a chip yield according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of selecting chips from the chips satisfying the process corner range according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of determining probability values in various distribution status ranges according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of calculating a probability difference between two chips according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a chip yield prediction apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
When predicting the yield of chips, the following two methods can be adopted:
mode 1: for new products with little change in product design and process, the electrical distribution of the new products can be generated by fine tuning according to the existing products. Selecting a small amount of new and old samples with similar WAT (Wafer Acceptance Test) parameters, comparing other electrical parameters of the new and old samples, finding out the relationship between the new and old samples, and popularizing the relationship, so that the electrical parameters of the new product can be deduced according to the electrical parameters of a large amount of old products, and the parameters are used as the input of a yield simulation program to finally calculate the yield prediction of the new product. However, the WAT and other electrical parameters testing methods are very different for new products with large variations in product design or process. On one hand, how to select new and old chip samples for comparison is an examination; another convenience is to generalize the relationship between a small number of new and old chips to a large number of chips, and the reliability and accuracy of this relationship are both issues.
Mode 2: the method for simulating the parameter loss yield of the integrated circuit by adopting the Monte Carlo analysis and the neural network regression analysis specifically comprises the following steps: and simulating the working characteristics based on the variables related to the semiconductor working characteristics, then carrying out neural network regression analysis by using the simulation result to obtain a variable function, and finally carrying out advanced Monte Carlo simulation on the variable function as input to predict the yield. However, for complex chips, yield-related variables are very numerous; in addition, the purely random variable simulation mode of Monte Carlo also faces a great challenge for the variables which are related to each other; moreover, this method requires a large amount of data, and is not accurate when predicting yield with a small lot of chips at the initial stage of mass production.
In order to solve the defects of low reliability and low precision when the chip yield prediction is performed by adopting the two methods, an embodiment of the invention provides a chip yield prediction method, as shown in fig. 1, the method includes:
s11, selecting a first preset number of chips meeting the process corner (corner) range.
And S12, performing electrical test on the selected chip to obtain electrical parameters of each test item of each chip.
And S13, calculating the position probability of each chip.
And S14, calculating the probability difference between two adjacent chips of a plurality of groups of position probabilities according to the position probability of each chip.
S15, for each test item, interpolating the electrical parameters of the two chips adjacent to each group of position probabilities according to the probability difference between the two chips adjacent to each group of position probabilities until a sample comprising a second preset number of electrical parameters is generated.
S16, performing yield calculation according to the samples of the second preset number of electrical parameters corresponding to each test item.
According to the chip yield prediction method provided by the embodiment of the invention, the statistical distribution rule is applied to the electrical distribution and interpolation processing is carried out according to the characteristic that the mass production process conforms to the statistical normal distribution, so that a large amount of electrical data conforming to the mass production distribution can be obtained according to a small batch of test samples, and the product yield is simulated and predicted.
The chip yield prediction method of the present invention will be described in detail with reference to the following embodiments.
In this embodiment, a small number of WAT parameters of chips satisfying a process angle range are selected, and a statistical rule is combined to deduce the characteristic distribution of mass production chips by interpolating the electrical parameters of a small number of chips. Since the characteristic relationship is derived from the new product, that is, the process design and the volume production of the chips satisfying the process angle range are the same, the reliability is not problematic, and the volume production process fluctuation is normally distributed, the statistical distribution of the volume production chips can be generated by simulating the electrical distribution of a small number of chips satisfying the process angle range, and the generated large amount of electrical data is used as the input of the yield calculation script to obtain the high-precision yield prediction through calculation.
The chip yield prediction method provided by the embodiment comprises the following steps:
and S21, selecting a certain number of chips from the chip pools meeting the process corner range.
Wherein the NMOS (N-type metal-oxide-semiconductor)/PMOS (P-type metal-oxide-semiconductor) electrical characteristics of the selected chip are uniformly distributed within 3sigma (process fluctuation range) and on the scatter plot, located at FF (fast NMOS fast, fast-fast, indicating that the circuit consists of fastest PMOS and fastest NMOS, defining the upper right corner of the process corner range)/FS (fast NMOS slow, indicating that the circuit consists of slowest PMOS and fastest NMOS, defining the upper left corner of the process corner range)/TT (typicaltypicality, indicating that the circuit consists of typicals and typical NMOS, defining the center of the process corner range)/SF (slow-fast, indicating that the circuit consists of PMOS and slowest NMOS, defining the right/SS (slow/slow, slow-slow, indicating that the circuit consists of PMOS and slowest NMOS, defining the right/SS (slow/slow, slow-slow, indicating that the circuit consists of PMOS and slowest NMOS, defining the right/SS (slow, slow-PMOS slow, indicating that the circuit consists of PMOS and slowest NMOS), defining the process corner range, the conditions are defined as the chip, the selected process range, the lower corner range is defined as 2, the selected process corner range.
Wherein the process corner indicates that the process falls within this range during production, and characterizes the production process fluctuation.
And S22, carrying out electrical test on the selected chip to obtain electrical parameters of each test item of each chip.
The electrical parameters are parameters related to the chip yield, such as leakage, frequency, etc.
And S23, calculating the position probability of each chip.
Specifically, according to WAT data and target (mean)/sigma of N-pipe and P-pipe of the chip, calculating corresponding probability of N-pipe and P-pipe of each chip according to the following formula (1), and since N-pipe and P-pipe are independently distributed, multiplying the probability of N-pipe by the probability of P-pipe, and thus obtaining the position probability of the whole chip.
Wherein, target (mean) corresponds to μ in formula (1), and sigma corresponds to σ in formula (1).
If the random variable x follows a normal distribution with a position parameter of mu and a scale parameter of sigma, the probability density function is:
and S24, calculating the probability difference between two chips adjacent to each other according to the position probability of each chip.
Specifically, the calculation may be performed as follows:
the indefinite integral of the normally distributed probability density function is a non-elementary function called the error function:
the relation between the normal distribution probability density integral and the error function can be obtained by changing elements:
the value of the error function can be found by looking up a table, so that the probability values in the various distribution states can be known.
As shown in fig. 3, regions 1 and 2 are ranges of values within less than one standard deviation from the mean, and in a normal distribution, the range accounts for 68.26%; the ratio within two standard deviations was 95%, and the ratio within three standard deviations was 99.73%.
For example, as shown in fig. 4, if the position probability of the chip P1 is 0.85 and the position probability of the chip P6 is 0.91, the chip ratio between P1 and P6 is 0.91-0.85=0.06, i.e. statistically, 6% of the chip electrical properties are considered to be between P1 and P6 (within the circular ring indicated by the two arrows in fig. 4).
And S25, interpolating the electrical parameters of the two chips with adjacent position probabilities according to the test item 1.
Assuming that the electrical properties between P1 and P6 are distributed with equal differences, 10000 samples can be generated by the following operations, and for test item 1, the difference is calculated according to equation (4):
step test1 ＝(test1 p6 -test1 p1 )/(0.06*10000) (4)
wherein test1 p6 The electrical parameter, test1, of test item 1 for P6 p1 The electrical parameters of test item 1 of P1 are shown.
Then, the median of 600 test items 1 is inserted between P1 and P6 in the arithmetic progression (step).
In practice, an arithmetic series, an exponential series, a logarithmic series, or the like may be selected according to the relationship between the test item and the WAT to perform interpolation. The embodiment adopts arithmetic progression interpolation, and the error between small-range intervals is acceptable after verification.
And S26, repeating the operations S24 and S25 for the two chips adjacent to other test items and other groups of position probabilities until a sample comprising 10000 complete electrical parameters is obtained, and generating an electrical parameter sample pool.
And S27, taking the electrical parameter sample pool as the input of the yield simulation script, and calculating the yield of mass production so as to make corresponding product specifications later.
According to the chip yield prediction method provided by the embodiment of the invention, according to the characteristic that the mass production process conforms to the statistical normal distribution, a small number of chips are selected, corresponding electrical parameters are measured, and samples with corresponding proportions are inserted between the samples which are distributed adjacently by combining with the statistical distribution rule, so that the electrical distribution of the mass production process is obtained, and the product yield is simulated and predicted. The method needs a small number of samples, is simple to calculate, can greatly reduce the modeling difficulty, and improves the reliability and the precision of yield prediction, for example, the yield of a certain single chip package simulation is 92.6 percent, the actual measurement is 92.5 percent, and the precision meets the expectation.
An embodiment of the present invention further provides a device for predicting a chip yield, as shown in fig. 5, the device includes:
a selecting unit 11, configured to select a first predetermined number of chips that satisfy a process corner range;
the test unit 12 is configured to perform an electrical test on the selected chip to obtain electrical parameters of each test item of each chip;
a first calculation unit 13 for calculating a position probability of each chip;
a second calculation unit 14 for calculating a plurality of sets of probability differences between two chips adjacent to each other in position probability according to the position probability of each chip;
the interpolation unit 15 is configured to interpolate, for each test item, the electrical parameters of the two chips adjacent to each group of position probabilities according to a probability difference between the two chips adjacent to each group of position probabilities until a sample including a second predetermined number of electrical parameters is generated;
the yield calculation unit 16 is configured to perform yield calculation according to a second predetermined number of samples of the electrical parameters corresponding to each test item.
According to the chip yield prediction device provided by the embodiment of the invention, the statistical distribution rule is applied to the electrical distribution and interpolation processing is carried out according to the characteristic that the mass production process accords with the statistical normal distribution, so that a large amount of electrical data which accords with the mass production distribution can be obtained according to a small batch of test samples, and then the product yield is simulated and predicted.
Optionally, the first calculating unit 13, configured to calculate the position probability of each chip, includes: and calculating the N-tube probability and the P-tube probability of the chip, and multiplying the N-tube probability and the P-tube probability to obtain the position probability of the chip.
Optionally, the second calculating unit 14 is configured to, for two chips adjacent to each group of position probabilities, perform a difference between the position probabilities of the two chips to obtain a probability difference between the two chips.
Optionally, the interpolation unit 15 is configured to interpolate the electrical parameters of the two chips adjacent to each group of position probabilities according to an arithmetic sequence, an exponential sequence, or a logarithmic sequence according to the probability difference between the two chips adjacent to each group of position probabilities.
Optionally, the interpolation unit 15 is further configured to determine a step size used for performing arithmetic series interpolation according to the probability difference between the two chips, the second predetermined number, and the electrical parameters of the two chips, and perform arithmetic series interpolation on the electrical parameters of the two chips according to the step size.
The apparatus of this embodiment may be configured to implement the technical solutions of the above method embodiments, and the implementation principles and technical effects are similar, which are not described herein again.
The embodiment of the invention also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are executed by a processor to realize the chip yield prediction method.
It will be understood by those skilled in the art that all or part of the processes of the embodiments of the methods described above may be implemented by a computer program, which may be stored in a computer readable storage medium and executed by a computer, and the processes of the embodiments of the methods described above may be included in the programs. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (12)
1. A method for predicting chip yield, the method comprising:
selecting a first preset number of chips meeting the process angle range;
performing electrical test on the selected chip to obtain electrical parameters of each test item of each chip;
calculating the position probability of each chip;
calculating probability difference between two adjacent chips of a plurality of groups of position probabilities according to the position probability of each chip;
for each test item, interpolating the electrical parameters of the two chips adjacent to each group of position probabilities according to the probability difference between the two chips adjacent to each group of position probabilities until a sample comprising a second preset number of electrical parameters is generated;
and performing yield calculation according to the samples of the second preset number of electrical parameters corresponding to each test item.
2. The method of claim 1, wherein selecting the first predetermined number of chips satisfying the process corner range comprises: selecting a first preset number of chips with the electrical property of NMOS and PMOS in a preset range and evenly distributed on a scatter diagram.
3. The method of claim 1, wherein calculating the position probability for each chip comprises: and calculating the N-tube probability and the P-tube probability of the chip, and multiplying the N-tube probability and the P-tube probability to obtain the position probability of the chip.
4. The method of claim 3, wherein calculating probability differences between two chips adjacent to each other according to the position probabilities of each chip comprises: and for two chips adjacent to each group of position probability, the position probabilities of the two chips are differed to obtain the probability difference between the two chips.
5. The method according to any one of claims 1 to 4, wherein the interpolating the electrical parameters of the two chips adjacent to each group of position probabilities according to the probability difference between the two chips adjacent to each group of position probabilities comprises: and according to the probability difference between the two chips adjacent to each group of position probabilities, interpolating the electrical parameters of the two chips adjacent to each group of position probabilities according to an arithmetic progression, an exponential progression or a logarithmic progression.
6. The method of claim 5, wherein interpolating the electrical parameters of the two chips adjacent to each group of position probabilities according to an arithmetic progression based on the probability difference between the two chips adjacent to each group of position probabilities comprises: and determining a step length used for performing arithmetic series interpolation according to the probability difference between the two chips, the second preset number and the electrical parameters of the two chips, and performing arithmetic series interpolation on the electrical parameters of the two chips according to the step length.
7. A chip yield prediction apparatus, the apparatus comprising:
the selecting unit is used for selecting a first preset number of chips meeting the process angle range;
the test unit is used for carrying out electrical test on the selected chip to obtain electrical parameters of each test item of each chip;
a first calculation unit for calculating a position probability of each chip;
a second calculation unit for calculating probability differences between two chips adjacent to each other in the plurality of groups of position probabilities, based on the position probability of each chip;
the interpolation unit is used for interpolating the electrical parameters of the two chips adjacent to each group of position probabilities according to the probability difference between the two chips adjacent to each group of position probabilities for each test item until a sample comprising a second preset number of electrical parameters is generated;
the yield calculation unit is used for performing yield calculation according to the samples of the second preset number of electrical parameters corresponding to each test item.
8. The apparatus of claim 7, wherein the first computing unit configured to compute the position probability of each chip comprises: and calculating the N-tube probability and the P-tube probability of the chip, and multiplying the N-tube probability and the P-tube probability to obtain the position probability of the chip.
9. The apparatus of claim 8, wherein the second computing unit is configured to, for two chips adjacent to each group of position probabilities, difference the position probabilities of the two chips to obtain a probability difference between the two chips.
10. The apparatus according to any one of claims 7 to 9, wherein the interpolation unit is configured to interpolate the electrical parameters of the two chips adjacent to each group of position probabilities according to an arithmetic sequence, an exponential sequence, or a logarithmic sequence based on the probability difference between the two chips adjacent to each group of position probabilities.
11. The apparatus of claim 10, wherein the interpolation unit is further configured to determine a step size used for performing arithmetic series interpolation according to the probability difference between the two chips, the second predetermined number, and the electrical parameters of the two chips, and perform arithmetic series interpolation on the electrical parameters of the two chips according to the step size.
12. A computer readable storage medium, wherein the computer readable storage medium stores computer instructions which, when executed by a processor, implement the method of any one of claims 1 to 6.
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| CN114461466A (en) * | 2021-12-31 | 2022-05-10 | 唐山捷准芯测信息科技有限公司 | Method, device, equipment and storage medium for fine tuning of reference circuit of flash memory chip |
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| CN110209542A (en) * | 2019-05-21 | 2019-09-06 | 苏州浪潮智能科技有限公司 | A kind of internal storage testing method based on Naive Bayes Classifier |
| CN113933672A (en) * | 2021-09-18 | 2022-01-14 | 杭州广立微电子股份有限公司 | Method and system for judging correlation of wafer test parameters |
| CN114461466A (en) * | 2021-12-31 | 2022-05-10 | 唐山捷准芯测信息科技有限公司 | Method, device, equipment and storage medium for fine tuning of reference circuit of flash memory chip |
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