CN115907020A - Quantum calculation circuit and quantum computer - Google Patents
Quantum calculation circuit and quantum computer Download PDFInfo
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- CN115907020A CN115907020A CN202110941249.2A CN202110941249A CN115907020A CN 115907020 A CN115907020 A CN 115907020A CN 202110941249 A CN202110941249 A CN 202110941249A CN 115907020 A CN115907020 A CN 115907020A
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Abstract
The application discloses quantum computing circuit and quantum computer belongs to quantum computing technology field. The quantum bit circuit comprises a plurality of quantum bit circuits, adjacent quantum bit circuits are coupled, and the quantum bit circuit comprises: a first capacitor, a first end of the first capacitor is grounded; a second capacitor, a first end of the second capacitor and a first end of the first capacitor are connected to the ground in common; and the first device comprises a first superconducting quantum interferometer and a third capacitor which are connected in parallel, the first end of the first superconducting quantum interferometer and the first end of the third capacitor which are connected in parallel are connected with the second end of the first capacitor, and the second end of the first superconducting quantum interferometer and the second end of the third capacitor which are connected in parallel are connected with the second end of the second capacitor. The parameter of at least one electric capacity in a plurality of electric capacities in the quantum bit circuit can be adjusted to this application to the design of electric capacity is comparatively nimble, and the space limitation is little, is convenient for the design and the arrangement of other circuit structure.
Description
Technical Field
The application belongs to the field of quantum information, particularly relates to the technical field of quantum computing, and particularly relates to a quantum computing circuit and a quantum computer.
Background
Quantum computers are physical devices that perform high-speed mathematical and logical operations, store and process quantum information in compliance with the laws of quantum mechanics. The quantum computer is characterized by high running speed, strong information processing capability, wide application range and the like. Compared with a common computer, the more information processing amount is, the more beneficial the quantum computer to implement operation is, and the more accurate the operation can be ensured.
The superconducting quantum computing can prepare quantum bits on a substrate by utilizing a micro-nano processing technology, and has superior performances of integration, expandability and the like. At present, a capacitor with one end grounded and a superconducting quantum interferometer connected with the capacitor in parallel are commonly adopted for a quantum bit in a quantum computing circuit, and certain space limitations exist in the design and manufacture of the quantum computing circuit only by using the structure, for example, the parameters of the capacitor in the structure are relatively fixed, which easily influences the design and arrangement of other circuit structures.
Summary of the invention
The quantum computing circuit adopts a first capacitor and a second capacitor, one end of the first superconducting quantum interferometer connected with the third capacitor in parallel is connected with the first capacitor, the other end of the first superconducting quantum interferometer connected with the third capacitor in parallel is connected with the second capacitor, and the structure facilitates design and arrangement of other circuit structures.
One embodiment of the present application provides a quantum computing circuit, including a plurality of qubit circuits, and coupling between adjacent ones of the qubit circuits, the qubit circuits including:
a first capacitor, a first end of the first capacitor is grounded;
a second capacitor, a first end of the second capacitor and a first end of the first capacitor are connected to the ground in common; and
the first device comprises a first superconducting quantum interferometer and a third capacitor which are connected in parallel, a first end of the first superconducting quantum interferometer and a first end of the third capacitor which are connected in parallel are connected with a second end of the first capacitor, and a second end of the first superconducting quantum interferometer and a second end of the third capacitor which are connected in parallel are connected with a second end of the second capacitor.
In the quantum computing circuit, a frequency tunable coupling circuit is connected between adjacent qubit circuits.
In the quantum computing circuit, the coupling circuit comprises a fourth capacitor with one end grounded and a second superconducting quantum interferometer connected with the fourth capacitor in parallel.
The quantum computing circuit as described above, the second superconducting quantum interferometer comprising at least two josephson junctions connected in parallel between the josephson junctions.
In the quantum computing circuit described above, the number of josephson junctions in the second superconducting quantum interferometer is an odd number.
In the quantum computing circuit, the josephson junction is a tunnel junction, a point contact or other structures showing josephson effect.
The quantum computing circuit as described above, further comprising a read circuit coupled with the qubit circuit.
In the quantum computing circuit, the reading circuit comprises a fifth capacitor with one end grounded and an inductor connected with the fifth capacitor in parallel.
The quantum computing circuit as described above, the read circuit being capacitively coupled with the qubit circuit.
In the quantum computing circuit, the capacitance value C of the first capacitor 1 A capacitance value C of the second capacitor 2 And a capacitance value C of said third capacitor 3 The following relationship is satisfied:
C 1 ＝C 2 eyes of people
An embodiment of the present application also provides a quantum computer provided with at least the quantum computing circuit as described above.
Compared with the prior art, the quantum computing circuit of this application, including a plurality of qubit circuits, and adjacent couple between the qubit circuit, the qubit circuit includes first electric capacity, second electric capacity and first device, and the first end of first electric capacity and the first end of second electric capacity are earthed jointly, and first device includes parallelly connected first superconducting quantum interferometer and third electric capacity, just first superconducting quantum interferometer with the parallelly connected first end of third electric capacity with the second end of first electric capacity is connected, parallelly connected second end with the second end of second electric capacity is connected. In the scheme of this application, the qubit circuit has contained a plurality of electric capacities, influence the dissonance of qubit energy level system through a plurality of electric capacities, compare in the quantum computing circuit among the prior art, the selection combination mode of electric capacity is comparatively nimble among the qubit circuit of this application, under the circumstances that the dissonance parameter of qubit energy level system is confirmed, can adjust the parameter of at least one electric capacity among a plurality of electric capacities as required, this kind of structure avoids the qubit to adopt the electric capacity of an one end ground connection and produced space limitation when the superconductive quantum interferometer of this electric capacity parallel connection in the qubit computing circuit of prior art, therefore, the scheme of this application is convenient for the design and the arrangement of other circuit structures.
Drawings
FIG. 1 is a diagram illustrating a quantum computing circuit according to the related art;
fig. 2 is a schematic diagram of a quantum computing circuit according to an embodiment of the present disclosure.
Detailed Description
The following detailed description is merely illustrative and is not intended to limit the embodiments and/or the application or uses of the embodiments. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding "background" or "summary" sections or "detailed description" sections.
To further clarify the objects, aspects and advantages of embodiments of the present application, one or more embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It may be evident, however, that one or more embodiments may be practiced in various instances without these specific details, and that the various embodiments may be incorporated by reference into each other without departing from the scope of the present disclosure.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the foregoing drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be implemented in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
According to different physical systems adopted for constructing the qubits, the qubits include superconducting quantum circuits, semiconductor quantum dots, ion traps, diamond vacancies, topological quanta, photons and the like in a physical implementation manner.
The superconducting quantum circuit is the best solid quantum computing implementation method at present. Because the energy level structure of the superconducting quantum circuit can be regulated and controlled by an external electromagnetic signal, the controllability of the design customization of the circuit is strong. Meanwhile, the quantum computing based on the superconducting quantum circuit has the scalability which is incomparable to most quantum physical systems due to the existing mature integrated circuit technology.
Fig. 1 is a schematic diagram of a quantum computing circuit in the related art.
Referring to fig. 1, in a conventional qubit calculation circuit, a capacitor C with one end grounded is used in the qubit calculation circuit q And the capacitor C q Circuit structure of parallel connected superconducting quantum interferometer Squid, capacitor C q Influences the non-harmonicity of the quantum bit, determines the non-harmonicity parameter of the quantum bit and the capacitance C when the quantum circuit is designed q That is, it is determined that since each element occupies a certain space, if we consider only the design and arrangement of a quantum computing circuit using such a circuit structure, that isCertain space limitations may be caused, and sufficient space cannot be reserved for other circuit structures or elements, thereby affecting the design and arrangement of other circuit structures.
Therefore, the quantum computing circuit and the quantum computer provided by the application solve the defects in the prior art, the quantum bit circuit in the quantum computing circuit adopts a structure that one end of a first capacitor and one end of a second capacitor are grounded, one end of a first superconducting quantum interferometer and one end of a third capacitor are connected in parallel with each other and are connected with the other end of the first capacitor, and the other end of the second capacitor is connected with the other end of the second capacitor in parallel, the capacitance combination mode of the quantum bit circuit in the structure is flexible, the parameter of at least one capacitor of a plurality of capacitors in the quantum bit circuit can be adjusted according to needs under the condition that the non-harmonic parameters of a quantum bit energy level system are determined, and compared with the structural form of the quantum computing circuit in the prior art, the scheme provided by the application can avoid the spatial limitation existing in the quantum computing circuit in the prior art, and is convenient for the design and arrangement of other circuit structures.
Fig. 2 is a schematic diagram of a quantum computing circuit according to an embodiment of the present disclosure.
Referring to fig. 2, an embodiment of the present application provides a qubit calculation circuit including a plurality of qubit circuits, and coupling between adjacent ones of the qubit circuits in a manner that can be coupled via a capacitive coupling or a resonant circuit, the qubit calculation circuit including:
a first capacitor C 1 Said first capacitor C 1 The first end of (1) is grounded;
second capacitor C 2 Said second capacitor C 2 And the first terminal of the first capacitor C 1 Are grounded; and
a first device comprising a first superconducting quantum interferometer Sq1 and a third capacitor C connected in parallel 3 And said first superconducting quantum interferometer Sq1 and said third capacitance C 3 A first end connected in parallel with the first capacitor C 1 Said first superconductor is connected toQuantum interferometer Sq1 and the third capacitance C 3 A second terminal connected in parallel with the second capacitor C 2 Is connected to the second end of the first housing.
In the quantum computing circuit provided by the embodiment of the application, the qubit circuit comprises a plurality of capacitors, the non-harmonicity of the qubit level system is influenced by the plurality of capacitors, compared with the quantum computing circuit in the prior art, the selection and combination mode of the capacitors in the qubit circuit is flexible, at least one of the plurality of capacitors in the qubit circuit can be adjusted as required under the condition that the non-harmonicity parameter of the qubit level system is determined, for example, the capacitance parameter is adjusted, the quantum computing circuit provided by the embodiment of the application can reserve enough space for other circuit structures or elements, and the space limitation caused when the qubit in the quantum computing circuit in the prior art only adopts one capacitor with one grounded end and a superconducting quantum interferometer connected in parallel with the capacitor is avoided, so that the design and the arrangement of other circuit structures are facilitated.
Referring to fig. 2 and fig. 1, in the case where the dissonance parameter of the qubit energy level system in the embodiment of the present application is the same as the dissonance parameter of the qubit energy level system in fig. 1, the first capacitor C in the embodiment of the present application 1 A second capacitor C 2 And a third capacitance C 3 As long as it satisfies
With respect to the structure of the qubit in fig. 1, the qubit in the embodiment of the present application includes a plurality of capacitors, and when designing the quantum chip, each capacitor may be designed and arranged according to practical situations (for example, considering the size of the reading resonant cavity, etc.), as long as the first capacitor C is used 1 A second capacitor C 2 And a third capacitance C 3 Combined equivalent capacitance and C q That is, illustratively, the capacitance value C of the first capacitor 1 A capacitance value C of the second capacitor 2 And a capacitance value C of said third capacitor 3 Satisfy C 1 ＝C 2 ＝2C q And &>
At this time, the capacitance C is compared with that in FIG. 1 q Based on the structure adopted in the embodiment of the present application, a quantum computing circuit is constructed on a substrate (e.g., a dielectric substrate such as silicon, sapphire, etc.), and the first capacitor C can be formed 1 And a second capacitor C 2 The physical size of the corresponding polar plate is enlarged, so that a larger space can be reserved, and the design and the arrangement of other circuit structures are facilitated.
The quantum computing circuit is constructed on a substrate (e.g., a dielectric substrate such as silicon, sapphire, etc.) based on the structure adopted in the embodiments of the present application, and specifically, a first capacitor plate, a second capacitor plate, and the first superconducting quantum interferometer are formed on the substrate based on an existing mature integrated circuit process, the first capacitor plate and the second capacitor plate are not directly connected to a ground plane (GND), but have a suitable gap with the ground plane GND, the physical size of the gap is determined according to the performance parameters of the quantum computing circuit, and it is noted that the first capacitor C is formed between the first capacitor plate and the ground plane (GND) 1 Said second capacitor C is formed between the second capacitor plate and the ground plane (GND) 2 The third capacitor C is formed between the first capacitor plate and the second capacitor plate 3 Calculating and determining the first capacitance C according to the performance parameters of the quantum computing circuit 1 A second capacitor C 2 And a third capacitance C 3 The first superconducting quantum interferometer is positioned between the first capacitor plate and the second capacitor plate, one end of the first superconducting quantum interferometer is connected with the first capacitor plate, the other end of the first superconducting quantum interferometer is connected with the second capacitor plate, the first capacitor plate, the second capacitor plate and the first superconducting quantum interferometer are surrounded by a ground plane (GND) and are separated from the ground plane (GND) through a gap exposing the surface of the substrate, the substrate can adopt a dielectric substrate such as silicon or sapphire, exemplarily, the first capacitor plate, the second capacitor plate, and the first superconducting quantum interferometer and the ground plane (GND) are formed on the silicon substrate, and the first capacitor plate, the second capacitor plate and the ground plane (GND) are formed on the silicon substrateThe two capacitor plates and the ground plane (GND) may be formed of a superconductor material exhibiting superconducting characteristics at a temperature equal to or lower than a critical temperature, for example, aluminum, niobium, titanium nitride, or the like, and the specific implementation is not limited thereto, and materials exhibiting superconducting characteristics at a temperature equal to or lower than a critical temperature may be used to form the first capacitor plate, the second capacitor plate, and the ground plane (GND).
In the embodiment provided by the application, the first capacitor may also be an equivalent capacitor formed by connecting a plurality of capacitor elements in series or in parallel, or by connecting a part of the capacitor elements in series and in parallel, and similarly, the second capacitor may also be an equivalent capacitor formed by connecting a plurality of capacitor elements in series or in parallel, or by connecting a part of the capacitor elements in series and in parallel, and the number and the electrical connection relationship of the capacitor elements may be determined as required.
In some embodiments, adjacent qubit circuits in the quantum computing circuit are connected through a tunable-frequency coupling circuit, and the tunable-frequency coupling circuit facilitates regulation and control of coupling strength between the adjacent qubit circuits, thereby facilitating implementation of a dual-quantum logic gate. For example, qubit circuit q1 and qubit circuit q2 are in adjacent positions, the coupling circuit is coupled to qubit circuit q1 and qubit circuit q2, respectively, resulting in indirect coupling between qubit circuit q1 and qubit circuit q2, and the coupling strength between qubit circuit q1 and qubit circuit q2 can be adjusted by adjusting the frequency of the coupling circuit. Wherein, as an example, the coupling circuit comprises a fourth capacitor C with one end grounded 4 And with said fourth capacitance C 4 A second superconducting quantum interferometer Sq2 connected in parallel. In some examples, the second superconducting quantum interferometer Sq2 includes at least two josephson junctions connected in parallel, and the frequency of the coupling circuit can be adjusted by an applied magnetic flux. In some examples, to obtain a second superconducting quantum interferometer Sq2 of asymmetric structure such that the frequency spectrum of the coupling circuit has at least two flux insensitive points, the number of josephson junctions in the second superconducting quantum interferometer Sq2 is odd. Similarly, the firstThe superconducting quantum interferometer Sq1 is similar to the second superconducting quantum interferometer and comprises at least two Josephson junctions, the Josephson junctions are connected in parallel, in order to obtain the first superconducting quantum interferometer Sq1 with an asymmetric structure so that the frequency spectrum of the qubit circuit has at least two flux insensitive points, and the number of the Josephson junctions in the first superconducting quantum interferometer Sq1 can also be selected to be an odd number.
By applying magnetic flux to qubit circuit q1 and qubit circuit q2, the applied magnetic flux directly affects the josephson energy of the qubit circuit, so that the frequency of the qubit circuit can be changed, and thus the frequency of the qubit circuit can be conveniently adjusted by adjusting the magnetic flux through the first superconducting quantum interferometer Sq 1. In the frequency tunable coupling circuit, the frequency of the coupling structure can be changed by changing the magnetic field generated by the current flowing through the Josephson junction in the second superconducting quantum interferometer Sq2. Based on this, the indirect coupling of the adjacent quantum bit circuit q1 and the quantum bit circuit q2 can be realized, and a foundation is laid for realizing the double-quantum logic gate.
In some embodiments, the josephson junction is a tunnel junction, a point contact, or other structure exhibiting josephson effect.
In some embodiments, the quantum computing circuit further comprises a reading circuit coupled to the qubit circuit for reading the regulated quantum state of the qubit circuit using the reading circuit. Wherein, as an example, the reading circuit comprises a fifth capacitor C with one end grounded 5 And with said fifth capacitance C 5 An inductor connected in parallel. In some examples, the read circuit is capacitively coupled with the qubit circuit. In an embodiment of the application, each qubit circuit has the reading circuit coupled thereto, and another end of the plurality of reading circuits is coupled to a common reading signal transmission line, and the reading signal transmission line acquires information of a quantum state through the reading circuit corresponding to each qubit.
The embodiment of the application also provides a quantum computer, wherein the quantum computer is a superconducting system and is at least provided with the quantum computing circuit.
Here, it should be noted that: the quantum computing circuit in the embodiments of the quantum computer has a similar structure to that in the embodiments of the quantum computing circuit, and has the same beneficial effects as the embodiments of the quantum computing circuit, and therefore, the description thereof is omitted. For technical details that are not disclosed in the quantum computer embodiments of the present application, those skilled in the art should refer to the description of the quantum computing circuit above for understanding, and for the sake of brevity, will not be described again here.
In combination with the description of the present document, compared with the prior art, the quantum computing circuit of the present application includes a plurality of qubit circuits, and adjacent ones of the qubit circuits are coupled to each other, and the qubit circuits include a first capacitor C 1 A second capacitor C 2 And a first device, a first capacitor C 1 First terminal of (2) and second capacitor C 2 Comprises a first superconducting quantum interferometer Sq1 and a third capacitor C connected in parallel 3 And said first superconducting quantum interferometer Sq1 and said third capacitance C 3 A first end connected in parallel with the first capacitor C 1 Is connected with the second end of the second capacitor C in parallel 2 Is connected to the second end of the first housing. In the quantum computing circuit of the present application, the qubit circuit includes a plurality of capacitors, the detuning of the qubit level system is affected by the plurality of capacitors, and compared with the quantum computing circuit in the prior art, the selection and combination manner of the capacitors in the qubit circuit of the present application is flexible, and the parameter of at least one capacitor in the plurality of capacitors can be adjusted as required under the condition that the detuning parameter of the qubit level system is determined, such a structure avoids the spatial limitation generated when the qubit in the quantum computing circuit of the prior art adopts a capacitor with one end grounded and a superconducting quantum interferometer connected in parallel with the capacitor, and thus, the scheme of the present application facilitates the design and arrangement of other circuit structures, for example, enough space is reserved for designing and arranging the read circuit and the regulation and control circuit of the qubit circuit (such as a flux regulation and control electric circuit (e.g., a flux regulation and control electric circuit)A way, a pulse conditioning circuit, not shown in the figure), etc. In the embodiment provided by the present application, the apparatus may include a magnetic flux control circuit, a pulse control circuit, and a read signal transmission line, the frequency of the qubit is adjusted to the working frequency by using a magnetic flux control signal on the magnetic flux control circuit, at this time, a quantum state control signal is applied by the pulse control circuit to perform quantum state control on the qubit in the initial state, the read circuit is used to read the quantum state of the regulated qubit 1, a read detection signal (for example, a microwave signal with a frequency of 4 to 8 GHz) is applied on the read signal transmission line coupled to the read circuit, and the quantum state in which the qubit is located is determined by analyzing a read feedback signal (a signal in response to the read detection signal) output by the read signal transmission line, and the magnetic flux control circuit, the pulse control circuit, and the read signal transmission line are not described herein again.
The construction, features and functions of the present application have been described in detail and illustrated in the drawings, the present application is not limited to the embodiments, but rather the invention is intended to cover all modifications, equivalents and equivalents falling within the spirit and scope of the present application.
Claims (11)
1. A qubit computation circuit comprising a plurality of qubit circuits, adjacent ones of the qubit circuits being coupled to each other, the qubit circuits comprising:
a first capacitor, a first end of the first capacitor is grounded;
a second capacitor, a first end of the second capacitor and a first end of the first capacitor are connected to the ground in common; and
the first device comprises a first superconducting quantum interferometer and a third capacitor which are connected in parallel, a first end of the first superconducting quantum interferometer and a first end of the third capacitor which are connected in parallel are connected with a second end of the first capacitor, and a second end of the first superconducting quantum interferometer and a second end of the third capacitor which are connected in parallel are connected with a second end of the second capacitor.
2. The quantum computing circuit of claim 1, wherein a frequency tunable coupling circuit is connected between adjacent qubit circuits.
3. A quantum computing circuit according to claim 2, wherein the coupling circuit comprises a fourth capacitor connected at one end to ground, and a second superconducting quantum interferometer connected in parallel with the fourth capacitor.
4. A quantum computing circuit according to claim 3, wherein the second superconducting quantum interferometer comprises at least two josephson junctions, and wherein the josephson junctions are connected in parallel.
5. A quantum computing circuit according to claim 4, wherein the number of Josephson junctions in the second superconducting quantum interferometer is an odd number.
6. A quantum computing circuit according to claim 4 or 5, wherein the Josephson junction is a tunnel junction, a point contact, or other structure exhibiting the Josephson effect.
7. The quantum computing circuit of claim 1, further comprising a read circuit coupled with the qubit circuit.
8. The quantum computing circuit of claim 7, wherein the read circuit comprises a fifth capacitor connected at one end to ground, and an inductor connected in parallel with the fifth capacitor.
9. A quantum computing circuit according to claim 7 or 8, wherein the read circuit is capacitively coupled to the qubit circuit.
10. A quantum computing circuit according to any of claims 1-5 and 7-8, wherein the capacitance value C of the first capacitor 1 A capacitance value C of the second capacitor 2 And a capacitance value C of said third capacitor 3 The following relationship is satisfied:
C 1 ＝C 2 and is and
11. a quantum computer, characterized in that it is provided with at least a quantum computing circuit according to claims 1-10.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110941249.2A CN115907020A (en) | 2021-08-17 | 2021-08-17 | Quantum calculation circuit and quantum computer |
| PCT/CN2022/108653 WO2023006041A1 (en) | 2021-07-30 | 2022-07-28 | Quantum circuit, quantum chip, and quantum computer |
| EP22848646.0A EP4328809A1 (en) | 2021-07-30 | 2022-07-28 | Quantum circuit, quantum chip, and quantum computer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110941249.2A CN115907020A (en) | 2021-08-17 | 2021-08-17 | Quantum calculation circuit and quantum computer |
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| Publication Number | Publication Date |
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| CN115907020A true CN115907020A (en) | 2023-04-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202110941249.2A Pending CN115907020A (en) | 2021-07-30 | 2021-08-17 | Quantum calculation circuit and quantum computer |
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| CN (1) | CN115907020A (en) |
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- 2021-08-17 CN CN202110941249.2A patent/CN115907020A/en active Pending
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